sdcc/device/non-free/lib/pic16/libdev/pic18lf26j11.c

   1 /*
   2  * This definitions of the PIC18LF26J11 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:54 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18lf26j11.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0EC6) __sfr RPOR0;
  30
  31 __at(0x0EC7) __sfr RPOR1;
  32
  33 __at(0x0EC8) __sfr RPOR2;
  34
  35 __at(0x0EC9) __sfr RPOR3;
  36
  37 __at(0x0ECA) __sfr RPOR4;
  38
  39 __at(0x0ECB) __sfr RPOR5;
  40
  41 __at(0x0ECC) __sfr RPOR6;
  42
  43 __at(0x0ECD) __sfr RPOR7;
  44
  45 __at(0x0ECE) __sfr RPOR8;
  46
  47 __at(0x0ECF) __sfr RPOR9;
  48
  49 __at(0x0ED0) __sfr RPOR10;
  50
  51 __at(0x0ED1) __sfr RPOR11;
  52
  53 __at(0x0ED2) __sfr RPOR12;
  54
  55 __at(0x0ED3) __sfr RPOR13;
  56
  57 __at(0x0ED4) __sfr RPOR14;
  58
  59 __at(0x0ED5) __sfr RPOR15;
  60
  61 __at(0x0ED6) __sfr RPOR16;
  62
  63 __at(0x0ED7) __sfr RPOR17;
  64
  65 __at(0x0ED8) __sfr RPOR18;
  66
  67 __at(0x0EE7) __sfr RPINR1;
  68
  69 __at(0x0EE8) __sfr RPINR2;
  70
  71 __at(0x0EE9) __sfr RPINR3;
  72
  73 __at(0x0EEA) __sfr RPINR4;
  74
  75 __at(0x0EEC) __sfr RPINR6;
  76
  77 __at(0x0EED) __sfr RPINR7;
  78
  79 __at(0x0EEE) __sfr RPINR8;
  80
  81 __at(0x0EF2) __sfr RPINR12;
  82
  83 __at(0x0EF3) __sfr RPINR13;
  84
  85 __at(0x0EF6) __sfr RPINR16;
  86
  87 __at(0x0EF7) __sfr RPINR17;
  88
  89 __at(0x0EFB) __sfr RPINR21;
  90
  91 __at(0x0EFC) __sfr RPINR22;
  92
  93 __at(0x0EFD) __sfr RPINR23;
  94
  95 __at(0x0EFE) __sfr RPINR24;
  96
  97 __at(0x0EFF) __sfr PPSCON;
  98 __at(0x0EFF) volatile __PPSCONbits_t PPSCONbits;
  99
 100 __at(0x0F3C) __sfr PADCFG1;
 101 __at(0x0F3C) volatile __PADCFG1bits_t PADCFG1bits;
 102
 103 __at(0x0F3D) __sfr REFOCON;
 104 __at(0x0F3D) volatile __REFOCONbits_t REFOCONbits;
 105
 106 __at(0x0F3E) __sfr RTCCAL;
 107 __at(0x0F3E) volatile __RTCCALbits_t RTCCALbits;
 108
 109 __at(0x0F3F) __sfr RTCCFG;
 110 __at(0x0F3F) volatile __RTCCFGbits_t RTCCFGbits;
 111
 112 __at(0x0F40) __sfr ODCON3;
 113 __at(0x0F40) volatile __ODCON3bits_t ODCON3bits;
 114
 115 __at(0x0F41) __sfr ODCON2;
 116 __at(0x0F41) volatile __ODCON2bits_t ODCON2bits;
 117
 118 __at(0x0F42) __sfr ODCON1;
 119 __at(0x0F42) volatile __ODCON1bits_t ODCON1bits;
 120
 121 __at(0x0F48) __sfr ANCON0;
 122 __at(0x0F48) volatile __ANCON0bits_t ANCON0bits;
 123
 124 __at(0x0F49) __sfr ANCON1;
 125 __at(0x0F49) volatile __ANCON1bits_t ANCON1bits;
 126
 127 __at(0x0F4A) __sfr DSWAKEL;
 128 __at(0x0F4A) volatile __DSWAKELbits_t DSWAKELbits;
 129
 130 __at(0x0F4B) __sfr DSWAKEH;
 131 __at(0x0F4B) volatile __DSWAKEHbits_t DSWAKEHbits;
 132
 133 __at(0x0F4C) __sfr DSCONL;
 134 __at(0x0F4C) volatile __DSCONLbits_t DSCONLbits;
 135
 136 __at(0x0F4D) __sfr DSCONH;
 137 __at(0x0F4D) volatile __DSCONHbits_t DSCONHbits;
 138
 139 __at(0x0F4E) __sfr DSGPR0;
 140
 141 __at(0x0F4F) __sfr DSGPR1;
 142
 143 __at(0x0F52) __sfr TCLKCON;
 144 __at(0x0F52) volatile __TCLKCONbits_t TCLKCONbits;
 145
 146 __at(0x0F53) __sfr CVRCON;
 147 __at(0x0F53) volatile __CVRCONbits_t CVRCONbits;
 148
 149 __at(0x0F66) __sfr DMABCH;
 150
 151 __at(0x0F67) __sfr DMABCL;
 152
 153 __at(0x0F68) __sfr RXADDRH;
 154
 155 __at(0x0F69) __sfr RXADDRL;
 156
 157 __at(0x0F6A) __sfr TXADDRH;
 158
 159 __at(0x0F6B) __sfr TXADDRL;
 160
 161 __at(0x0F70) __sfr CMSTAT;
 162 __at(0x0F70) volatile __CMSTATbits_t CMSTATbits;
 163
 164 __at(0x0F70) __sfr CMSTATUS;
 165 __at(0x0F70) volatile __CMSTATUSbits_t CMSTATUSbits;
 166
 167 __at(0x0F71) __sfr SSP2CON2;
 168 __at(0x0F71) volatile __SSP2CON2bits_t SSP2CON2bits;
 169
 170 __at(0x0F72) __sfr SSP2CON1;
 171 __at(0x0F72) volatile __SSP2CON1bits_t SSP2CON1bits;
 172
 173 __at(0x0F73) __sfr SSP2STAT;
 174 __at(0x0F73) volatile __SSP2STATbits_t SSP2STATbits;
 175
 176 __at(0x0F74) __sfr SSP2ADD;
 177 __at(0x0F74) volatile __SSP2ADDbits_t SSP2ADDbits;
 178
 179 __at(0x0F74) __sfr SSP2MSK;
 180 __at(0x0F74) volatile __SSP2MSKbits_t SSP2MSKbits;
 181
 182 __at(0x0F75) __sfr SSP2BUF;
 183
 184 __at(0x0F76) __sfr T4CON;
 185 __at(0x0F76) volatile __T4CONbits_t T4CONbits;
 186
 187 __at(0x0F77) __sfr PR4;
 188
 189 __at(0x0F78) __sfr TMR4;
 190
 191 __at(0x0F79) __sfr T3CON;
 192 __at(0x0F79) volatile __T3CONbits_t T3CONbits;
 193
 194 __at(0x0F7A) __sfr TMR3;
 195
 196 __at(0x0F7A) __sfr TMR3L;
 197
 198 __at(0x0F7B) __sfr TMR3H;
 199
 200 __at(0x0F7C) __sfr BAUDCON2;
 201 __at(0x0F7C) volatile __BAUDCON2bits_t BAUDCON2bits;
 202
 203 __at(0x0F7D) __sfr SPBRGH2;
 204
 205 __at(0x0F7E) __sfr BAUDCON;
 206 __at(0x0F7E) volatile __BAUDCONbits_t BAUDCONbits;
 207
 208 __at(0x0F7E) __sfr BAUDCON1;
 209 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits;
 210
 211 __at(0x0F7E) __sfr BAUDCTL;
 212 __at(0x0F7E) volatile __BAUDCTLbits_t BAUDCTLbits;
 213
 214 __at(0x0F7F) __sfr SPBRGH;
 215
 216 __at(0x0F7F) __sfr SPBRGH1;
 217
 218 __at(0x0F80) __sfr PORTA;
 219 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 220
 221 __at(0x0F81) __sfr PORTB;
 222 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 223
 224 __at(0x0F82) __sfr PORTC;
 225 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 226
 227 __at(0x0F85) __sfr HLVDCON;
 228 __at(0x0F85) volatile __HLVDCONbits_t HLVDCONbits;
 229
 230 __at(0x0F86) __sfr DMACON2;
 231 __at(0x0F86) volatile __DMACON2bits_t DMACON2bits;
 232
 233 __at(0x0F88) __sfr DMACON1;
 234 __at(0x0F88) volatile __DMACON1bits_t DMACON1bits;
 235
 236 __at(0x0F89) __sfr LATA;
 237 __at(0x0F89) volatile __LATAbits_t LATAbits;
 238
 239 __at(0x0F8A) __sfr LATB;
 240 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 241
 242 __at(0x0F8B) __sfr LATC;
 243 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 244
 245 __at(0x0F8E) __sfr ALRMVALL;
 246
 247 __at(0x0F8F) __sfr ALRMVALH;
 248
 249 __at(0x0F90) __sfr ALRMRPT;
 250 __at(0x0F90) volatile __ALRMRPTbits_t ALRMRPTbits;
 251
 252 __at(0x0F91) __sfr ALRMCFG;
 253 __at(0x0F91) volatile __ALRMCFGbits_t ALRMCFGbits;
 254
 255 __at(0x0F92) __sfr TRISA;
 256 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 257
 258 __at(0x0F93) __sfr TRISB;
 259 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 260
 261 __at(0x0F94) __sfr TRISC;
 262 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 263
 264 __at(0x0F97) __sfr T3GCON;
 265 __at(0x0F97) volatile __T3GCONbits_t T3GCONbits;
 266
 267 __at(0x0F98) __sfr RTCVALL;
 268
 269 __at(0x0F99) __sfr RTCVALH;
 270
 271 __at(0x0F9A) __sfr T1GCON;
 272 __at(0x0F9A) volatile __T1GCONbits_t T1GCONbits;
 273
 274 __at(0x0F9B) __sfr OSCTUNE;
 275 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 276
 277 __at(0x0F9C) __sfr RCSTA2;
 278 __at(0x0F9C) volatile __RCSTA2bits_t RCSTA2bits;
 279
 280 __at(0x0F9D) __sfr PIE1;
 281 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 282
 283 __at(0x0F9E) __sfr PIR1;
 284 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 285
 286 __at(0x0F9F) __sfr IPR1;
 287 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 288
 289 __at(0x0FA0) __sfr PIE2;
 290 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 291
 292 __at(0x0FA1) __sfr PIR2;
 293 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 294
 295 __at(0x0FA2) __sfr IPR2;
 296 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 297
 298 __at(0x0FA3) __sfr PIE3;
 299 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 300
 301 __at(0x0FA4) __sfr PIR3;
 302 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 303
 304 __at(0x0FA5) __sfr IPR3;
 305 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 306
 307 __at(0x0FA6) __sfr EECON1;
 308 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 309
 310 __at(0x0FA7) __sfr EECON2;
 311
 312 __at(0x0FA8) __sfr TXSTA2;
 313 __at(0x0FA8) volatile __TXSTA2bits_t TXSTA2bits;
 314
 315 __at(0x0FA9) __sfr TXREG2;
 316
 317 __at(0x0FAA) __sfr RCREG2;
 318
 319 __at(0x0FAB) __sfr SPBRG2;
 320
 321 __at(0x0FAC) __sfr RCSTA;
 322 __at(0x0FAC) volatile __RCSTAbits_t RCSTAbits;
 323
 324 __at(0x0FAC) __sfr RCSTA1;
 325 __at(0x0FAC) volatile __RCSTA1bits_t RCSTA1bits;
 326
 327 __at(0x0FAD) __sfr TXSTA;
 328 __at(0x0FAD) volatile __TXSTAbits_t TXSTAbits;
 329
 330 __at(0x0FAD) __sfr TXSTA1;
 331 __at(0x0FAD) volatile __TXSTA1bits_t TXSTA1bits;
 332
 333 __at(0x0FAE) __sfr TXREG;
 334
 335 __at(0x0FAE) __sfr TXREG1;
 336
 337 __at(0x0FAF) __sfr RCREG;
 338
 339 __at(0x0FAF) __sfr RCREG1;
 340
 341 __at(0x0FB0) __sfr SPBRG;
 342
 343 __at(0x0FB0) __sfr SPBRG1;
 344
 345 __at(0x0FB1) __sfr CTMUICON;
 346 __at(0x0FB1) volatile __CTMUICONbits_t CTMUICONbits;
 347
 348 __at(0x0FB2) __sfr CTMUCONL;
 349 __at(0x0FB2) volatile __CTMUCONLbits_t CTMUCONLbits;
 350
 351 __at(0x0FB3) __sfr CTMUCONH;
 352 __at(0x0FB3) volatile __CTMUCONHbits_t CTMUCONHbits;
 353
 354 __at(0x0FB4) __sfr CCP2CON;
 355 __at(0x0FB4) volatile __CCP2CONbits_t CCP2CONbits;
 356
 357 __at(0x0FB4) __sfr ECCP2CON;
 358 __at(0x0FB4) volatile __ECCP2CONbits_t ECCP2CONbits;
 359
 360 __at(0x0FB5) __sfr CCPR2;
 361
 362 __at(0x0FB5) __sfr CCPR2L;
 363
 364 __at(0x0FB6) __sfr CCPR2H;
 365
 366 __at(0x0FB7) __sfr ECCP2DEL;
 367 __at(0x0FB7) volatile __ECCP2DELbits_t ECCP2DELbits;
 368
 369 __at(0x0FB7) __sfr PWM2CON;
 370 __at(0x0FB7) volatile __PWM2CONbits_t PWM2CONbits;
 371
 372 __at(0x0FB8) __sfr ECCP2AS;
 373 __at(0x0FB8) volatile __ECCP2ASbits_t ECCP2ASbits;
 374
 375 __at(0x0FB9) __sfr PSTR2CON;
 376 __at(0x0FB9) volatile __PSTR2CONbits_t PSTR2CONbits;
 377
 378 __at(0x0FBA) __sfr CCP1CON;
 379 __at(0x0FBA) volatile __CCP1CONbits_t CCP1CONbits;
 380
 381 __at(0x0FBA) __sfr ECCP1CON;
 382 __at(0x0FBA) volatile __ECCP1CONbits_t ECCP1CONbits;
 383
 384 __at(0x0FBB) __sfr CCPR1;
 385
 386 __at(0x0FBB) __sfr CCPR1L;
 387
 388 __at(0x0FBC) __sfr CCPR1H;
 389
 390 __at(0x0FBD) __sfr ECCP1DEL;
 391 __at(0x0FBD) volatile __ECCP1DELbits_t ECCP1DELbits;
 392
 393 __at(0x0FBD) __sfr PWM1CON;
 394 __at(0x0FBD) volatile __PWM1CONbits_t PWM1CONbits;
 395
 396 __at(0x0FBE) __sfr ECCP1AS;
 397 __at(0x0FBE) volatile __ECCP1ASbits_t ECCP1ASbits;
 398
 399 __at(0x0FBF) __sfr PSTR1CON;
 400 __at(0x0FBF) volatile __PSTR1CONbits_t PSTR1CONbits;
 401
 402 __at(0x0FC0) __sfr WDTCON;
 403 __at(0x0FC0) volatile __WDTCONbits_t WDTCONbits;
 404
 405 __at(0x0FC1) __sfr ADCON1;
 406 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 407
 408 __at(0x0FC2) __sfr ADCON0;
 409 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 410
 411 __at(0x0FC3) __sfr ADRES;
 412
 413 __at(0x0FC3) __sfr ADRESL;
 414
 415 __at(0x0FC4) __sfr ADRESH;
 416
 417 __at(0x0FC5) __sfr SSP1CON2;
 418 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 419
 420 __at(0x0FC5) __sfr SSPCON2;
 421 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 422
 423 __at(0x0FC6) __sfr SSP1CON1;
 424 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 425
 426 __at(0x0FC6) __sfr SSPCON1;
 427 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 428
 429 __at(0x0FC7) __sfr SSP1STAT;
 430 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 431
 432 __at(0x0FC7) __sfr SSPSTAT;
 433 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 434
 435 __at(0x0FC8) __sfr SSP1ADD;
 436 __at(0x0FC8) volatile __SSP1ADDbits_t SSP1ADDbits;
 437
 438 __at(0x0FC8) __sfr SSP1MSK;
 439 __at(0x0FC8) volatile __SSP1MSKbits_t SSP1MSKbits;
 440
 441 __at(0x0FC8) __sfr SSPADD;
 442 __at(0x0FC8) volatile __SSPADDbits_t SSPADDbits;
 443
 444 __at(0x0FC9) __sfr SSP1BUF;
 445
 446 __at(0x0FC9) __sfr SSPBUF;
 447
 448 __at(0x0FCA) __sfr T2CON;
 449 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 450
 451 __at(0x0FCB) __sfr PR2;
 452
 453 __at(0x0FCC) __sfr TMR2;
 454
 455 __at(0x0FCD) __sfr T1CON;
 456 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 457
 458 __at(0x0FCE) __sfr TMR1;
 459
 460 __at(0x0FCE) __sfr TMR1L;
 461
 462 __at(0x0FCF) __sfr TMR1H;
 463
 464 __at(0x0FD0) __sfr RCON;
 465 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 466
 467 __at(0x0FD1) __sfr CM2CON;
 468 __at(0x0FD1) volatile __CM2CONbits_t CM2CONbits;
 469
 470 __at(0x0FD1) __sfr CM2CON1;
 471 __at(0x0FD1) volatile __CM2CON1bits_t CM2CON1bits;
 472
 473 __at(0x0FD2) __sfr CM1CON;
 474 __at(0x0FD2) volatile __CM1CONbits_t CM1CONbits;
 475
 476 __at(0x0FD2) __sfr CM1CON1;
 477 __at(0x0FD2) volatile __CM1CON1bits_t CM1CON1bits;
 478
 479 __at(0x0FD3) __sfr OSCCON;
 480 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 481
 482 __at(0x0FD5) __sfr T0CON;
 483 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 484
 485 __at(0x0FD6) __sfr TMR0;
 486
 487 __at(0x0FD6) __sfr TMR0L;
 488
 489 __at(0x0FD7) __sfr TMR0H;
 490
 491 __at(0x0FD8) __sfr STATUS;
 492 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 493
 494 __at(0x0FD9) __sfr FSR2L;
 495
 496 __at(0x0FDA) __sfr FSR2H;
 497
 498 __at(0x0FDB) __sfr PLUSW2;
 499
 500 __at(0x0FDC) __sfr PREINC2;
 501
 502 __at(0x0FDD) __sfr POSTDEC2;
 503
 504 __at(0x0FDE) __sfr POSTINC2;
 505
 506 __at(0x0FDF) __sfr INDF2;
 507
 508 __at(0x0FE0) __sfr BSR;
 509
 510 __at(0x0FE1) __sfr FSR1L;
 511
 512 __at(0x0FE2) __sfr FSR1H;
 513
 514 __at(0x0FE3) __sfr PLUSW1;
 515
 516 __at(0x0FE4) __sfr PREINC1;
 517
 518 __at(0x0FE5) __sfr POSTDEC1;
 519
 520 __at(0x0FE6) __sfr POSTINC1;
 521
 522 __at(0x0FE7) __sfr INDF1;
 523
 524 __at(0x0FE8) __sfr WREG;
 525
 526 __at(0x0FE9) __sfr FSR0L;
 527
 528 __at(0x0FEA) __sfr FSR0H;
 529
 530 __at(0x0FEB) __sfr PLUSW0;
 531
 532 __at(0x0FEC) __sfr PREINC0;
 533
 534 __at(0x0FED) __sfr POSTDEC0;
 535
 536 __at(0x0FEE) __sfr POSTINC0;
 537
 538 __at(0x0FEF) __sfr INDF0;
 539
 540 __at(0x0FF0) __sfr INTCON3;
 541 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 542
 543 __at(0x0FF1) __sfr INTCON2;
 544 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 545
 546 __at(0x0FF2) __sfr INTCON;
 547 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 548
 549 __at(0x0FF3) __sfr PROD;
 550
 551 __at(0x0FF3) __sfr PRODL;
 552
 553 __at(0x0FF4) __sfr PRODH;
 554
 555 __at(0x0FF5) __sfr TABLAT;
 556
 557 __at(0x0FF6) __sfr TBLPTR;
 558
 559 __at(0x0FF6) __sfr TBLPTRL;
 560
 561 __at(0x0FF7) __sfr TBLPTRH;
 562
 563 __at(0x0FF8) __sfr TBLPTRU;
 564
 565 __at(0x0FF9) __sfr PC;
 566
 567 __at(0x0FF9) __sfr PCL;
 568
 569 __at(0x0FFA) __sfr PCLATH;
 570
 571 __at(0x0FFB) __sfr PCLATU;
 572
 573 __at(0x0FFC) __sfr STKPTR;
 574 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 575
 576 __at(0x0FFD) __sfr TOS;
 577
 578 __at(0x0FFD) __sfr TOSL;
 579
 580 __at(0x0FFE) __sfr TOSH;
 581
 582 __at(0x0FFF) __sfr TOSU;