sdcc/device/non-free/lib/pic16/libdev/pic18lf4331.c

   1 /*
   2  * This definitions of the PIC18LF4331 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:24:02 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18lf4331.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F60) __sfr DFLTCON;
  30 __at(0x0F60) volatile __DFLTCONbits_t DFLTCONbits;
  31
  32 __at(0x0F61) __sfr CAP3CON;
  33 __at(0x0F61) volatile __CAP3CONbits_t CAP3CONbits;
  34
  35 __at(0x0F62) __sfr CAP2CON;
  36 __at(0x0F62) volatile __CAP2CONbits_t CAP2CONbits;
  37
  38 __at(0x0F63) __sfr CAP1CON;
  39 __at(0x0F63) volatile __CAP1CONbits_t CAP1CONbits;
  40
  41 __at(0x0F64) __sfr CAP3BUFL;
  42
  43 __at(0x0F64) __sfr MAXCNTL;
  44
  45 __at(0x0F65) __sfr CAP3BUFH;
  46
  47 __at(0x0F65) __sfr MAXCNTH;
  48
  49 __at(0x0F66) __sfr CAP2BUFL;
  50
  51 __at(0x0F66) __sfr POSCNTL;
  52
  53 __at(0x0F67) __sfr CAP2BUFH;
  54
  55 __at(0x0F67) __sfr POSCNTH;
  56
  57 __at(0x0F68) __sfr CAP1BUFL;
  58
  59 __at(0x0F68) __sfr VELRL;
  60
  61 __at(0x0F69) __sfr CAP1BUFH;
  62
  63 __at(0x0F69) __sfr VELRH;
  64
  65 __at(0x0F6A) __sfr OVDCONS;
  66 __at(0x0F6A) volatile __OVDCONSbits_t OVDCONSbits;
  67
  68 __at(0x0F6B) __sfr OVDCOND;
  69 __at(0x0F6B) volatile __OVDCONDbits_t OVDCONDbits;
  70
  71 __at(0x0F6C) __sfr FLTCONFIG;
  72 __at(0x0F6C) volatile __FLTCONFIGbits_t FLTCONFIGbits;
  73
  74 __at(0x0F6D) __sfr DTCON;
  75 __at(0x0F6D) volatile __DTCONbits_t DTCONbits;
  76
  77 __at(0x0F6E) __sfr PWMCON1;
  78 __at(0x0F6E) volatile __PWMCON1bits_t PWMCON1bits;
  79
  80 __at(0x0F6F) __sfr PWMCON0;
  81 __at(0x0F6F) volatile __PWMCON0bits_t PWMCON0bits;
  82
  83 __at(0x0F70) __sfr SEVTCMPH;
  84
  85 __at(0x0F71) __sfr SEVTCMPL;
  86
  87 __at(0x0F72) __sfr PDC3H;
  88
  89 __at(0x0F73) __sfr PDC3L;
  90
  91 __at(0x0F74) __sfr PDC2H;
  92
  93 __at(0x0F75) __sfr PDC2L;
  94
  95 __at(0x0F76) __sfr PDC1H;
  96
  97 __at(0x0F77) __sfr PDC1L;
  98
  99 __at(0x0F78) __sfr PDC0H;
 100
 101 __at(0x0F79) __sfr PDC0L;
 102
 103 __at(0x0F7A) __sfr PTPERH;
 104
 105 __at(0x0F7B) __sfr PTPERL;
 106
 107 __at(0x0F7C) __sfr PTMRH;
 108
 109 __at(0x0F7D) __sfr PTMRL;
 110
 111 __at(0x0F7E) __sfr PTCON1;
 112 __at(0x0F7E) volatile __PTCON1bits_t PTCON1bits;
 113
 114 __at(0x0F7F) __sfr PTCON0;
 115 __at(0x0F7F) volatile __PTCON0bits_t PTCON0bits;
 116
 117 __at(0x0F80) __sfr PORTA;
 118 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 119
 120 __at(0x0F81) __sfr PORTB;
 121 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 122
 123 __at(0x0F82) __sfr PORTC;
 124 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 125
 126 __at(0x0F83) __sfr PORTD;
 127 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 128
 129 __at(0x0F84) __sfr PORTE;
 130 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 131
 132 __at(0x0F87) __sfr TMR5;
 133
 134 __at(0x0F87) __sfr TMR5L;
 135
 136 __at(0x0F88) __sfr TMR5H;
 137
 138 __at(0x0F89) __sfr LATA;
 139 __at(0x0F89) volatile __LATAbits_t LATAbits;
 140
 141 __at(0x0F8A) __sfr LATB;
 142 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 143
 144 __at(0x0F8B) __sfr LATC;
 145 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 146
 147 __at(0x0F8C) __sfr LATD;
 148 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 149
 150 __at(0x0F8D) __sfr LATE;
 151 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 152
 153 __at(0x0F90) __sfr PR5;
 154
 155 __at(0x0F90) __sfr PR5L;
 156
 157 __at(0x0F91) __sfr PR5H;
 158
 159 __at(0x0F92) __sfr DDRA;
 160 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 161
 162 __at(0x0F92) __sfr TRISA;
 163 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 164
 165 __at(0x0F93) __sfr DDRB;
 166 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 167
 168 __at(0x0F93) __sfr TRISB;
 169 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 170
 171 __at(0x0F94) __sfr DDRC;
 172 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 173
 174 __at(0x0F94) __sfr TRISC;
 175 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 176
 177 __at(0x0F95) __sfr DDRD;
 178 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 179
 180 __at(0x0F95) __sfr TRISD;
 181 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 182
 183 __at(0x0F96) __sfr DDRE;
 184 __at(0x0F96) volatile __DDREbits_t DDREbits;
 185
 186 __at(0x0F96) __sfr TRISE;
 187 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 188
 189 __at(0x0F99) __sfr ADCHS;
 190 __at(0x0F99) volatile __ADCHSbits_t ADCHSbits;
 191
 192 __at(0x0F9A) __sfr ADCON3;
 193 __at(0x0F9A) volatile __ADCON3bits_t ADCON3bits;
 194
 195 __at(0x0F9B) __sfr OSCTUNE;
 196 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 197
 198 __at(0x0F9D) __sfr PIE1;
 199 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 200
 201 __at(0x0F9E) __sfr PIR1;
 202 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 203
 204 __at(0x0F9F) __sfr IPR1;
 205 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 206
 207 __at(0x0FA0) __sfr PIE2;
 208 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 209
 210 __at(0x0FA1) __sfr PIR2;
 211 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 212
 213 __at(0x0FA2) __sfr IPR2;
 214 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 215
 216 __at(0x0FA3) __sfr PIE3;
 217 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 218
 219 __at(0x0FA4) __sfr PIR3;
 220 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 221
 222 __at(0x0FA5) __sfr IPR3;
 223 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 224
 225 __at(0x0FA6) __sfr EECON1;
 226 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 227
 228 __at(0x0FA7) __sfr EECON2;
 229
 230 __at(0x0FA8) __sfr EEDATA;
 231
 232 __at(0x0FA9) __sfr EEADR;
 233
 234 __at(0x0FAA) __sfr BAUDCON;
 235 __at(0x0FAA) volatile __BAUDCONbits_t BAUDCONbits;
 236
 237 __at(0x0FAA) __sfr BAUDCTL;
 238 __at(0x0FAA) volatile __BAUDCTLbits_t BAUDCTLbits;
 239
 240 __at(0x0FAB) __sfr RCSTA;
 241 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 242
 243 __at(0x0FAC) __sfr TXSTA;
 244 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 245
 246 __at(0x0FAD) __sfr TXREG;
 247
 248 __at(0x0FAE) __sfr RCREG;
 249
 250 __at(0x0FAF) __sfr SPBRG;
 251
 252 __at(0x0FB0) __sfr SPBRGH;
 253
 254 __at(0x0FB6) __sfr QEICON;
 255 __at(0x0FB6) volatile __QEICONbits_t QEICONbits;
 256
 257 __at(0x0FB7) __sfr T5CON;
 258 __at(0x0FB7) volatile __T5CONbits_t T5CONbits;
 259
 260 __at(0x0FB8) __sfr ANSEL0;
 261 __at(0x0FB8) volatile __ANSEL0bits_t ANSEL0bits;
 262
 263 __at(0x0FB9) __sfr ANSEL1;
 264 __at(0x0FB9) volatile __ANSEL1bits_t ANSEL1bits;
 265
 266 __at(0x0FBA) __sfr CCP2CON;
 267 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits;
 268
 269 __at(0x0FBB) __sfr CCPR2;
 270
 271 __at(0x0FBB) __sfr CCPR2L;
 272
 273 __at(0x0FBC) __sfr CCPR2H;
 274
 275 __at(0x0FBD) __sfr CCP1CON;
 276 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 277
 278 __at(0x0FBE) __sfr CCPR1;
 279
 280 __at(0x0FBE) __sfr CCPR1L;
 281
 282 __at(0x0FBF) __sfr CCPR1H;
 283
 284 __at(0x0FC0) __sfr ADCON2;
 285 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 286
 287 __at(0x0FC1) __sfr ADCON1;
 288 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 289
 290 __at(0x0FC2) __sfr ADCON0;
 291 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 292
 293 __at(0x0FC3) __sfr ADRES;
 294
 295 __at(0x0FC3) __sfr ADRESL;
 296
 297 __at(0x0FC4) __sfr ADRESH;
 298
 299 __at(0x0FC6) __sfr SSPCON;
 300 __at(0x0FC6) volatile __SSPCONbits_t SSPCONbits;
 301
 302 __at(0x0FC7) __sfr SSPSTAT;
 303 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 304
 305 __at(0x0FC8) __sfr SSPADD;
 306
 307 __at(0x0FC9) __sfr SSPBUF;
 308
 309 __at(0x0FCA) __sfr T2CON;
 310 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 311
 312 __at(0x0FCB) __sfr PR2;
 313
 314 __at(0x0FCC) __sfr TMR2;
 315
 316 __at(0x0FCD) __sfr T1CON;
 317 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 318
 319 __at(0x0FCE) __sfr TMR1;
 320
 321 __at(0x0FCE) __sfr TMR1L;
 322
 323 __at(0x0FCF) __sfr TMR1H;
 324
 325 __at(0x0FD0) __sfr RCON;
 326 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 327
 328 __at(0x0FD1) __sfr WDTCON;
 329 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 330
 331 __at(0x0FD2) __sfr LVDCON;
 332 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits;
 333
 334 __at(0x0FD3) __sfr OSCCON;
 335 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 336
 337 __at(0x0FD5) __sfr T0CON;
 338 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 339
 340 __at(0x0FD6) __sfr TMR0;
 341
 342 __at(0x0FD6) __sfr TMR0L;
 343
 344 __at(0x0FD7) __sfr TMR0H;
 345
 346 __at(0x0FD8) __sfr STATUS;
 347 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 348
 349 __at(0x0FD9) __sfr FSR2L;
 350
 351 __at(0x0FDA) __sfr FSR2H;
 352
 353 __at(0x0FDB) __sfr PLUSW2;
 354
 355 __at(0x0FDC) __sfr PREINC2;
 356
 357 __at(0x0FDD) __sfr POSTDEC2;
 358
 359 __at(0x0FDE) __sfr POSTINC2;
 360
 361 __at(0x0FDF) __sfr INDF2;
 362
 363 __at(0x0FE0) __sfr BSR;
 364
 365 __at(0x0FE1) __sfr FSR1L;
 366
 367 __at(0x0FE2) __sfr FSR1H;
 368
 369 __at(0x0FE3) __sfr PLUSW1;
 370
 371 __at(0x0FE4) __sfr PREINC1;
 372
 373 __at(0x0FE5) __sfr POSTDEC1;
 374
 375 __at(0x0FE6) __sfr POSTINC1;
 376
 377 __at(0x0FE7) __sfr INDF1;
 378
 379 __at(0x0FE8) __sfr WREG;
 380
 381 __at(0x0FE9) __sfr FSR0L;
 382
 383 __at(0x0FEA) __sfr FSR0H;
 384
 385 __at(0x0FEB) __sfr PLUSW0;
 386
 387 __at(0x0FEC) __sfr PREINC0;
 388
 389 __at(0x0FED) __sfr POSTDEC0;
 390
 391 __at(0x0FEE) __sfr POSTINC0;
 392
 393 __at(0x0FEF) __sfr INDF0;
 394
 395 __at(0x0FF0) __sfr INTCON3;
 396 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 397
 398 __at(0x0FF1) __sfr INTCON2;
 399 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 400
 401 __at(0x0FF2) __sfr INTCON;
 402 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 403
 404 __at(0x0FF3) __sfr PROD;
 405
 406 __at(0x0FF3) __sfr PRODL;
 407
 408 __at(0x0FF4) __sfr PRODH;
 409
 410 __at(0x0FF5) __sfr TABLAT;
 411
 412 __at(0x0FF6) __sfr TBLPTR;
 413
 414 __at(0x0FF6) __sfr TBLPTRL;
 415
 416 __at(0x0FF7) __sfr TBLPTRH;
 417
 418 __at(0x0FF8) __sfr TBLPTRU;
 419
 420 __at(0x0FF9) __sfr PC;
 421
 422 __at(0x0FF9) __sfr PCL;
 423
 424 __at(0x0FFA) __sfr PCLATH;
 425
 426 __at(0x0FFB) __sfr PCLATU;
 427
 428 __at(0x0FFC) __sfr STKPTR;
 429 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 430
 431 __at(0x0FFD) __sfr TOS;
 432
 433 __at(0x0FFD) __sfr TOSL;
 434
 435 __at(0x0FFE) __sfr TOSH;
 436
 437 __at(0x0FFF) __sfr TOSU;