sdcc/device/non-free/lib/pic16/libdev/pic18lf458.c

   1 /*
   2  * This definitions of the PIC18LF458 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:59 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18lf458.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F00) __sfr RXF0SIDH;
  30 __at(0x0F00) volatile __RXF0SIDHbits_t RXF0SIDHbits;
  31
  32 __at(0x0F01) __sfr RXF0SIDL;
  33 __at(0x0F01) volatile __RXF0SIDLbits_t RXF0SIDLbits;
  34
  35 __at(0x0F02) __sfr RXF0EIDH;
  36 __at(0x0F02) volatile __RXF0EIDHbits_t RXF0EIDHbits;
  37
  38 __at(0x0F03) __sfr RXF0EIDL;
  39 __at(0x0F03) volatile __RXF0EIDLbits_t RXF0EIDLbits;
  40
  41 __at(0x0F04) __sfr RXF1SIDH;
  42 __at(0x0F04) volatile __RXF1SIDHbits_t RXF1SIDHbits;
  43
  44 __at(0x0F05) __sfr RXF1SIDL;
  45 __at(0x0F05) volatile __RXF1SIDLbits_t RXF1SIDLbits;
  46
  47 __at(0x0F06) __sfr RXF1EIDH;
  48 __at(0x0F06) volatile __RXF1EIDHbits_t RXF1EIDHbits;
  49
  50 __at(0x0F07) __sfr RXF1EIDL;
  51 __at(0x0F07) volatile __RXF1EIDLbits_t RXF1EIDLbits;
  52
  53 __at(0x0F08) __sfr RXF2SIDH;
  54 __at(0x0F08) volatile __RXF2SIDHbits_t RXF2SIDHbits;
  55
  56 __at(0x0F09) __sfr RXF2SIDL;
  57 __at(0x0F09) volatile __RXF2SIDLbits_t RXF2SIDLbits;
  58
  59 __at(0x0F0A) __sfr RXF2EIDH;
  60 __at(0x0F0A) volatile __RXF2EIDHbits_t RXF2EIDHbits;
  61
  62 __at(0x0F0B) __sfr RXF2EIDL;
  63 __at(0x0F0B) volatile __RXF2EIDLbits_t RXF2EIDLbits;
  64
  65 __at(0x0F0C) __sfr RXF3SIDH;
  66 __at(0x0F0C) volatile __RXF3SIDHbits_t RXF3SIDHbits;
  67
  68 __at(0x0F0D) __sfr RXF3SIDL;
  69 __at(0x0F0D) volatile __RXF3SIDLbits_t RXF3SIDLbits;
  70
  71 __at(0x0F0E) __sfr RXF3EIDH;
  72 __at(0x0F0E) volatile __RXF3EIDHbits_t RXF3EIDHbits;
  73
  74 __at(0x0F0F) __sfr RXF3EIDL;
  75 __at(0x0F0F) volatile __RXF3EIDLbits_t RXF3EIDLbits;
  76
  77 __at(0x0F10) __sfr RXF4SIDH;
  78 __at(0x0F10) volatile __RXF4SIDHbits_t RXF4SIDHbits;
  79
  80 __at(0x0F11) __sfr RXF4SIDL;
  81 __at(0x0F11) volatile __RXF4SIDLbits_t RXF4SIDLbits;
  82
  83 __at(0x0F12) __sfr RXF4EIDH;
  84 __at(0x0F12) volatile __RXF4EIDHbits_t RXF4EIDHbits;
  85
  86 __at(0x0F13) __sfr RXF4EIDL;
  87 __at(0x0F13) volatile __RXF4EIDLbits_t RXF4EIDLbits;
  88
  89 __at(0x0F14) __sfr RXF5SIDH;
  90 __at(0x0F14) volatile __RXF5SIDHbits_t RXF5SIDHbits;
  91
  92 __at(0x0F15) __sfr RXF5SIDL;
  93 __at(0x0F15) volatile __RXF5SIDLbits_t RXF5SIDLbits;
  94
  95 __at(0x0F16) __sfr RXF5EIDH;
  96 __at(0x0F16) volatile __RXF5EIDHbits_t RXF5EIDHbits;
  97
  98 __at(0x0F17) __sfr RXF5EIDL;
  99 __at(0x0F17) volatile __RXF5EIDLbits_t RXF5EIDLbits;
 100
 101 __at(0x0F18) __sfr RXM0SIDH;
 102 __at(0x0F18) volatile __RXM0SIDHbits_t RXM0SIDHbits;
 103
 104 __at(0x0F19) __sfr RXM0SIDL;
 105 __at(0x0F19) volatile __RXM0SIDLbits_t RXM0SIDLbits;
 106
 107 __at(0x0F1A) __sfr RXM0EIDH;
 108 __at(0x0F1A) volatile __RXM0EIDHbits_t RXM0EIDHbits;
 109
 110 __at(0x0F1B) __sfr RXM0EIDL;
 111 __at(0x0F1B) volatile __RXM0EIDLbits_t RXM0EIDLbits;
 112
 113 __at(0x0F1C) __sfr RXM1SIDH;
 114 __at(0x0F1C) volatile __RXM1SIDHbits_t RXM1SIDHbits;
 115
 116 __at(0x0F1D) __sfr RXM1SIDL;
 117 __at(0x0F1D) volatile __RXM1SIDLbits_t RXM1SIDLbits;
 118
 119 __at(0x0F1E) __sfr RXM1EIDH;
 120 __at(0x0F1E) volatile __RXM1EIDHbits_t RXM1EIDHbits;
 121
 122 __at(0x0F1F) __sfr RXM1EIDL;
 123 __at(0x0F1F) volatile __RXM1EIDLbits_t RXM1EIDLbits;
 124
 125 __at(0x0F20) __sfr TXB2CON;
 126 __at(0x0F20) volatile __TXB2CONbits_t TXB2CONbits;
 127
 128 __at(0x0F21) __sfr TXB2SIDH;
 129 __at(0x0F21) volatile __TXB2SIDHbits_t TXB2SIDHbits;
 130
 131 __at(0x0F22) __sfr TXB2SIDL;
 132 __at(0x0F22) volatile __TXB2SIDLbits_t TXB2SIDLbits;
 133
 134 __at(0x0F23) __sfr TXB2EIDH;
 135 __at(0x0F23) volatile __TXB2EIDHbits_t TXB2EIDHbits;
 136
 137 __at(0x0F24) __sfr TXB2EIDL;
 138 __at(0x0F24) volatile __TXB2EIDLbits_t TXB2EIDLbits;
 139
 140 __at(0x0F25) __sfr TXB2DLC;
 141 __at(0x0F25) volatile __TXB2DLCbits_t TXB2DLCbits;
 142
 143 __at(0x0F26) __sfr TXB2D0;
 144 __at(0x0F26) volatile __TXB2D0bits_t TXB2D0bits;
 145
 146 __at(0x0F27) __sfr TXB2D1;
 147 __at(0x0F27) volatile __TXB2D1bits_t TXB2D1bits;
 148
 149 __at(0x0F28) __sfr TXB2D2;
 150 __at(0x0F28) volatile __TXB2D2bits_t TXB2D2bits;
 151
 152 __at(0x0F29) __sfr TXB2D3;
 153 __at(0x0F29) volatile __TXB2D3bits_t TXB2D3bits;
 154
 155 __at(0x0F2A) __sfr TXB2D4;
 156 __at(0x0F2A) volatile __TXB2D4bits_t TXB2D4bits;
 157
 158 __at(0x0F2B) __sfr TXB2D5;
 159 __at(0x0F2B) volatile __TXB2D5bits_t TXB2D5bits;
 160
 161 __at(0x0F2C) __sfr TXB2D6;
 162 __at(0x0F2C) volatile __TXB2D6bits_t TXB2D6bits;
 163
 164 __at(0x0F2D) __sfr TXB2D7;
 165 __at(0x0F2D) volatile __TXB2D7bits_t TXB2D7bits;
 166
 167 __at(0x0F2E) __sfr CANSTATRO4;
 168 __at(0x0F2E) volatile __CANSTATRO4bits_t CANSTATRO4bits;
 169
 170 __at(0x0F30) __sfr TXB1CON;
 171 __at(0x0F30) volatile __TXB1CONbits_t TXB1CONbits;
 172
 173 __at(0x0F31) __sfr TXB1SIDH;
 174 __at(0x0F31) volatile __TXB1SIDHbits_t TXB1SIDHbits;
 175
 176 __at(0x0F32) __sfr TXB1SIDL;
 177 __at(0x0F32) volatile __TXB1SIDLbits_t TXB1SIDLbits;
 178
 179 __at(0x0F33) __sfr TXB1EIDH;
 180 __at(0x0F33) volatile __TXB1EIDHbits_t TXB1EIDHbits;
 181
 182 __at(0x0F34) __sfr TXB1EIDL;
 183 __at(0x0F34) volatile __TXB1EIDLbits_t TXB1EIDLbits;
 184
 185 __at(0x0F35) __sfr TXB1DLC;
 186 __at(0x0F35) volatile __TXB1DLCbits_t TXB1DLCbits;
 187
 188 __at(0x0F36) __sfr TXB1D0;
 189 __at(0x0F36) volatile __TXB1D0bits_t TXB1D0bits;
 190
 191 __at(0x0F37) __sfr TXB1D1;
 192 __at(0x0F37) volatile __TXB1D1bits_t TXB1D1bits;
 193
 194 __at(0x0F38) __sfr TXB1D2;
 195 __at(0x0F38) volatile __TXB1D2bits_t TXB1D2bits;
 196
 197 __at(0x0F39) __sfr TXB1D3;
 198 __at(0x0F39) volatile __TXB1D3bits_t TXB1D3bits;
 199
 200 __at(0x0F3A) __sfr TXB1D4;
 201 __at(0x0F3A) volatile __TXB1D4bits_t TXB1D4bits;
 202
 203 __at(0x0F3B) __sfr TXB1D5;
 204 __at(0x0F3B) volatile __TXB1D5bits_t TXB1D5bits;
 205
 206 __at(0x0F3C) __sfr TXB1D6;
 207 __at(0x0F3C) volatile __TXB1D6bits_t TXB1D6bits;
 208
 209 __at(0x0F3D) __sfr TXB1D7;
 210 __at(0x0F3D) volatile __TXB1D7bits_t TXB1D7bits;
 211
 212 __at(0x0F3E) __sfr CANSTATRO3;
 213 __at(0x0F3E) volatile __CANSTATRO3bits_t CANSTATRO3bits;
 214
 215 __at(0x0F40) __sfr TXB0CON;
 216 __at(0x0F40) volatile __TXB0CONbits_t TXB0CONbits;
 217
 218 __at(0x0F41) __sfr TXB0SIDH;
 219 __at(0x0F41) volatile __TXB0SIDHbits_t TXB0SIDHbits;
 220
 221 __at(0x0F42) __sfr TXB0SIDL;
 222 __at(0x0F42) volatile __TXB0SIDLbits_t TXB0SIDLbits;
 223
 224 __at(0x0F43) __sfr TXB0EIDH;
 225 __at(0x0F43) volatile __TXB0EIDHbits_t TXB0EIDHbits;
 226
 227 __at(0x0F44) __sfr TXB0EIDL;
 228 __at(0x0F44) volatile __TXB0EIDLbits_t TXB0EIDLbits;
 229
 230 __at(0x0F45) __sfr TXB0DLC;
 231 __at(0x0F45) volatile __TXB0DLCbits_t TXB0DLCbits;
 232
 233 __at(0x0F46) __sfr TXB0D0;
 234 __at(0x0F46) volatile __TXB0D0bits_t TXB0D0bits;
 235
 236 __at(0x0F47) __sfr TXB0D1;
 237 __at(0x0F47) volatile __TXB0D1bits_t TXB0D1bits;
 238
 239 __at(0x0F48) __sfr TXB0D2;
 240 __at(0x0F48) volatile __TXB0D2bits_t TXB0D2bits;
 241
 242 __at(0x0F49) __sfr TXB0D3;
 243 __at(0x0F49) volatile __TXB0D3bits_t TXB0D3bits;
 244
 245 __at(0x0F4A) __sfr TXB0D4;
 246 __at(0x0F4A) volatile __TXB0D4bits_t TXB0D4bits;
 247
 248 __at(0x0F4B) __sfr TXB0D5;
 249 __at(0x0F4B) volatile __TXB0D5bits_t TXB0D5bits;
 250
 251 __at(0x0F4C) __sfr TXB0D6;
 252 __at(0x0F4C) volatile __TXB0D6bits_t TXB0D6bits;
 253
 254 __at(0x0F4D) __sfr TXB0D7;
 255 __at(0x0F4D) volatile __TXB0D7bits_t TXB0D7bits;
 256
 257 __at(0x0F4E) __sfr CANSTATRO2;
 258 __at(0x0F4E) volatile __CANSTATRO2bits_t CANSTATRO2bits;
 259
 260 __at(0x0F50) __sfr RXB1CON;
 261 __at(0x0F50) volatile __RXB1CONbits_t RXB1CONbits;
 262
 263 __at(0x0F51) __sfr RXB1SIDH;
 264 __at(0x0F51) volatile __RXB1SIDHbits_t RXB1SIDHbits;
 265
 266 __at(0x0F52) __sfr RXB1SIDL;
 267 __at(0x0F52) volatile __RXB1SIDLbits_t RXB1SIDLbits;
 268
 269 __at(0x0F53) __sfr RXB1EIDH;
 270 __at(0x0F53) volatile __RXB1EIDHbits_t RXB1EIDHbits;
 271
 272 __at(0x0F54) __sfr RXB1EIDL;
 273 __at(0x0F54) volatile __RXB1EIDLbits_t RXB1EIDLbits;
 274
 275 __at(0x0F55) __sfr RXB1DLC;
 276 __at(0x0F55) volatile __RXB1DLCbits_t RXB1DLCbits;
 277
 278 __at(0x0F56) __sfr RXB1D0;
 279 __at(0x0F56) volatile __RXB1D0bits_t RXB1D0bits;
 280
 281 __at(0x0F57) __sfr RXB1D1;
 282 __at(0x0F57) volatile __RXB1D1bits_t RXB1D1bits;
 283
 284 __at(0x0F58) __sfr RXB1D2;
 285 __at(0x0F58) volatile __RXB1D2bits_t RXB1D2bits;
 286
 287 __at(0x0F59) __sfr RXB1D3;
 288 __at(0x0F59) volatile __RXB1D3bits_t RXB1D3bits;
 289
 290 __at(0x0F5A) __sfr RXB1D4;
 291 __at(0x0F5A) volatile __RXB1D4bits_t RXB1D4bits;
 292
 293 __at(0x0F5B) __sfr RXB1D5;
 294 __at(0x0F5B) volatile __RXB1D5bits_t RXB1D5bits;
 295
 296 __at(0x0F5C) __sfr RXB1D6;
 297 __at(0x0F5C) volatile __RXB1D6bits_t RXB1D6bits;
 298
 299 __at(0x0F5D) __sfr RXB1D7;
 300 __at(0x0F5D) volatile __RXB1D7bits_t RXB1D7bits;
 301
 302 __at(0x0F5E) __sfr CANSTATRO1;
 303 __at(0x0F5E) volatile __CANSTATRO1bits_t CANSTATRO1bits;
 304
 305 __at(0x0F60) __sfr RXB0CON;
 306 __at(0x0F60) volatile __RXB0CONbits_t RXB0CONbits;
 307
 308 __at(0x0F61) __sfr RXB0SIDH;
 309 __at(0x0F61) volatile __RXB0SIDHbits_t RXB0SIDHbits;
 310
 311 __at(0x0F62) __sfr RXB0SIDL;
 312 __at(0x0F62) volatile __RXB0SIDLbits_t RXB0SIDLbits;
 313
 314 __at(0x0F63) __sfr RXB0EIDH;
 315 __at(0x0F63) volatile __RXB0EIDHbits_t RXB0EIDHbits;
 316
 317 __at(0x0F64) __sfr RXB0EIDL;
 318 __at(0x0F64) volatile __RXB0EIDLbits_t RXB0EIDLbits;
 319
 320 __at(0x0F65) __sfr RXB0DLC;
 321 __at(0x0F65) volatile __RXB0DLCbits_t RXB0DLCbits;
 322
 323 __at(0x0F66) __sfr RXB0D0;
 324 __at(0x0F66) volatile __RXB0D0bits_t RXB0D0bits;
 325
 326 __at(0x0F67) __sfr RXB0D1;
 327 __at(0x0F67) volatile __RXB0D1bits_t RXB0D1bits;
 328
 329 __at(0x0F68) __sfr RXB0D2;
 330 __at(0x0F68) volatile __RXB0D2bits_t RXB0D2bits;
 331
 332 __at(0x0F69) __sfr RXB0D3;
 333 __at(0x0F69) volatile __RXB0D3bits_t RXB0D3bits;
 334
 335 __at(0x0F6A) __sfr RXB0D4;
 336 __at(0x0F6A) volatile __RXB0D4bits_t RXB0D4bits;
 337
 338 __at(0x0F6B) __sfr RXB0D5;
 339 __at(0x0F6B) volatile __RXB0D5bits_t RXB0D5bits;
 340
 341 __at(0x0F6C) __sfr RXB0D6;
 342 __at(0x0F6C) volatile __RXB0D6bits_t RXB0D6bits;
 343
 344 __at(0x0F6D) __sfr RXB0D7;
 345 __at(0x0F6D) volatile __RXB0D7bits_t RXB0D7bits;
 346
 347 __at(0x0F6E) __sfr CANSTAT;
 348 __at(0x0F6E) volatile __CANSTATbits_t CANSTATbits;
 349
 350 __at(0x0F6F) __sfr CANCON;
 351 __at(0x0F6F) volatile __CANCONbits_t CANCONbits;
 352
 353 __at(0x0F70) __sfr BRGCON1;
 354 __at(0x0F70) volatile __BRGCON1bits_t BRGCON1bits;
 355
 356 __at(0x0F71) __sfr BRGCON2;
 357 __at(0x0F71) volatile __BRGCON2bits_t BRGCON2bits;
 358
 359 __at(0x0F72) __sfr BRGCON3;
 360 __at(0x0F72) volatile __BRGCON3bits_t BRGCON3bits;
 361
 362 __at(0x0F73) __sfr CIOCON;
 363 __at(0x0F73) volatile __CIOCONbits_t CIOCONbits;
 364
 365 __at(0x0F74) __sfr COMSTAT;
 366 __at(0x0F74) volatile __COMSTATbits_t COMSTATbits;
 367
 368 __at(0x0F75) __sfr RXERRCNT;
 369 __at(0x0F75) volatile __RXERRCNTbits_t RXERRCNTbits;
 370
 371 __at(0x0F76) __sfr TXERRCNT;
 372 __at(0x0F76) volatile __TXERRCNTbits_t TXERRCNTbits;
 373
 374 __at(0x0F80) __sfr PORTA;
 375 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 376
 377 __at(0x0F81) __sfr PORTB;
 378 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 379
 380 __at(0x0F82) __sfr PORTC;
 381 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 382
 383 __at(0x0F83) __sfr PORTD;
 384 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 385
 386 __at(0x0F84) __sfr PORTE;
 387 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 388
 389 __at(0x0F89) __sfr LATA;
 390 __at(0x0F89) volatile __LATAbits_t LATAbits;
 391
 392 __at(0x0F8A) __sfr LATB;
 393 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 394
 395 __at(0x0F8B) __sfr LATC;
 396 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 397
 398 __at(0x0F8C) __sfr LATD;
 399 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 400
 401 __at(0x0F8D) __sfr LATE;
 402 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 403
 404 __at(0x0F92) __sfr DDRA;
 405 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 406
 407 __at(0x0F92) __sfr TRISA;
 408 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 409
 410 __at(0x0F93) __sfr DDRB;
 411 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 412
 413 __at(0x0F93) __sfr TRISB;
 414 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 415
 416 __at(0x0F94) __sfr DDRC;
 417 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 418
 419 __at(0x0F94) __sfr TRISC;
 420 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 421
 422 __at(0x0F95) __sfr DDRD;
 423 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 424
 425 __at(0x0F95) __sfr TRISD;
 426 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 427
 428 __at(0x0F96) __sfr DDRE;
 429 __at(0x0F96) volatile __DDREbits_t DDREbits;
 430
 431 __at(0x0F96) __sfr TRISE;
 432 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 433
 434 __at(0x0F9D) __sfr PIE1;
 435 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 436
 437 __at(0x0F9E) __sfr PIR1;
 438 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 439
 440 __at(0x0F9F) __sfr IPR1;
 441 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 442
 443 __at(0x0FA0) __sfr PIE2;
 444 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 445
 446 __at(0x0FA1) __sfr PIR2;
 447 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 448
 449 __at(0x0FA2) __sfr IPR2;
 450 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 451
 452 __at(0x0FA3) __sfr PIE3;
 453 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 454
 455 __at(0x0FA4) __sfr PIR3;
 456 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 457
 458 __at(0x0FA5) __sfr IPR3;
 459 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 460
 461 __at(0x0FA6) __sfr EECON1;
 462 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 463
 464 __at(0x0FA7) __sfr EECON2;
 465
 466 __at(0x0FA8) __sfr EEDATA;
 467
 468 __at(0x0FA9) __sfr EEADR;
 469
 470 __at(0x0FAB) __sfr RCSTA;
 471 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 472
 473 __at(0x0FAC) __sfr TXSTA;
 474 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 475
 476 __at(0x0FAD) __sfr TXREG;
 477
 478 __at(0x0FAE) __sfr RCREG;
 479
 480 __at(0x0FAF) __sfr SPBRG;
 481
 482 __at(0x0FB1) __sfr T3CON;
 483 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 484
 485 __at(0x0FB2) __sfr TMR3;
 486
 487 __at(0x0FB2) __sfr TMR3L;
 488
 489 __at(0x0FB3) __sfr TMR3H;
 490
 491 __at(0x0FB4) __sfr CMCON;
 492 __at(0x0FB4) volatile __CMCONbits_t CMCONbits;
 493
 494 __at(0x0FB5) __sfr CVRCON;
 495 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits;
 496
 497 __at(0x0FB6) __sfr ECCPAS;
 498 __at(0x0FB6) volatile __ECCPASbits_t ECCPASbits;
 499
 500 __at(0x0FB7) __sfr ECCP1DEL;
 501 __at(0x0FB7) volatile __ECCP1DELbits_t ECCP1DELbits;
 502
 503 __at(0x0FBA) __sfr ECCP1CON;
 504 __at(0x0FBA) volatile __ECCP1CONbits_t ECCP1CONbits;
 505
 506 __at(0x0FBB) __sfr ECCPR1;
 507
 508 __at(0x0FBB) __sfr ECCPR1L;
 509
 510 __at(0x0FBC) __sfr ECCPR1H;
 511
 512 __at(0x0FBD) __sfr CCP1CON;
 513 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 514
 515 __at(0x0FBE) __sfr CCPR1;
 516
 517 __at(0x0FBE) __sfr CCPR1L;
 518
 519 __at(0x0FBF) __sfr CCPR1H;
 520
 521 __at(0x0FC1) __sfr ADCON1;
 522 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 523
 524 __at(0x0FC2) __sfr ADCON0;
 525 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 526
 527 __at(0x0FC3) __sfr ADRES;
 528
 529 __at(0x0FC3) __sfr ADRESL;
 530
 531 __at(0x0FC4) __sfr ADRESH;
 532
 533 __at(0x0FC5) __sfr SSPCON2;
 534 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 535
 536 __at(0x0FC6) __sfr SSPCON1;
 537 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 538
 539 __at(0x0FC7) __sfr SSPSTAT;
 540 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 541
 542 __at(0x0FC8) __sfr SSPADD;
 543
 544 __at(0x0FC9) __sfr SSPBUF;
 545
 546 __at(0x0FCA) __sfr T2CON;
 547 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 548
 549 __at(0x0FCB) __sfr PR2;
 550
 551 __at(0x0FCC) __sfr TMR2;
 552
 553 __at(0x0FCD) __sfr T1CON;
 554 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 555
 556 __at(0x0FCE) __sfr TMR1;
 557
 558 __at(0x0FCE) __sfr TMR1L;
 559
 560 __at(0x0FCF) __sfr TMR1H;
 561
 562 __at(0x0FD0) __sfr RCON;
 563 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 564
 565 __at(0x0FD1) __sfr WDTCON;
 566 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 567
 568 __at(0x0FD2) __sfr LVDCON;
 569 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits;
 570
 571 __at(0x0FD3) __sfr OSCCON;
 572 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 573
 574 __at(0x0FD5) __sfr T0CON;
 575 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 576
 577 __at(0x0FD6) __sfr TMR0;
 578
 579 __at(0x0FD6) __sfr TMR0L;
 580
 581 __at(0x0FD7) __sfr TMR0H;
 582
 583 __at(0x0FD8) __sfr STATUS;
 584 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 585
 586 __at(0x0FD9) __sfr FSR2L;
 587
 588 __at(0x0FDA) __sfr FSR2H;
 589
 590 __at(0x0FDB) __sfr PLUSW2;
 591
 592 __at(0x0FDC) __sfr PREINC2;
 593
 594 __at(0x0FDD) __sfr POSTDEC2;
 595
 596 __at(0x0FDE) __sfr POSTINC2;
 597
 598 __at(0x0FDF) __sfr INDF2;
 599
 600 __at(0x0FE0) __sfr BSR;
 601
 602 __at(0x0FE1) __sfr FSR1L;
 603
 604 __at(0x0FE2) __sfr FSR1H;
 605
 606 __at(0x0FE3) __sfr PLUSW1;
 607
 608 __at(0x0FE4) __sfr PREINC1;
 609
 610 __at(0x0FE5) __sfr POSTDEC1;
 611
 612 __at(0x0FE6) __sfr POSTINC1;
 613
 614 __at(0x0FE7) __sfr INDF1;
 615
 616 __at(0x0FE8) __sfr WREG;
 617
 618 __at(0x0FE9) __sfr FSR0L;
 619
 620 __at(0x0FEA) __sfr FSR0H;
 621
 622 __at(0x0FEB) __sfr PLUSW0;
 623
 624 __at(0x0FEC) __sfr PREINC0;
 625
 626 __at(0x0FED) __sfr POSTDEC0;
 627
 628 __at(0x0FEE) __sfr POSTINC0;
 629
 630 __at(0x0FEF) __sfr INDF0;
 631
 632 __at(0x0FF0) __sfr INTCON3;
 633 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 634
 635 __at(0x0FF1) __sfr INTCON2;
 636 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 637
 638 __at(0x0FF2) __sfr INTCON;
 639 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 640
 641 __at(0x0FF2) __sfr INTCON1;
 642 __at(0x0FF2) volatile __INTCON1bits_t INTCON1bits;
 643
 644 __at(0x0FF3) __sfr PROD;
 645
 646 __at(0x0FF3) __sfr PRODL;
 647
 648 __at(0x0FF4) __sfr PRODH;
 649
 650 __at(0x0FF5) __sfr TABLAT;
 651
 652 __at(0x0FF6) __sfr TBLPTR;
 653
 654 __at(0x0FF6) __sfr TBLPTRL;
 655
 656 __at(0x0FF7) __sfr TBLPTRH;
 657
 658 __at(0x0FF8) __sfr TBLPTRU;
 659
 660 __at(0x0FF9) __sfr PC;
 661
 662 __at(0x0FF9) __sfr PCL;
 663
 664 __at(0x0FFA) __sfr PCLATH;
 665
 666 __at(0x0FFB) __sfr PCLATU;
 667
 668 __at(0x0FFC) __sfr STKPTR;
 669 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 670
 671 __at(0x0FFD) __sfr TOS;
 672
 673 __at(0x0FFD) __sfr TOSL;
 674
 675 __at(0x0FFE) __sfr TOSH;
 676
 677 __at(0x0FFF) __sfr TOSU;