sdcc/device/non-free/lib/pic16/libdev/pic18lf45k50.c

   1 /*
   2  * This definitions of the PIC18LF45K50 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:56 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18lf45k50.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F57) __sfr SRCON1;
  30 __at(0x0F57) volatile __SRCON1bits_t SRCON1bits;
  31
  32 __at(0x0F58) __sfr SRCON0;
  33 __at(0x0F58) volatile __SRCON0bits_t SRCON0bits;
  34
  35 __at(0x0F59) __sfr CCPTMRS;
  36 __at(0x0F59) volatile __CCPTMRSbits_t CCPTMRSbits;
  37
  38 __at(0x0F5B) __sfr ANSELA;
  39 __at(0x0F5B) volatile __ANSELAbits_t ANSELAbits;
  40
  41 __at(0x0F5C) __sfr ANSELB;
  42 __at(0x0F5C) volatile __ANSELBbits_t ANSELBbits;
  43
  44 __at(0x0F5D) __sfr ANSELC;
  45 __at(0x0F5D) volatile __ANSELCbits_t ANSELCbits;
  46
  47 __at(0x0F5E) __sfr ANSELD;
  48 __at(0x0F5E) volatile __ANSELDbits_t ANSELDbits;
  49
  50 __at(0x0F5F) __sfr ANSELE;
  51 __at(0x0F5F) volatile __ANSELEbits_t ANSELEbits;
  52
  53 __at(0x0F60) __sfr UCON;
  54 __at(0x0F60) volatile __UCONbits_t UCONbits;
  55
  56 __at(0x0F61) __sfr USTAT;
  57 __at(0x0F61) volatile __USTATbits_t USTATbits;
  58
  59 __at(0x0F62) __sfr UCFG;
  60 __at(0x0F62) volatile __UCFGbits_t UCFGbits;
  61
  62 __at(0x0F63) __sfr UADDR;
  63 __at(0x0F63) volatile __UADDRbits_t UADDRbits;
  64
  65 __at(0x0F64) __sfr UIE;
  66 __at(0x0F64) volatile __UIEbits_t UIEbits;
  67
  68 __at(0x0F65) __sfr UIR;
  69 __at(0x0F65) volatile __UIRbits_t UIRbits;
  70
  71 __at(0x0F66) __sfr UEIE;
  72 __at(0x0F66) volatile __UEIEbits_t UEIEbits;
  73
  74 __at(0x0F67) __sfr UEIR;
  75 __at(0x0F67) volatile __UEIRbits_t UEIRbits;
  76
  77 __at(0x0F68) __sfr UFRM;
  78
  79 __at(0x0F68) __sfr UFRML;
  80 __at(0x0F68) volatile __UFRMLbits_t UFRMLbits;
  81
  82 __at(0x0F69) __sfr UFRMH;
  83 __at(0x0F69) volatile __UFRMHbits_t UFRMHbits;
  84
  85 __at(0x0F6A) __sfr UEP0;
  86 __at(0x0F6A) volatile __UEP0bits_t UEP0bits;
  87
  88 __at(0x0F6B) __sfr UEP1;
  89 __at(0x0F6B) volatile __UEP1bits_t UEP1bits;
  90
  91 __at(0x0F6C) __sfr UEP2;
  92 __at(0x0F6C) volatile __UEP2bits_t UEP2bits;
  93
  94 __at(0x0F6D) __sfr UEP3;
  95 __at(0x0F6D) volatile __UEP3bits_t UEP3bits;
  96
  97 __at(0x0F6E) __sfr UEP4;
  98 __at(0x0F6E) volatile __UEP4bits_t UEP4bits;
  99
 100 __at(0x0F6F) __sfr UEP5;
 101 __at(0x0F6F) volatile __UEP5bits_t UEP5bits;
 102
 103 __at(0x0F70) __sfr UEP6;
 104 __at(0x0F70) volatile __UEP6bits_t UEP6bits;
 105
 106 __at(0x0F71) __sfr UEP7;
 107 __at(0x0F71) volatile __UEP7bits_t UEP7bits;
 108
 109 __at(0x0F72) __sfr UEP8;
 110 __at(0x0F72) volatile __UEP8bits_t UEP8bits;
 111
 112 __at(0x0F73) __sfr UEP9;
 113 __at(0x0F73) volatile __UEP9bits_t UEP9bits;
 114
 115 __at(0x0F74) __sfr UEP10;
 116 __at(0x0F74) volatile __UEP10bits_t UEP10bits;
 117
 118 __at(0x0F75) __sfr UEP11;
 119 __at(0x0F75) volatile __UEP11bits_t UEP11bits;
 120
 121 __at(0x0F76) __sfr UEP12;
 122 __at(0x0F76) volatile __UEP12bits_t UEP12bits;
 123
 124 __at(0x0F77) __sfr UEP13;
 125 __at(0x0F77) volatile __UEP13bits_t UEP13bits;
 126
 127 __at(0x0F78) __sfr UEP14;
 128 __at(0x0F78) volatile __UEP14bits_t UEP14bits;
 129
 130 __at(0x0F79) __sfr UEP15;
 131 __at(0x0F79) volatile __UEP15bits_t UEP15bits;
 132
 133 __at(0x0F7A) __sfr SLRCON;
 134 __at(0x0F7A) volatile __SLRCONbits_t SLRCONbits;
 135
 136 __at(0x0F7B) __sfr VREFCON2;
 137 __at(0x0F7B) volatile __VREFCON2bits_t VREFCON2bits;
 138
 139 __at(0x0F7C) __sfr VREFCON1;
 140 __at(0x0F7C) volatile __VREFCON1bits_t VREFCON1bits;
 141
 142 __at(0x0F7D) __sfr VREFCON0;
 143 __at(0x0F7D) volatile __VREFCON0bits_t VREFCON0bits;
 144
 145 __at(0x0F7E) __sfr PMD0;
 146 __at(0x0F7E) volatile __PMD0bits_t PMD0bits;
 147
 148 __at(0x0F7F) __sfr PMD1;
 149 __at(0x0F7F) volatile __PMD1bits_t PMD1bits;
 150
 151 __at(0x0F80) __sfr PORTA;
 152 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
 153
 154 __at(0x0F81) __sfr PORTB;
 155 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
 156
 157 __at(0x0F82) __sfr PORTC;
 158 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
 159
 160 __at(0x0F83) __sfr PORTD;
 161 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
 162
 163 __at(0x0F84) __sfr PORTE;
 164 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
 165
 166 __at(0x0F85) __sfr WPUB;
 167 __at(0x0F85) volatile __WPUBbits_t WPUBbits;
 168
 169 __at(0x0F86) __sfr IOCB;
 170 __at(0x0F86) volatile __IOCBbits_t IOCBbits;
 171
 172 __at(0x0F87) __sfr IOCC;
 173 __at(0x0F87) volatile __IOCCbits_t IOCCbits;
 174
 175 __at(0x0F88) __sfr CTMUICON;
 176 __at(0x0F88) volatile __CTMUICONbits_t CTMUICONbits;
 177
 178 __at(0x0F89) __sfr LATA;
 179 __at(0x0F89) volatile __LATAbits_t LATAbits;
 180
 181 __at(0x0F8A) __sfr LATB;
 182 __at(0x0F8A) volatile __LATBbits_t LATBbits;
 183
 184 __at(0x0F8B) __sfr LATC;
 185 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 186
 187 __at(0x0F8C) __sfr LATD;
 188 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 189
 190 __at(0x0F8D) __sfr LATE;
 191 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 192
 193 __at(0x0F8E) __sfr CTMUCON1;
 194 __at(0x0F8E) volatile __CTMUCON1bits_t CTMUCON1bits;
 195
 196 __at(0x0F8E) __sfr CTMUCONL;
 197 __at(0x0F8E) volatile __CTMUCONLbits_t CTMUCONLbits;
 198
 199 __at(0x0F8F) __sfr CTMUCON0;
 200 __at(0x0F8F) volatile __CTMUCON0bits_t CTMUCON0bits;
 201
 202 __at(0x0F8F) __sfr CTMUCONH;
 203 __at(0x0F8F) volatile __CTMUCONHbits_t CTMUCONHbits;
 204
 205 __at(0x0F90) __sfr CCPR2;
 206
 207 __at(0x0F90) __sfr CCPR2L;
 208
 209 __at(0x0F91) __sfr CCPR2H;
 210
 211 __at(0x0F92) __sfr DDRA;
 212 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 213
 214 __at(0x0F92) __sfr TRISA;
 215 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 216
 217 __at(0x0F93) __sfr DDRB;
 218 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 219
 220 __at(0x0F93) __sfr TRISB;
 221 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 222
 223 __at(0x0F94) __sfr DDRC;
 224 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 225
 226 __at(0x0F94) __sfr TRISC;
 227 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 228
 229 __at(0x0F95) __sfr DDRD;
 230 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 231
 232 __at(0x0F95) __sfr TRISD;
 233 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 234
 235 __at(0x0F96) __sfr DDRE;
 236 __at(0x0F96) volatile __DDREbits_t DDREbits;
 237
 238 __at(0x0F96) __sfr TRISE;
 239 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 240
 241 __at(0x0F97) __sfr CCP2CON;
 242 __at(0x0F97) volatile __CCP2CONbits_t CCP2CONbits;
 243
 244 __at(0x0F97) __sfr ECCP2CON;
 245 __at(0x0F97) volatile __ECCP2CONbits_t ECCP2CONbits;
 246
 247 __at(0x0F98) __sfr CM1CON0;
 248 __at(0x0F98) volatile __CM1CON0bits_t CM1CON0bits;
 249
 250 __at(0x0F99) __sfr CM2CON0;
 251 __at(0x0F99) volatile __CM2CON0bits_t CM2CON0bits;
 252
 253 __at(0x0F9A) __sfr CM2CON1;
 254 __at(0x0F9A) volatile __CM2CON1bits_t CM2CON1bits;
 255
 256 __at(0x0F9B) __sfr OSCTUNE;
 257 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits;
 258
 259 __at(0x0F9C) __sfr HLVDCON;
 260 __at(0x0F9C) volatile __HLVDCONbits_t HLVDCONbits;
 261
 262 __at(0x0F9D) __sfr PIE1;
 263 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 264
 265 __at(0x0F9E) __sfr PIR1;
 266 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 267
 268 __at(0x0F9F) __sfr IPR1;
 269 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 270
 271 __at(0x0FA0) __sfr PIE2;
 272 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 273
 274 __at(0x0FA1) __sfr PIR2;
 275 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 276
 277 __at(0x0FA2) __sfr IPR2;
 278 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 279
 280 __at(0x0FA3) __sfr PIE3;
 281 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 282
 283 __at(0x0FA4) __sfr PIR3;
 284 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 285
 286 __at(0x0FA5) __sfr IPR3;
 287 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 288
 289 __at(0x0FA6) __sfr EECON1;
 290 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 291
 292 __at(0x0FA7) __sfr EECON2;
 293
 294 __at(0x0FA8) __sfr EEDATA;
 295
 296 __at(0x0FA9) __sfr EEADR;
 297
 298 __at(0x0FAB) __sfr RCSTA;
 299 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 300
 301 __at(0x0FAB) __sfr RCSTA1;
 302 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits;
 303
 304 __at(0x0FAC) __sfr TXSTA;
 305 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 306
 307 __at(0x0FAC) __sfr TXSTA1;
 308 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits;
 309
 310 __at(0x0FAD) __sfr TXREG;
 311
 312 __at(0x0FAD) __sfr TXREG1;
 313
 314 __at(0x0FAE) __sfr RCREG;
 315
 316 __at(0x0FAE) __sfr RCREG1;
 317
 318 __at(0x0FAF) __sfr SPBRG;
 319 __at(0x0FAF) volatile __SPBRGbits_t SPBRGbits;
 320
 321 __at(0x0FAF) __sfr SPBRG1;
 322 __at(0x0FAF) volatile __SPBRG1bits_t SPBRG1bits;
 323
 324 __at(0x0FB0) __sfr SPBRGH;
 325 __at(0x0FB0) volatile __SPBRGHbits_t SPBRGHbits;
 326
 327 __at(0x0FB0) __sfr SPBRGH1;
 328 __at(0x0FB0) volatile __SPBRGH1bits_t SPBRGH1bits;
 329
 330 __at(0x0FB1) __sfr T3CON;
 331 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 332
 333 __at(0x0FB2) __sfr TMR3;
 334
 335 __at(0x0FB2) __sfr TMR3L;
 336
 337 __at(0x0FB3) __sfr TMR3H;
 338
 339 __at(0x0FB4) __sfr T3GCON;
 340 __at(0x0FB4) volatile __T3GCONbits_t T3GCONbits;
 341
 342 __at(0x0FB5) __sfr ACTCON;
 343 __at(0x0FB5) volatile __ACTCONbits_t ACTCONbits;
 344
 345 __at(0x0FB5) __sfr STCON;
 346 __at(0x0FB5) volatile __STCONbits_t STCONbits;
 347
 348 __at(0x0FB6) __sfr ECCP1AS;
 349 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits;
 350
 351 __at(0x0FB7) __sfr ECCP1DEL;
 352 __at(0x0FB7) volatile __ECCP1DELbits_t ECCP1DELbits;
 353
 354 __at(0x0FB7) __sfr PWM1CON;
 355 __at(0x0FB7) volatile __PWM1CONbits_t PWM1CONbits;
 356
 357 __at(0x0FB8) __sfr BAUDCON;
 358 __at(0x0FB8) volatile __BAUDCONbits_t BAUDCONbits;
 359
 360 __at(0x0FB8) __sfr BAUDCON1;
 361 __at(0x0FB8) volatile __BAUDCON1bits_t BAUDCON1bits;
 362
 363 __at(0x0FB9) __sfr PSTR1CON;
 364 __at(0x0FB9) volatile __PSTR1CONbits_t PSTR1CONbits;
 365
 366 __at(0x0FBA) __sfr T2CON;
 367 __at(0x0FBA) volatile __T2CONbits_t T2CONbits;
 368
 369 __at(0x0FBB) __sfr PR2;
 370
 371 __at(0x0FBC) __sfr TMR2;
 372
 373 __at(0x0FBD) __sfr CCP1CON;
 374 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 375
 376 __at(0x0FBD) __sfr ECCP1CON;
 377 __at(0x0FBD) volatile __ECCP1CONbits_t ECCP1CONbits;
 378
 379 __at(0x0FBE) __sfr CCPR1;
 380
 381 __at(0x0FBE) __sfr CCPR1L;
 382
 383 __at(0x0FBF) __sfr CCPR1H;
 384
 385 __at(0x0FC0) __sfr ADCON2;
 386 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 387
 388 __at(0x0FC1) __sfr ADCON1;
 389 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 390
 391 __at(0x0FC2) __sfr ADCON0;
 392 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 393
 394 __at(0x0FC3) __sfr ADRESL;
 395
 396 __at(0x0FC4) __sfr ADRESH;
 397
 398 __at(0x0FC5) __sfr SSP1CON2;
 399 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits;
 400
 401 __at(0x0FC5) __sfr SSPCON2;
 402 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 403
 404 __at(0x0FC6) __sfr SSP1CON1;
 405 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits;
 406
 407 __at(0x0FC6) __sfr SSPCON;
 408 __at(0x0FC6) volatile __SSPCONbits_t SSPCONbits;
 409
 410 __at(0x0FC6) __sfr SSPCON1;
 411 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 412
 413 __at(0x0FC7) __sfr SSP1STAT;
 414 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits;
 415
 416 __at(0x0FC7) __sfr SSPSTAT;
 417 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 418
 419 __at(0x0FC8) __sfr SSP1ADD;
 420 __at(0x0FC8) volatile __SSP1ADDbits_t SSP1ADDbits;
 421
 422 __at(0x0FC8) __sfr SSPADD;
 423 __at(0x0FC8) volatile __SSPADDbits_t SSPADDbits;
 424
 425 __at(0x0FC9) __sfr SSP1BUF;
 426
 427 __at(0x0FC9) __sfr SSPBUF;
 428
 429 __at(0x0FCA) __sfr SSP1MSK;
 430 __at(0x0FCA) volatile __SSP1MSKbits_t SSP1MSKbits;
 431
 432 __at(0x0FCA) __sfr SSPMSK;
 433 __at(0x0FCA) volatile __SSPMSKbits_t SSPMSKbits;
 434
 435 __at(0x0FCB) __sfr SSP1CON3;
 436 __at(0x0FCB) volatile __SSP1CON3bits_t SSP1CON3bits;
 437
 438 __at(0x0FCB) __sfr SSPCON3;
 439 __at(0x0FCB) volatile __SSPCON3bits_t SSPCON3bits;
 440
 441 __at(0x0FCC) __sfr T1GCON;
 442 __at(0x0FCC) volatile __T1GCONbits_t T1GCONbits;
 443
 444 __at(0x0FCD) __sfr T1CON;
 445 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 446
 447 __at(0x0FCE) __sfr TMR1;
 448
 449 __at(0x0FCE) __sfr TMR1L;
 450
 451 __at(0x0FCF) __sfr TMR1H;
 452
 453 __at(0x0FD0) __sfr RCON;
 454 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 455
 456 __at(0x0FD1) __sfr WDTCON;
 457 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 458
 459 __at(0x0FD2) __sfr OSCCON2;
 460 __at(0x0FD2) volatile __OSCCON2bits_t OSCCON2bits;
 461
 462 __at(0x0FD3) __sfr OSCCON;
 463 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 464
 465 __at(0x0FD5) __sfr T0CON;
 466 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 467
 468 __at(0x0FD6) __sfr TMR0;
 469
 470 __at(0x0FD6) __sfr TMR0L;
 471
 472 __at(0x0FD7) __sfr TMR0H;
 473
 474 __at(0x0FD8) __sfr STATUS;
 475 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 476
 477 __at(0x0FD9) __sfr FSR2L;
 478
 479 __at(0x0FDA) __sfr FSR2H;
 480
 481 __at(0x0FDB) __sfr PLUSW2;
 482
 483 __at(0x0FDC) __sfr PREINC2;
 484
 485 __at(0x0FDD) __sfr POSTDEC2;
 486
 487 __at(0x0FDE) __sfr POSTINC2;
 488
 489 __at(0x0FDF) __sfr INDF2;
 490
 491 __at(0x0FE0) __sfr BSR;
 492
 493 __at(0x0FE1) __sfr FSR1L;
 494
 495 __at(0x0FE2) __sfr FSR1H;
 496
 497 __at(0x0FE3) __sfr PLUSW1;
 498
 499 __at(0x0FE4) __sfr PREINC1;
 500
 501 __at(0x0FE5) __sfr POSTDEC1;
 502
 503 __at(0x0FE6) __sfr POSTINC1;
 504
 505 __at(0x0FE7) __sfr INDF1;
 506
 507 __at(0x0FE8) __sfr WREG;
 508
 509 __at(0x0FE9) __sfr FSR0L;
 510
 511 __at(0x0FEA) __sfr FSR0H;
 512
 513 __at(0x0FEB) __sfr PLUSW0;
 514
 515 __at(0x0FEC) __sfr PREINC0;
 516
 517 __at(0x0FED) __sfr POSTDEC0;
 518
 519 __at(0x0FEE) __sfr POSTINC0;
 520
 521 __at(0x0FEF) __sfr INDF0;
 522
 523 __at(0x0FF0) __sfr INTCON3;
 524 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 525
 526 __at(0x0FF1) __sfr INTCON2;
 527 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 528
 529 __at(0x0FF2) __sfr INTCON;
 530 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 531
 532 __at(0x0FF3) __sfr PROD;
 533
 534 __at(0x0FF3) __sfr PRODL;
 535
 536 __at(0x0FF4) __sfr PRODH;
 537
 538 __at(0x0FF5) __sfr TABLAT;
 539
 540 __at(0x0FF6) __sfr TBLPTR;
 541
 542 __at(0x0FF6) __sfr TBLPTRL;
 543
 544 __at(0x0FF7) __sfr TBLPTRH;
 545
 546 __at(0x0FF8) __sfr TBLPTRU;
 547
 548 __at(0x0FF9) __sfr PC;
 549
 550 __at(0x0FF9) __sfr PCL;
 551
 552 __at(0x0FFA) __sfr PCLATH;
 553
 554 __at(0x0FFB) __sfr PCLATU;
 555
 556 __at(0x0FFC) __sfr STKPTR;
 557 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 558
 559 __at(0x0FFD) __sfr TOS;
 560
 561 __at(0x0FFD) __sfr TOSL;
 562
 563 __at(0x0FFE) __sfr TOSH;
 564
 565 __at(0x0FFF) __sfr TOSU;