sdcc/device/non-free/lib/pic16/libdev/pic18lf8720.c

   1 /*
   2  * This definitions of the PIC18LF8720 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:24:09 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic18lf8720.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0F6B) __sfr RCSTA2;
  30 __at(0x0F6B) volatile __RCSTA2bits_t RCSTA2bits;
  31
  32 __at(0x0F6C) __sfr TXSTA2;
  33 __at(0x0F6C) volatile __TXSTA2bits_t TXSTA2bits;
  34
  35 __at(0x0F6D) __sfr TXREG2;
  36
  37 __at(0x0F6E) __sfr RCREG2;
  38
  39 __at(0x0F6F) __sfr SPBRG2;
  40
  41 __at(0x0F70) __sfr CCP5CON;
  42 __at(0x0F70) volatile __CCP5CONbits_t CCP5CONbits;
  43
  44 __at(0x0F71) __sfr CCPR5;
  45
  46 __at(0x0F71) __sfr CCPR5L;
  47
  48 __at(0x0F72) __sfr CCPR5H;
  49
  50 __at(0x0F73) __sfr CCP4CON;
  51 __at(0x0F73) volatile __CCP4CONbits_t CCP4CONbits;
  52
  53 __at(0x0F74) __sfr CCPR4;
  54
  55 __at(0x0F74) __sfr CCPR4L;
  56
  57 __at(0x0F75) __sfr CCPR4H;
  58
  59 __at(0x0F76) __sfr T4CON;
  60 __at(0x0F76) volatile __T4CONbits_t T4CONbits;
  61
  62 __at(0x0F77) __sfr PR4;
  63
  64 __at(0x0F78) __sfr TMR4;
  65
  66 __at(0x0F80) __sfr PORTA;
  67 __at(0x0F80) volatile __PORTAbits_t PORTAbits;
  68
  69 __at(0x0F81) __sfr PORTB;
  70 __at(0x0F81) volatile __PORTBbits_t PORTBbits;
  71
  72 __at(0x0F82) __sfr PORTC;
  73 __at(0x0F82) volatile __PORTCbits_t PORTCbits;
  74
  75 __at(0x0F83) __sfr PORTD;
  76 __at(0x0F83) volatile __PORTDbits_t PORTDbits;
  77
  78 __at(0x0F84) __sfr PORTE;
  79 __at(0x0F84) volatile __PORTEbits_t PORTEbits;
  80
  81 __at(0x0F85) __sfr PORTF;
  82 __at(0x0F85) volatile __PORTFbits_t PORTFbits;
  83
  84 __at(0x0F86) __sfr PORTG;
  85 __at(0x0F86) volatile __PORTGbits_t PORTGbits;
  86
  87 __at(0x0F87) __sfr PORTH;
  88 __at(0x0F87) volatile __PORTHbits_t PORTHbits;
  89
  90 __at(0x0F88) __sfr PORTJ;
  91 __at(0x0F88) volatile __PORTJbits_t PORTJbits;
  92
  93 __at(0x0F89) __sfr LATA;
  94 __at(0x0F89) volatile __LATAbits_t LATAbits;
  95
  96 __at(0x0F8A) __sfr LATB;
  97 __at(0x0F8A) volatile __LATBbits_t LATBbits;
  98
  99 __at(0x0F8B) __sfr LATC;
 100 __at(0x0F8B) volatile __LATCbits_t LATCbits;
 101
 102 __at(0x0F8C) __sfr LATD;
 103 __at(0x0F8C) volatile __LATDbits_t LATDbits;
 104
 105 __at(0x0F8D) __sfr LATE;
 106 __at(0x0F8D) volatile __LATEbits_t LATEbits;
 107
 108 __at(0x0F8E) __sfr LATF;
 109 __at(0x0F8E) volatile __LATFbits_t LATFbits;
 110
 111 __at(0x0F8F) __sfr LATG;
 112 __at(0x0F8F) volatile __LATGbits_t LATGbits;
 113
 114 __at(0x0F90) __sfr LATH;
 115 __at(0x0F90) volatile __LATHbits_t LATHbits;
 116
 117 __at(0x0F91) __sfr LATJ;
 118 __at(0x0F91) volatile __LATJbits_t LATJbits;
 119
 120 __at(0x0F92) __sfr DDRA;
 121 __at(0x0F92) volatile __DDRAbits_t DDRAbits;
 122
 123 __at(0x0F92) __sfr TRISA;
 124 __at(0x0F92) volatile __TRISAbits_t TRISAbits;
 125
 126 __at(0x0F93) __sfr DDRB;
 127 __at(0x0F93) volatile __DDRBbits_t DDRBbits;
 128
 129 __at(0x0F93) __sfr TRISB;
 130 __at(0x0F93) volatile __TRISBbits_t TRISBbits;
 131
 132 __at(0x0F94) __sfr DDRC;
 133 __at(0x0F94) volatile __DDRCbits_t DDRCbits;
 134
 135 __at(0x0F94) __sfr TRISC;
 136 __at(0x0F94) volatile __TRISCbits_t TRISCbits;
 137
 138 __at(0x0F95) __sfr DDRD;
 139 __at(0x0F95) volatile __DDRDbits_t DDRDbits;
 140
 141 __at(0x0F95) __sfr TRISD;
 142 __at(0x0F95) volatile __TRISDbits_t TRISDbits;
 143
 144 __at(0x0F96) __sfr DDRE;
 145 __at(0x0F96) volatile __DDREbits_t DDREbits;
 146
 147 __at(0x0F96) __sfr TRISE;
 148 __at(0x0F96) volatile __TRISEbits_t TRISEbits;
 149
 150 __at(0x0F97) __sfr DDRF;
 151 __at(0x0F97) volatile __DDRFbits_t DDRFbits;
 152
 153 __at(0x0F97) __sfr TRISF;
 154 __at(0x0F97) volatile __TRISFbits_t TRISFbits;
 155
 156 __at(0x0F98) __sfr DDRG;
 157 __at(0x0F98) volatile __DDRGbits_t DDRGbits;
 158
 159 __at(0x0F98) __sfr TRISG;
 160 __at(0x0F98) volatile __TRISGbits_t TRISGbits;
 161
 162 __at(0x0F99) __sfr DDRH;
 163 __at(0x0F99) volatile __DDRHbits_t DDRHbits;
 164
 165 __at(0x0F99) __sfr TRISH;
 166 __at(0x0F99) volatile __TRISHbits_t TRISHbits;
 167
 168 __at(0x0F9A) __sfr DDRJ;
 169 __at(0x0F9A) volatile __DDRJbits_t DDRJbits;
 170
 171 __at(0x0F9A) __sfr TRISJ;
 172 __at(0x0F9A) volatile __TRISJbits_t TRISJbits;
 173
 174 __at(0x0F9C) __sfr MEMCON;
 175 __at(0x0F9C) volatile __MEMCONbits_t MEMCONbits;
 176
 177 __at(0x0F9D) __sfr PIE1;
 178 __at(0x0F9D) volatile __PIE1bits_t PIE1bits;
 179
 180 __at(0x0F9E) __sfr PIR1;
 181 __at(0x0F9E) volatile __PIR1bits_t PIR1bits;
 182
 183 __at(0x0F9F) __sfr IPR1;
 184 __at(0x0F9F) volatile __IPR1bits_t IPR1bits;
 185
 186 __at(0x0FA0) __sfr PIE2;
 187 __at(0x0FA0) volatile __PIE2bits_t PIE2bits;
 188
 189 __at(0x0FA1) __sfr PIR2;
 190 __at(0x0FA1) volatile __PIR2bits_t PIR2bits;
 191
 192 __at(0x0FA2) __sfr IPR2;
 193 __at(0x0FA2) volatile __IPR2bits_t IPR2bits;
 194
 195 __at(0x0FA3) __sfr PIE3;
 196 __at(0x0FA3) volatile __PIE3bits_t PIE3bits;
 197
 198 __at(0x0FA4) __sfr PIR3;
 199 __at(0x0FA4) volatile __PIR3bits_t PIR3bits;
 200
 201 __at(0x0FA5) __sfr IPR3;
 202 __at(0x0FA5) volatile __IPR3bits_t IPR3bits;
 203
 204 __at(0x0FA6) __sfr EECON1;
 205 __at(0x0FA6) volatile __EECON1bits_t EECON1bits;
 206
 207 __at(0x0FA7) __sfr EECON2;
 208
 209 __at(0x0FA8) __sfr EEDATA;
 210
 211 __at(0x0FA9) __sfr EEADR;
 212
 213 __at(0x0FAA) __sfr EEADRH;
 214
 215 __at(0x0FAB) __sfr RCSTA;
 216 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits;
 217
 218 __at(0x0FAB) __sfr RCSTA1;
 219 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits;
 220
 221 __at(0x0FAC) __sfr TXSTA;
 222 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits;
 223
 224 __at(0x0FAC) __sfr TXSTA1;
 225 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits;
 226
 227 __at(0x0FAD) __sfr TXREG;
 228
 229 __at(0x0FAD) __sfr TXREG1;
 230
 231 __at(0x0FAE) __sfr RCREG;
 232
 233 __at(0x0FAE) __sfr RCREG1;
 234
 235 __at(0x0FAF) __sfr SPBRG;
 236
 237 __at(0x0FAF) __sfr SPBRG1;
 238
 239 __at(0x0FB0) __sfr PSPCON;
 240 __at(0x0FB0) volatile __PSPCONbits_t PSPCONbits;
 241
 242 __at(0x0FB1) __sfr T3CON;
 243 __at(0x0FB1) volatile __T3CONbits_t T3CONbits;
 244
 245 __at(0x0FB2) __sfr TMR3;
 246
 247 __at(0x0FB2) __sfr TMR3L;
 248
 249 __at(0x0FB3) __sfr TMR3H;
 250
 251 __at(0x0FB4) __sfr CMCON;
 252 __at(0x0FB4) volatile __CMCONbits_t CMCONbits;
 253
 254 __at(0x0FB5) __sfr CVRCON;
 255 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits;
 256
 257 __at(0x0FB7) __sfr CCP3CON;
 258 __at(0x0FB7) volatile __CCP3CONbits_t CCP3CONbits;
 259
 260 __at(0x0FB8) __sfr CCPR3;
 261
 262 __at(0x0FB8) __sfr CCPR3L;
 263
 264 __at(0x0FB9) __sfr CCPR3H;
 265
 266 __at(0x0FBA) __sfr CCP2CON;
 267 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits;
 268
 269 __at(0x0FBB) __sfr CCPR2;
 270
 271 __at(0x0FBB) __sfr CCPR2L;
 272
 273 __at(0x0FBC) __sfr CCPR2H;
 274
 275 __at(0x0FBD) __sfr CCP1CON;
 276 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits;
 277
 278 __at(0x0FBE) __sfr CCPR1;
 279
 280 __at(0x0FBE) __sfr CCPR1L;
 281
 282 __at(0x0FBF) __sfr CCPR1H;
 283
 284 __at(0x0FC0) __sfr ADCON2;
 285 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits;
 286
 287 __at(0x0FC1) __sfr ADCON1;
 288 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits;
 289
 290 __at(0x0FC2) __sfr ADCON0;
 291 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits;
 292
 293 __at(0x0FC3) __sfr ADRES;
 294
 295 __at(0x0FC3) __sfr ADRESL;
 296
 297 __at(0x0FC4) __sfr ADRESH;
 298
 299 __at(0x0FC5) __sfr SSPCON2;
 300 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits;
 301
 302 __at(0x0FC6) __sfr SSPCON1;
 303 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits;
 304
 305 __at(0x0FC7) __sfr SSPSTAT;
 306 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits;
 307
 308 __at(0x0FC8) __sfr SSPADD;
 309
 310 __at(0x0FC9) __sfr SSPBUF;
 311
 312 __at(0x0FCA) __sfr T2CON;
 313 __at(0x0FCA) volatile __T2CONbits_t T2CONbits;
 314
 315 __at(0x0FCB) __sfr PR2;
 316
 317 __at(0x0FCC) __sfr TMR2;
 318
 319 __at(0x0FCD) __sfr T1CON;
 320 __at(0x0FCD) volatile __T1CONbits_t T1CONbits;
 321
 322 __at(0x0FCE) __sfr TMR1;
 323
 324 __at(0x0FCE) __sfr TMR1L;
 325
 326 __at(0x0FCF) __sfr TMR1H;
 327
 328 __at(0x0FD0) __sfr RCON;
 329 __at(0x0FD0) volatile __RCONbits_t RCONbits;
 330
 331 __at(0x0FD1) __sfr WDTCON;
 332 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits;
 333
 334 __at(0x0FD2) __sfr LVDCON;
 335 __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits;
 336
 337 __at(0x0FD3) __sfr OSCCON;
 338 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits;
 339
 340 __at(0x0FD5) __sfr T0CON;
 341 __at(0x0FD5) volatile __T0CONbits_t T0CONbits;
 342
 343 __at(0x0FD6) __sfr TMR0;
 344
 345 __at(0x0FD6) __sfr TMR0L;
 346
 347 __at(0x0FD7) __sfr TMR0H;
 348
 349 __at(0x0FD8) __sfr STATUS;
 350 __at(0x0FD8) volatile __STATUSbits_t STATUSbits;
 351
 352 __at(0x0FD9) __sfr FSR2L;
 353
 354 __at(0x0FDA) __sfr FSR2H;
 355
 356 __at(0x0FDB) __sfr PLUSW2;
 357
 358 __at(0x0FDC) __sfr PREINC2;
 359
 360 __at(0x0FDD) __sfr POSTDEC2;
 361
 362 __at(0x0FDE) __sfr POSTINC2;
 363
 364 __at(0x0FDF) __sfr INDF2;
 365
 366 __at(0x0FE0) __sfr BSR;
 367
 368 __at(0x0FE1) __sfr FSR1L;
 369
 370 __at(0x0FE2) __sfr FSR1H;
 371
 372 __at(0x0FE3) __sfr PLUSW1;
 373
 374 __at(0x0FE4) __sfr PREINC1;
 375
 376 __at(0x0FE5) __sfr POSTDEC1;
 377
 378 __at(0x0FE6) __sfr POSTINC1;
 379
 380 __at(0x0FE7) __sfr INDF1;
 381
 382 __at(0x0FE8) __sfr WREG;
 383
 384 __at(0x0FE9) __sfr FSR0L;
 385
 386 __at(0x0FEA) __sfr FSR0H;
 387
 388 __at(0x0FEB) __sfr PLUSW0;
 389
 390 __at(0x0FEC) __sfr PREINC0;
 391
 392 __at(0x0FED) __sfr POSTDEC0;
 393
 394 __at(0x0FEE) __sfr POSTINC0;
 395
 396 __at(0x0FEF) __sfr INDF0;
 397
 398 __at(0x0FF0) __sfr INTCON3;
 399 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits;
 400
 401 __at(0x0FF1) __sfr INTCON2;
 402 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits;
 403
 404 __at(0x0FF2) __sfr INTCON;
 405 __at(0x0FF2) volatile __INTCONbits_t INTCONbits;
 406
 407 __at(0x0FF2) __sfr INTCON1;
 408 __at(0x0FF2) volatile __INTCON1bits_t INTCON1bits;
 409
 410 __at(0x0FF3) __sfr PROD;
 411
 412 __at(0x0FF3) __sfr PRODL;
 413
 414 __at(0x0FF4) __sfr PRODH;
 415
 416 __at(0x0FF5) __sfr TABLAT;
 417
 418 __at(0x0FF6) __sfr TBLPTR;
 419
 420 __at(0x0FF6) __sfr TBLPTRL;
 421
 422 __at(0x0FF7) __sfr TBLPTRH;
 423
 424 __at(0x0FF8) __sfr TBLPTRU;
 425
 426 __at(0x0FF9) __sfr PC;
 427
 428 __at(0x0FF9) __sfr PCL;
 429
 430 __at(0x0FFA) __sfr PCLATH;
 431
 432 __at(0x0FFB) __sfr PCLATU;
 433
 434 __at(0x0FFC) __sfr STKPTR;
 435 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits;
 436
 437 __at(0x0FFD) __sfr TOS;
 438
 439 __at(0x0FFD) __sfr TOSL;
 440
 441 __at(0x0FFE) __sfr TOSH;
 442
 443 __at(0x0FFF) __sfr TOSU;