sdcc/sdas/astlcs90/t90mch.c

   1 /* t90mch.c */
   2
   3 /*
   4  *  Copyright (C) 2013 Rainer Keuchel
   5  *
   6  *  This program is free software: you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation, either version 3 of the License, or
   9  *  (at your option) any later version.
  10  *
  11  *  This program is distributed in the hope that it will be useful,
  12  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  *  GNU General Public License for more details.
  15  *
  16  *  You should have received a copy of the GNU General Public License
  17  *  along with this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #include <limits.h>
  21 #include "asxxxx.h"
  22 #include "t90.h"
  23
  24 #define IS_DIRECT_MEM(V) (((V) & 0xFF00) == 0xFF00)
  25
  26 // these fail on negative numbers..
  27 //#define IS_8BIT_IMMED(V) (((V) & 0xFF00) == 0x0)
  28 //#define IS_16BIT_IMMED(V) (((V) & 0xFFFF0000) == 0x0)
  29
  30 #define IS_8BIT_IMMED(V) 1
  31 #define IS_16BIT_IMMED(V) 1
  32 #define IS_REG_INDIRECT(T) ((T) >= S_IDBC && (T) <= S_IDSP)
  33 #define GET_IND_REG(T) ((T) - S_IDBC)
  34 #define GET_COND_FROM_MODE(V) ((V) & 0xFF)
  35
  36 char *cpu = "Toshiba TLCS90";
  37 char *dsft = "asm";
  38
  39 /*
  40  * Opcode Cycle Definitions (not yet)
  41  */
  42 #define OPCY_SDP        ((char) (0xFF))
  43 #define OPCY_ERR        ((char) (0xFE))
  44
  45 /*      OPCY_NONE       ((char) (0x80)) */
  46 /*      OPCY_MASK       ((char) (0x7F)) */
  47
  48 #define OPCY_CPU        ((char) (0xFD))
  49
  50 #define UN      ((char) (OPCY_NONE | 0x00))
  51 #define P2      ((char) (OPCY_NONE | 0x01))
  52 #define P3      ((char) (OPCY_NONE | 0x02))
  53 #define P4      ((char) (OPCY_NONE | 0x03))
  54 #define P5      ((char) (OPCY_NONE | 0x04))
  55 #define P6      ((char) (OPCY_NONE | 0x05))
  56 #define P7      ((char) (OPCY_NONE | 0x06))
  57
  58 /*
  59  * TLCS-90 Opcode Cycle Pages (NOT CHANGED FROM Z80 YET!)
  60  */
  61
  62 static char  t90pg1[256] = {
  63 /*--*--* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
  64 /*--*--* -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - */
  65 /*00*/   4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
  66 /*10*/  13,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
  67 /*20*/  12,10,16, 6, 4, 4, 7, 4,12,11,16, 6, 4, 4, 7, 4,
  68 /*30*/  12,10,13, 6,11,11,10, 4,12,11,13, 6, 4, 4, 7, 4,
  69 /*40*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
  70 /*50*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
  71 /*60*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
  72 /*70*/   7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
  73 /*80*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
  74 /*90*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
  75 /*A0*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
  76 /*B0*/   4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
  77 /*C0*/  11,10,10,10,17,11, 7,11,11,10,10,P2,17,17, 7,11,
  78 /*D0*/  11,10,10,11,17,11, 7,11,11, 4,10,11,17,P3, 7,11,
  79 /*E0*/  11,10,10,19,17,11, 7,11,11, 4,10, 4,17,P4, 7,11,
  80 /*F0*/  11,10,10, 4,17,11, 7,11,11, 6,10, 4,17,P5, 7,11
  81 };
  82
  83 static char  t90pg2[256] = {  /* P2 == CB */
  84 /*--*--* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
  85 /*--*--* -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - */
  86 /*00*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
  87 /*10*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
  88 /*20*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
  89 /*30*/  UN,UN,UN,UN,UN,UN,UN,UN, 8, 8, 8, 8, 8, 8,15, 8,
  90 /*40*/   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
  91 /*50*/   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
  92 /*60*/   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
  93 /*70*/   8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
  94 /*80*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
  95 /*90*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
  96 /*A0*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
  97 /*B0*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
  98 /*C0*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
  99 /*D0*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
 100 /*E0*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
 101 /*F0*/   8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8
 102 };
 103
 104 static char  t90pg3[256] = {  /* P3 == DD */
 105 /*--*--* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
 106 /*--*--* -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - */
 107 /*00*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,15,UN,UN,UN,UN,UN,UN,
 108 /*10*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,15,UN,UN,UN,UN,UN,UN,
 109 /*20*/  UN,14,20,10,UN,UN,UN,UN,UN,15,20,10,UN,UN,UN,UN,
 110 /*30*/  UN,UN,UN,UN,23,23,19,UN,UN,15,UN,UN,UN,UN,UN,UN,
 111 /*40*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 112 /*50*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 113 /*60*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 114 /*70*/  19,19,19,19,19,19,UN,19,UN,UN,UN,UN,UN,UN,19,UN,
 115 /*80*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 116 /*90*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 117 /*A0*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 118 /*B0*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 119 /*C0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,P6,UN,UN,UN,UN,
 120 /*D0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 121 /*E0*/  UN,14,UN,23,UN,15,UN,UN,UN, 8,UN,UN,UN,UN,UN,UN,
 122 /*F0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,10,UN,UN,UN,UN,UN,UN
 123 };
 124
 125 static char  t90pg4[256] = {  /* P4 == ED */
 126 /*--*--* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
 127 /*--*--* -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - */
 128 /*00*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 129 /*10*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 130 /*20*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 131 /*30*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 132 /*40*/  12,12,15,20, 8,14, 8, 9,12,12,15,20,UN,14,UN, 9,
 133 /*50*/  12,12,15,20,UN,UN, 8, 9,12,12,15,20,UN,UN, 8, 9,
 134 /*60*/  12,12,15,20,UN,UN,UN,18,12,12,15,20,UN,UN,UN,18,
 135 /*70*/  UN,UN,15,20,UN,UN,UN,UN,12,12,15,20,UN,UN,UN,UN,
 136 /*80*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 137 /*90*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 138 /*A0*/  16,16,16,16,UN,UN,UN,UN,16,16,16,16,UN,UN,UN,UN,
 139 /*B0*/  21,21,21,21,UN,UN,UN,UN,21,21,21,21,UN,UN,UN,UN,
 140 /*C0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 141 /*D0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 142 /*E0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 143 /*F0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN
 144 };
 145
 146 static char  t90pg5[256] = {  /* P5 == FD */
 147 /*--*--* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
 148 /*--*--* -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - */
 149 /*00*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,15,UN,UN,UN,UN,UN,UN,
 150 /*10*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,15,UN,UN,UN,UN,UN,UN,
 151 /*20*/  UN,14,20,10,UN,UN,UN,UN,UN,15,20,10,UN,UN,UN,UN,
 152 /*30*/  UN,UN,UN,UN,23,23,19,UN,UN,15,UN,UN,UN,UN,UN,UN,
 153 /*40*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 154 /*50*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 155 /*60*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 156 /*70*/  19,19,19,19,19,19,UN,19,UN,UN,UN,UN,UN,UN,19,UN,
 157 /*80*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 158 /*90*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 159 /*A0*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 160 /*B0*/  UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
 161 /*C0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,P7,UN,UN,UN,UN,
 162 /*D0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
 163 /*E0*/  UN,14,UN,23,UN,15,UN,UN,UN, 8,UN,UN,UN,UN,UN,UN,
 164 /*F0*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,10,UN,UN,UN,UN,UN,UN
 165 };
 166
 167 static char  t90pg6[256] = {  /* P6 == DD CB */
 168 /*--*--* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
 169 /*--*--* -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - */
 170 /*00*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 171 /*10*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 172 /*20*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 173 /*30*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,23,UN,
 174 /*40*/  UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
 175 /*50*/  UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
 176 /*60*/  UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
 177 /*70*/  UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
 178 /*80*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 179 /*90*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 180 /*A0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 181 /*B0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 182 /*C0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 183 /*D0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 184 /*E0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 185 /*F0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN
 186 };
 187
 188 static char  t90pg7[256] = {  /* P7 == FD CB */
 189 /*--*--* 0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F */
 190 /*--*--* -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - */
 191 /*00*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 192 /*10*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 193 /*20*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 194 /*30*/  UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,23,UN,
 195 /*40*/  UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
 196 /*50*/  UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
 197 /*60*/  UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
 198 /*70*/  UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
 199 /*80*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 200 /*90*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 201 /*A0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 202 /*B0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 203 /*C0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 204 /*D0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 205 /*E0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
 206 /*F0*/  UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN
 207 };
 208
 209 static char *t90Page[7] = {
 210   t90pg1, t90pg2, t90pg3, t90pg4,
 211   t90pg5, t90pg6, t90pg7
 212 };
 213
 214 int
 215 gen_xop_arith(int rf, int op, int t1, int t2, int v1, int v2, struct expr *e1, struct expr *e2)
 216 {
 217   if(IS_REG_INDIRECT(t1) && t2 == S_IMMED)
 218     {
 219       int r = GET_IND_REG(t1);
 220
 221       if(e1->e_addr == 0)
 222         {
 223           outab(0xe8 + r);
 224           outab(op);
 225           outab(v2);
 226         }
 227       else
 228         {
 229           if(r == HL) // HL+A
 230             {
 231               outab(0xf0 + 7);
 232               outab(op);
 233               outab(v2);
 234             }
 235           else
 236             {
 237               outab(0xf0 + r);
 238               outab(e1->e_addr & 0xFF);
 239               outab(op);
 240               outab(v2);
 241             }
 242         }
 243
 244       return 1;
 245     }
 246
 247   if(IS_REG_INDIRECT(t1) && t2 == S_R8)
 248     {
 249       // not allowed
 250       aerr();
 251
 252       return 1;
 253     }
 254
 255   if(IS_REG_INDIRECT(t1) && t2 == S_R16)
 256     {
 257       // TODO!
 258       aerr();
 259       return 1;
 260     }
 261
 262   if(t1 == S_R8 && IS_REG_INDIRECT(t2))
 263     {
 264       // TODO!
 265       aerr();
 266       return 1;
 267     }
 268
 269   if(t1 == S_R16 && IS_REG_INDIRECT(t2))
 270     {
 271       int r;
 272
 273       r = GET_IND_REG(t2);
 274
 275       if(e2->e_addr == 0)
 276         {
 277           outab(0xe0 + r);
 278
 279           if(v1 == HL)
 280             outab(op);
 281           else
 282             outab(op + v1);
 283         }
 284       else
 285         {
 286           if(r == HL)
 287             {
 288               if(v1 == HL)
 289                 {
 290                   if(e2->e_addr == 0)
 291                     {
 292                       outab(0xf3);
 293                       outab(op);
 294                     }
 295                   else
 296                     {
 297                       // HL+A
 298                       outab(0xf3);
 299                       outab(op);
 300                     }
 301                 }
 302               else
 303                 {
 304                   aerr();
 305                 }
 306             }
 307           else
 308             {
 309               outab((0xf0 - IX) + r);
 310               outab(e2->e_addr);
 311
 312               if(v1 == HL)
 313                 outab(op);
 314               else
 315                 outab(op + v1);
 316             }
 317         }
 318       return 1;
 319     }
 320
 321   if(t1 == S_R16 && t2 == S_R16)
 322     {
 323       outab(0xf8 + v2);
 324
 325       if(v1 == HL)
 326         outab(op + 0x10);
 327       else if(v1 == IX)
 328         outab(0x14);
 329       else if(v1 == IY)
 330         outab(0x15);
 331       else
 332         goto err;
 333
 334       return 1;
 335     }
 336
 337   if(t1 == S_R8 && t2 == S_INDM)
 338     {
 339       if(v1 == A)
 340         {
 341           if(IS_DIRECT_MEM(v2))
 342             {
 343               outab(op);
 344               outab(e2->e_addr & 0xFF);
 345               return 1;
 346             }
 347           else
 348             {
 349               outab(0xe3);
 350               outrw(e2, 0); // reloc..
 351               outab(op);
 352               return 1;
 353             }
 354
 355           goto err;
 356         }
 357
 358       return 1;
 359     }
 360
 361   if(t1 == S_R8 && t2 == S_IMMED)
 362     {
 363       outab(0xf8 + v1);
 364       outab(op);
 365       outab(v2);
 366       return 1;
 367     }
 368
 369   if(t1 == S_R16 && t2 == S_INDM)
 370     {
 371       if(IS_DIRECT_MEM(v2))
 372         {
 373           if(v1 == HL)
 374             {
 375               outab(op);
 376               outab(v2 & 0xFF);
 377               return 1;
 378             }
 379           else
 380             {
 381               outab(0xE7);
 382               outab(v2 & 0xFF);
 383               outab(op + v1);
 384               return 1;
 385             }
 386         }
 387       else
 388         {
 389           outab(0xE3);
 390           outrw(e2, 0); // reloc..
 391
 392           if(v1 == HL)
 393             outab(op);
 394           else
 395             outab(op + v1);
 396           return 1;
 397         }
 398
 399       goto err;
 400     }
 401
 402   if(t1 == S_R8 && t2 == S_R8)
 403     {
 404       outab(0xf8 + v2);
 405
 406       if(v1 == A)
 407         outab(op);
 408       else
 409         outab(op + v1);
 410       return 1;
 411     }
 412
 413   if(t1 == S_INDM && t2 == S_IMMED)
 414     {
 415       if(IS_DIRECT_MEM(v1))
 416         {
 417           outab(0xef);
 418           outab(v1 & 0xFF);
 419           outab(op);
 420           outab(v2);
 421           return 1;
 422         }
 423       else
 424         {
 425           outab(0xeb);
 426           outrw(e1, 0);
 427           outab(op);
 428           outab(v2);
 429           return 1;
 430         }
 431     }
 432
 433  err:
 434   aerr();
 435   return 0;
 436 }
 437
 438 /*
 439  * Process an insn..
 440  */
 441
 442 void
 443 machine(struct mne *mp)
 444 {
 445   int op, t1, t2, t3;
 446   struct expr e1, e2;
 447   int rf, v1, v2, v3;
 448
 449   clrexpr(&e1);
 450   clrexpr(&e2);
 451
 452   op = (int) mp->m_valu;
 453   rf = mp->m_type;
 454
 455   // NOTE: S_CPU must be max!?
 456
 457   if(rf > S_CPU)
 458     rf = 0;
 459
 460   switch (rf)
 461     {
 462     case S_PUSH:
 463       t1 = addr(&e1);
 464       v1 = (int) e1.e_addr;
 465
 466       if ((t1 == S_R16))
 467         {
 468           outab(op | (v1 & 0x0F));
 469           break;
 470         }
 471
 472       aerr();
 473       break;
 474
 475       //////////////////////////////////////////////////////////////////////
 476
 477     case S_LDA:
 478       t1 = addr(&e1);
 479       v1 = (int) e1.e_addr;
 480       comma(1);
 481       t2 = addr(&e2);
 482       v2 = (int) e2.e_addr;
 483       comma(1);
 484       t3 = addr(&e2);
 485       v3 = (int) e2.e_addr;
 486
 487       if (t1 == S_R16 && (t2 == S_R16) && (v2==IX || v2==IY || v2==SP) && t3 == S_IMMED)
 488         {
 489           outab(op + v2 - IX);
 490           outrb(&e2, R_SGND);
 491           outab(0x38 + (v1 & 0x0F));
 492           break;
 493         }
 494       if (t1 == S_R16 && (t2 == S_R16) && (v2==HL) && t3 == S_R8 && v3 == A)
 495         {
 496           outab(0xF7);
 497           outab(0x38 + (v1 & 0x0F));
 498           break;
 499         }
 500       aerr();
 501       break;
 502
 503     case S_INCX:
 504     case S_DECX:
 505       t1 = addr(&e1);
 506       v1 = (unsigned short) e1.e_addr;
 507
 508       // incx (0xff20)
 509       // decx (0xff20)
 510       if ((t1 == S_INDM) && (IS_DIRECT_MEM(v1)))
 511         {
 512           outab(op);
 513           outab(v1 & 0xff);
 514           break;
 515         }
 516
 517       aerr();
 518       break;
 519
 520       //////////////////////////////////////////////////////////////////////
 521
 522     case S_RET:
 523       if (more())
 524         {
 525           // ret cc
 526           if ((v1 = admode(CND)) != 0)
 527             {
 528               outab(0xFE);
 529
 530               outab(0xD0 | GET_COND_FROM_MODE(v1));
 531               break;
 532             }
 533           else
 534             {
 535               qerr();
 536             }
 537         }
 538       else
 539         {
 540           // ret
 541           outab(0x1E);
 542           break;
 543         }
 544
 545       aerr();
 546       break;
 547
 548       //////////////////////////////////////////////////////////////////////
 549
 550     case S_CALL:
 551       if ((v1 = admode(CND)) != 0)
 552         {
 553           // call cc
 554
 555           comma(1);
 556
 557           t1 = addr(&e1);
 558
 559           if (t1 == S_USER)
 560             {
 561               outab(0xEB);
 562               outrw(&e1, 0);
 563               outab(0xD0 + GET_COND_FROM_MODE(v1));
 564               break;
 565             }
 566         }
 567       else
 568         {
 569           t1 = addr(&e1);
 570
 571           op = 0x1C;
 572
 573           if (t1 == S_USER)
 574             {
 575               outab(op);
 576               outrw(&e1, 0);
 577               break;
 578             }
 579           else if (IS_REG_INDIRECT(t1))
 580             {
 581               int r = GET_IND_REG(t1);
 582
 583               outab(0xE8 + r);
 584               outab(0xD8);
 585
 586               break;
 587             }
 588         }
 589
 590       aerr();
 591       break;
 592
 593       //////////////////////////////////////////////////////////////////////
 594
 595     case S_INH1:
 596       // singe byte op
 597       outab(op);
 598       break;
 599
 600       //////////////////////////////////////////////////////////////////////
 601
 602     case S_JP:
 603       if ((v1 = admode(CND)) != 0)
 604         {
 605           comma(1);
 606
 607           t1 = addr(&e1);
 608
 609           if(t1 == S_R16)
 610             {
 611               op = 0xC0;
 612
 613               // jp cc
 614               op |= GET_COND_FROM_MODE(v1);
 615
 616               aerr();
 617               break;
 618             }
 619           else if(t1 == S_USER)
 620             {
 621               outab(0xEB);
 622               outrw(&e1, 0); // jmp, reloc
 623               outab(0xC0 | GET_COND_FROM_MODE(v1));
 624               break;
 625             }
 626           else
 627             {
 628               aerr();
 629             }
 630         }
 631       else
 632         {
 633           t1 = addr(&e1);
 634
 635           if (t1 == S_USER)
 636             {
 637               outab(0x1A);
 638               outrw(&e1, 0); // jmp, reloc..
 639               break;
 640             }
 641           else if (IS_REG_INDIRECT(t1)) // also S_R16?
 642             {
 643               int r = GET_IND_REG(t1);
 644
 645               outab(0xE8 + r);
 646               outab(0xC0 | 0x8);
 647               break;
 648             }
 649         }
 650
 651       aerr();
 652       break;
 653
 654       //////////////////////////////////////////////////////////////////////
 655
 656     case S_JR:
 657     case S_DJNZ:
 658     case S_CALLR:
 659       if (rf == S_JR)
 660         {
 661           if((v1 = admode(CND)) != 0)
 662             {
 663               op = 0xC0 | GET_COND_FROM_MODE(v1);
 664
 665               comma(1);
 666             }
 667           else
 668             {
 669               op = 0xC8;
 670             }
 671         }
 672       else if(rf == S_CALLR)
 673         {
 674           t1 = addr(&e2);
 675
 676           op = 0x1D;
 677           outab(op);
 678
 679           e2.e_addr += 1;
 680
 681           // signed 16-bit pcrel
 682           outrw(&e2, R_PCR);
 683           break;
 684         }
 685       else if(rf == S_DJNZ)
 686         {
 687           op = 0x18;
 688         }
 689
 690       //expr(&e2, 0);
 691       t2 = addr(&e2);
 692
 693       if(rf == S_DJNZ)
 694         {
 695           // djnz bc, xxxx
 696           if(t2 == S_R16)
 697             {
 698               if(e2.e_addr != BC)
 699                 aerr();
 700
 701               op = 0x19;
 702
 703               comma(1);
 704
 705               expr(&e2, 0);
 706             }
 707         }
 708
 709       if (e2.e_mode != S_USER)
 710         rerr();
 711
 712       outab(op);
 713
 714       if (mchpcr(&e2))
 715         {
 716           v2 = (int) (e2.e_addr - dot.s_addr - 1);
 717
 718           // SDCC currently generates jr cc, xxxx calls that exceeds the pc rel limit, i.e. 132..
 719           if (pass == 2 && ((v2 < -128) || (v2 > 127)))
 720             aerr();
 721
 722           outab(v2);
 723           break;
 724         }
 725       else
 726         {
 727           outrb(&e2, R_PCR);
 728           break;
 729         }
 730
 731       aerr();
 732       break;
 733
 734       //////////////////////////////////////////////////////////////////////
 735
 736     case S_EX:
 737       t1 = addr(&e1);
 738       comma(1);
 739       t2 = addr(&e2);
 740
 741       v1 = (int) e1.e_addr;
 742       v2 = (int) e2.e_addr;
 743
 744       if (t1 == S_R16 && t2 == S_R16)
 745         {
 746           if ((v1 == DE) && (v2 == HL))
 747             {
 748               outab(0x08);
 749               break;
 750             }
 751           if ((v2 == DE) && (v1 == HL))
 752             {
 753               outab(0x08);
 754               break;
 755             }
 756
 757           if((v1 & 0xF) == AF && (v2 & 0xF) == AF)
 758             {
 759               // ex af, af'
 760               outab(0x09);
 761               break;
 762             }
 763
 764           aerr();
 765         }
 766
 767       if(IS_REG_INDIRECT(t1) && t2 == S_R16)
 768         {
 769           int r = GET_IND_REG(t1);
 770
 771           if(e1.e_addr == 0)
 772             {
 773               outab(0xE0 + r);
 774               outab(op + v2);
 775               break;
 776             }
 777           else
 778             {
 779               if(r == HL)
 780                 {
 781                   outab(0xF3);
 782                   outab(op + v2);
 783                   break;
 784                 }
 785               else
 786                 {
 787                   outab(0xF0 + (r - IX));
 788                   outab(e1.e_addr);
 789                   outab(op + v2);
 790                   break;
 791                 }
 792             }
 793         }
 794
 795       if(t1 == S_R16 && IS_REG_INDIRECT(t2))
 796         {
 797           int r = GET_IND_REG(t2);
 798
 799           if(e2.e_addr == 0)
 800             {
 801               outab(0xE0 + r);
 802               outab(op + v1);
 803               break;
 804             }
 805           else
 806             {
 807               if(r == HL)
 808                 {
 809                   outab(0xF3);
 810                   outab(op + v1);
 811                   break;
 812                 }
 813               else
 814                 {
 815                   outab(0xF0 + (r - IX));
 816                   outab(e2.e_addr);
 817                   outab(op + v1);
 818                   break;
 819                 }
 820             }
 821         }
 822
 823       aerr();
 824       break;
 825
 826       //////////////////////////////////////////////////////////////////////
 827
 828     case S_DEC:
 829     case S_INC:
 830       t1 = addr(&e1);
 831       v1 = (int) e1.e_addr;
 832
 833       if(IS_REG_INDIRECT(t1))
 834         {
 835           int r;
 836
 837           r = GET_IND_REG(t1);
 838
 839           if(e1.e_addr == 0)
 840             {
 841               outab(0xe0 + r);
 842               outab(op + 7);
 843               break;
 844             }
 845           else
 846             {
 847               if(r == HL)
 848                 {
 849                   outab(0xF3);
 850                   outab(op + 7);
 851                   break;
 852                 }
 853               else
 854                 {
 855                   outab(0xec + r);
 856                   outab(e1.e_addr);
 857                   outab(op + 7);
 858                   break;
 859                 }
 860             }
 861         }
 862
 863       if(t1 == S_R8)
 864         {
 865           outab(op + v1);
 866           break;
 867         }
 868
 869       if(t1 == S_R16)
 870         {
 871           outab(op + 0x10 + v1);
 872           break;
 873         }
 874
 875       if ((t1 == S_INDM))
 876         {
 877           if(IS_DIRECT_MEM(v1))
 878             {
 879               outab(op + 7);
 880               outab(v1 & 0xff);
 881               break;
 882             }
 883           else
 884             {
 885               outab(0xE3);
 886               outrw(&e1, 0); // reloc
 887               outab(op + 7);
 888               break;
 889             }
 890         }
 891
 892       aerr();
 893       break;
 894
 895       //////////////////////////////////////////////////////////////////////
 896
 897     case S_INCW:
 898     case S_DECW:
 899       t1 = addr(&e1);
 900       v1 = (int) e1.e_addr;
 901
 902       if ((t1 == S_INDM))
 903         {
 904           if((IS_DIRECT_MEM(v1)))
 905             {
 906               outab(op);
 907               outab(v1 & 0xff);
 908               break;
 909             }
 910           else
 911             {
 912               outab(0xE3);
 913               outrw(&e1, 0);
 914               outab(op);
 915               break;
 916             }
 917         }
 918       else if(IS_REG_INDIRECT(t1))
 919         {
 920           int r = GET_IND_REG(t1);
 921
 922           if(e1.e_addr == 0)
 923             {
 924               outab(0xe0 + r);
 925               outab(op);
 926               break;
 927             }
 928           else
 929             {
 930               if(r == HL) // HL+A
 931                 {
 932                   outab(0xf0 + 3);
 933                   outab(op);
 934                   break;
 935                 }
 936               else
 937                 {
 938                   outab(0xf0 + (r - IX));
 939                   outab(v1);
 940                   outab(op);
 941                   break;
 942                 }
 943             }
 944         }
 945
 946       aerr();
 947       break;
 948
 949       //////////////////////////////////////////////////////////////////////
 950
 951     case S_MUL:
 952     case S_DIV:
 953       t1 = addr(&e1);
 954       v1 = (int) e1.e_addr;
 955       comma(1);
 956       t2 = addr(&e2);
 957       v2 = (int) e2.e_addr;
 958
 959       if(t1 == S_R16 && t2 == S_R8)
 960         {
 961           if(v1 != HL)
 962             aerr();
 963
 964           outab(0xF8 + v2);
 965           outab(op);
 966           break;
 967         }
 968
 969       if(t1 == S_R16 && t2 == S_INDM)
 970         {
 971           if(v1 == HL && (IS_DIRECT_MEM(v2)))
 972             {
 973               outab(0xE7);
 974               outab(v2 & 0xFF);
 975               outab(op);
 976               break;
 977             }
 978
 979           aerr();
 980         }
 981
 982       if(t1 == S_R16 && t2 == S_IMMED)
 983         {
 984           if(v1 == HL && (IS_8BIT_IMMED(v2)))
 985             {
 986               outab(op);
 987               outab(v2);
 988               break;
 989             }
 990
 991           aerr();
 992         }
 993
 994       if(t1 == S_R16 && IS_REG_INDIRECT(t2))
 995         {
 996           int r = GET_IND_REG(t2);
 997
 998           if(v1 == HL)
 999             {
1000               if(e2.e_addr == 0)
1001                 {
1002                   outab(0xE0 | r);
1003                   outab(op);
1004                 }
1005               else
1006                 {
1007                   if(r == HL) // HL+A
1008                     {
1009                       outab(0xF3);
1010                       outab(op);
1011                     }
1012                   else
1013                     {
1014                       outab(0xF0 + (r - IX));
1015                       outab(e2.e_addr & 0xFF);
1016                       outab(op);
1017                     }
1018                 }
1019               break;
1020             }
1021         }
1022
1023       aerr();
1024       break;
1025
1026       //////////////////////////////////////////////////////////////////////
1027
1028     case S_BIT:
1029     case S_RES:
1030     case S_SET:
1031     case S_TSET:
1032       t1 = addr(&e1);
1033       v1 = (int) e1.e_addr;
1034       comma(1);
1035       t2 = addr(&e2);
1036       v2 = (int) e2.e_addr;
1037
1038       if(t1 == S_USER && t2 == S_R8)
1039         {
1040           outab(0xF8 + v2);
1041           outab(op + v1);
1042           break;
1043         }
1044
1045       if ((t1 == S_USER && t2 == S_INDM))
1046         {
1047           if(v1 < 0 || v1 > 7)
1048             aerr();
1049
1050           if((IS_DIRECT_MEM(v2)))
1051             {
1052               outab(op + v1);
1053               outab(v2 & 0xff);
1054               break;
1055             }
1056           else
1057             {
1058               outab(0xe3);
1059               outrw(&e2, 0);
1060               outab(op + v1);
1061               outab(v2 & 0xff);
1062               break;
1063             }
1064         }
1065
1066       if ((t1 == S_USER && IS_REG_INDIRECT(t2)))
1067         {
1068           int r = GET_IND_REG(t2);
1069
1070           if(v1 < 0 || v1 > 7)
1071             aerr();
1072
1073           if(e2.e_addr == 0)
1074             {
1075               outab(0xe0 + r);
1076               outab(op + v1);
1077               break;
1078             }
1079           else
1080             {
1081               if(r == HL) // HL+A
1082                 {
1083                   outab(0xf3);
1084                   outab(op + v1);
1085                   break;
1086                 }
1087
1088               if(r == IX)
1089                 outab(0xF0);
1090               else if(r == IY)
1091                 outab(0xF1);
1092               else if(r == SP)
1093                 outab(0xF2);
1094               else
1095                 aerr();
1096
1097               outab(e2.e_addr & 0xFF);
1098               outab(op + v1);
1099               break;
1100             }
1101         }
1102
1103       aerr();
1104       break;
1105
1106       //////////////////////////////////////////////////////////////////////
1107
1108     case S_CP:
1109     case S_OR:
1110     case S_XOR:
1111     case S_AND:
1112     case S_ADD:
1113     case S_ADC:
1114     case S_SUB:
1115     case S_SBC:
1116       t1 = addr(&e1);
1117       v1 = (int) e1.e_addr;
1118       comma(1);
1119       t2 = addr(&e2);
1120       v2 = (int) e2.e_addr;
1121
1122       // add r8, r8
1123       if(t1 == S_R8 && t2 == S_R8)
1124         {
1125           gen_xop_arith(rf, op, t1, t2, v1, v2, &e1, &e2);
1126           break;
1127         }
1128
1129       // add (mm), imd
1130       if(t1 == S_INDM && t2 == S_IMMED)
1131         {
1132           gen_xop_arith(rf, op + 0x8, t1, t2, v1, v2, &e1, &e2);
1133           break;
1134         }
1135
1136       // add r, (mm)
1137       if(t1 == S_R8 && t2 == S_INDM)
1138         {
1139           if(v1 == A)
1140             {
1141               if(IS_DIRECT_MEM(v2))
1142                 {
1143                   outab(op);
1144                   outab(v2 & 0xff);
1145                   break;
1146                 }
1147               else
1148                 {
1149                   gen_xop_arith(rf, op, t1, t2, v1, v2, &e1, &e2);
1150                   break;
1151                 }
1152             }
1153           else
1154             {
1155               // only a allowed!?
1156               aerr();
1157             }
1158         }
1159
1160       // add r, (rr)
1161       if(t1 == S_R8 && IS_REG_INDIRECT(t2))
1162         {
1163           int r = GET_IND_REG(t2);
1164
1165           if(v1 != A)
1166             {
1167               aerr();
1168               break;
1169             }
1170
1171           if(e2.e_addr == 0)
1172             {
1173               outab(0xE0 + r);
1174               outab((op - 6) + v1);
1175               break;
1176             }
1177           else
1178             {
1179               if(r == HL) // HL+A
1180                 {
1181                   outab(0xF3);
1182                   outab(op);
1183                   break;
1184                 }
1185
1186               outab(0xEC + r);
1187               outab(e2.e_addr & 0xFF);
1188               outab((op - 6) + v1);
1189               break;
1190             }
1191         }
1192
1193       // add rr, (rr)
1194       if(t1 == S_R16 && IS_REG_INDIRECT(t2))
1195         {
1196           // not allowed
1197           if(v1 == BC || v1 == DE)
1198             {
1199               aerr();
1200               break;
1201             }
1202
1203           if(rf != S_ADD && v1 != HL)
1204             {
1205               aerr();
1206               break;
1207             }
1208
1209           if(v1 == HL)
1210             gen_xop_arith(rf, op + 0x10, t1, t2, v1, v2, &e1, &e2);
1211           else
1212             gen_xop_arith(rf, 0x10, t1, t2, v1, v2, &e1, &e2);
1213
1214           break;
1215         }
1216
1217       // add (rr), r
1218       if(IS_REG_INDIRECT(t1) && t2 == S_R8)
1219         {
1220           gen_xop_arith(rf, op, t1, t2, v1, v2, &e1, &e2);
1221           break;
1222         }
1223
1224       // add (rr), imd
1225       if(IS_REG_INDIRECT(t1) && t2 == S_IMMED)
1226         {
1227           gen_xop_arith(rf, op + 0x8, t1, t2, v1, v2, &e1, &e2);
1228           break;
1229         }
1230
1231       // add r, imm
1232       if(t1 == S_R8 && t2 == S_IMMED)
1233         {
1234           if((v1 == A) && (IS_8BIT_IMMED(v2)))
1235             {
1236               outab(op + 8);
1237               outrb(&e2,0);
1238               break;
1239             }
1240           else
1241             {
1242               gen_xop_arith(rf, op + 8, t1, t2, v1, v2, &e1, &e2);
1243               break;
1244             }
1245         }
1246
1247       // add rr, (mm)
1248       if(t1 == S_R16 && t2 == S_INDM)
1249         {
1250           // bc, de not allowed..
1251           if(v1 == BC || v1 == DE)
1252             aerr();
1253
1254           if(v1 == HL)
1255             {
1256               if(IS_DIRECT_MEM(v2))
1257                 {
1258                   outab(op + 0x10);
1259                   outab(v2 & 0xff);
1260                   break;
1261                 }
1262               else
1263                 {
1264                   gen_xop_arith(rf, op + 0x10, t1, t2, v1, v2, &e1, &e2);
1265                   break;
1266                 }
1267             }
1268           else
1269             {
1270               gen_xop_arith(rf, 0x10, t1, t2, v1, v2, &e1, &e2);
1271               break;
1272             }
1273         }
1274
1275       // add rr, rr
1276       if(t1 == S_R16 && t2 == S_R16)
1277         {
1278           gen_xop_arith(rf, op, t1, t2, v1, v2, &e1, &e2);
1279           break;
1280         }
1281
1282       // add rr, imd
1283       if(t1 == S_R16 && t2 == S_IMMED)
1284         {
1285           // sub not allowed on sp, ix, iy
1286           // de, bc not allowed at all!?
1287
1288           if(v1 == IX)
1289             {
1290               if(rf == S_ADD)
1291                 {
1292                   outab(0x14);
1293                   outrw(&e2, 0);
1294                   break;
1295                 }
1296               aerr();
1297             }
1298           else if(v1 == IY)
1299             {
1300               if(rf == S_ADD)
1301                 {
1302                   outab(0x15);
1303                   outrw(&e2, 0);
1304                   break;
1305                 }
1306               aerr();
1307             }
1308           else if(v1 == SP)
1309             {
1310               if(rf == S_ADD)
1311                 {
1312                   outab(0x16);
1313                   outrw(&e2, 0);
1314                   break;
1315                 }
1316               aerr();
1317             }
1318           else
1319             {
1320               // only hl allowed?
1321               if(v1 != HL)
1322                 aerr();
1323
1324               outab(op + 0x16 + v1);
1325               outrw(&e2, 0);
1326               break;
1327             }
1328         }
1329
1330       aerr();
1331       break;
1332
1333       //////////////////////////////////////////////////////////////////////
1334
1335     case S_RLC:
1336     case S_RRC:
1337     case S_RL:
1338     case S_RR:
1339     case S_SLA:
1340     case S_SRA:
1341     case S_SLL:
1342     case S_SRL:
1343       t1 = addr(&e1);
1344       v1 = (int) e1.e_addr;
1345       // can have a as first op or not..
1346       if(more())
1347         {
1348           if(t1 == S_R8 && v1 == A)
1349             {
1350               clrexpr(&e1);
1351
1352               comma(1);
1353
1354               t1 = addr(&e1);
1355               v1 = (int) e1.e_addr;
1356             }
1357           else
1358             {
1359               aerr();
1360               break;
1361             }
1362         }
1363
1364       if(IS_DIRECT_MEM(v1) && v1 > 0)
1365         {
1366           outab(0xE7);
1367           outab(v1 & 0xFF);
1368           outab(0xA0 + (rf - S_RLC));
1369           break;
1370         }
1371
1372       if(IS_REG_INDIRECT(t1))
1373         {
1374           int r = GET_IND_REG(t1);
1375
1376           if(v1 == 0)
1377             {
1378               outab(0xE0 + r);
1379               outab(0xA0 + (rf - S_RLC));
1380               break;
1381             }
1382           else
1383             {
1384               if(r == HL) // HL+A
1385                 {
1386                   outab(0xF3);
1387                   outab(0xA0 + (rf - S_RLC));
1388                   break;
1389                 }
1390
1391               outab(0xF0 + (r - IX));
1392               outab(v1 & 0xFF);
1393               outab(0xA0 + (rf - S_RLC));
1394               break;
1395             }
1396         }
1397
1398       if(t1 == S_R8)
1399         {
1400 #if 0
1401           // TODO: not used by asl assembler..
1402           if(v1 == A)
1403             {
1404               outab(0xA0 + (rf - S_RLC));
1405               break;
1406             }
1407           else
1408 #endif
1409             {
1410               outab(0xF8 + v1);
1411               outab(0xA0 + (rf - S_RLC));
1412               break;
1413             }
1414         }
1415
1416       aerr();
1417       break;
1418
1419       //////////////////////////////////////////////////////////////////////
1420
1421     case S_LDI:
1422       outab(0xFE);
1423       outab(0x58);
1424       break;
1425
1426     case S_LDIR:
1427       outab(0xFE);
1428       outab(0x59);
1429       break;
1430
1431     case S_LDD:
1432       outab(0xFE);
1433       outab(0x5A);
1434       break;
1435
1436     case S_LDDR:
1437       outab(0xFE);
1438       outab(0x5B);
1439       break;
1440
1441     case S_CPI:
1442       outab(0xFE);
1443       outab(0x5C);
1444       break;
1445
1446     case S_CPIR:
1447       outab(0xFE);
1448       outab(0x5D);
1449       break;
1450
1451     case S_CPD:
1452       outab(0xFE);
1453       outab(0x5E);
1454       break;
1455
1456     case S_CPDR:
1457       outab(0xFE);
1458       outab(0x5F);
1459       break;
1460
1461       //////////////////////////////////////////////////////////////////////
1462
1463     case S_LDAR:
1464       // load relative
1465       t1 = addr(&e1);
1466       v1 = (int) e1.e_addr;
1467       comma(1);
1468       t2 = addr(&e2);
1469       v2 = (int) e2.e_addr;
1470
1471       if(t1 == S_R16 && t2 == S_USER)
1472         {
1473           if(v1 == HL)
1474             {
1475               outab(op);
1476
1477               e2.e_addr += 1;
1478
1479               // signed 16-bit pcrel
1480               outrw(&e2, R_PCR);
1481
1482               break;
1483             }
1484         }
1485
1486       aerr();
1487       break;
1488
1489       //////////////////////////////////////////////////////////////////////
1490
1491     case S_LDW:
1492       t1 = addr(&e1);
1493       v1 = (int) e1.e_addr;
1494       comma(1);
1495       t2 = addr(&e2);
1496       v2 = (int) e2.e_addr;
1497
1498       if(t1 == S_INDM && t2 == S_IMMED)
1499         {
1500           if(IS_DIRECT_MEM(v1))
1501             {
1502               outab(0x3F);
1503               outab(v1 & 0xff);
1504               outrw(&e2, 0);
1505               break;
1506             }
1507           else
1508             {
1509               outab(0xEB);
1510               outrw(&e2, 0); // addr
1511               outab(0x3F);
1512               outrw(&e2, 0); // immd
1513               break;
1514             }
1515
1516           aerr();
1517         }
1518
1519       if(IS_REG_INDIRECT(t1) && t2 == S_IMMED)
1520         {
1521           int r;
1522
1523           r = GET_IND_REG(t1);
1524
1525           if(e1.e_addr == 0)
1526             {
1527               outab(0xe8 + r);
1528               outab(0x3F);
1529               outrw(&e2, 0);
1530               break;
1531             }
1532           else
1533             {
1534               if(r == HL)
1535                 {
1536                   outab(0xF7);
1537                   outab(0x3F);
1538                   outrw(&e2, 0);
1539                   break;
1540                 }
1541
1542               outab(0xF0 + r);
1543               outab(e1.e_addr & 0xFF);
1544               outab(0x3F);
1545               outrw(&e2, 0);
1546               break;
1547             }
1548         }
1549
1550       aerr();
1551       break;
1552
1553       //////////////////////////////////////////////////////////////////////
1554
1555     case S_LD:
1556       t1 = addr(&e1);
1557       v1 = (int) e1.e_addr;
1558       comma(1);
1559       t2 = addr(&e2);
1560       v2 = (int) e2.e_addr;
1561
1562       if(t1 == S_R8 && t2 == S_R8)
1563         {
1564           if(v1 == A)
1565             {
1566               outab(0x20 + v2);
1567               break;
1568             }
1569           if(v2 == A)
1570             {
1571               outab(0x28 + v1);
1572               break;
1573             }
1574
1575           outab(0xF8 + v2);
1576           outab(0x30 + v1);
1577           break;
1578
1579           aerr();
1580         }
1581
1582       if(IS_REG_INDIRECT(t1) && t2 == S_R8)
1583         {
1584           int r;
1585
1586           r = GET_IND_REG(t1);
1587
1588           if(e1.e_addr == 0)
1589             {
1590               outab(0xe8 + r);
1591               outab(0x20 + v2);
1592               break;
1593             }
1594           else
1595             {
1596               if(r == IX)
1597                 outab(0xf4);
1598               else if(r == IY)
1599                 outab(0xf5);
1600               else if(r == SP)
1601                 outab(0xf6);
1602               else if(r == HL)
1603                 {
1604                   outab(0xf7); // HL+A
1605                   outab(0x20 + v2);
1606                   break;
1607                 }
1608               else
1609                 aerr();
1610
1611               outab(e1.e_addr);
1612               outab(0x20 + v2);
1613               break;
1614             }
1615         }
1616
1617       if(t1 == S_R8 && IS_REG_INDIRECT(t2))
1618         {
1619           int r;
1620
1621           r = GET_IND_REG(t2);
1622
1623           if(e2.e_addr == 0)
1624             {
1625               outab(0xe0 + r);
1626               outab(0x28 + v1);
1627             }
1628           else
1629             {
1630               if(r == IX)
1631                 outab(0xf0);
1632               else if(r == IY)
1633                 outab(0xf1);
1634               else if(r == SP)
1635                 outab(0xf2);
1636               else if(r == HL) // HL+A
1637                 {
1638                   outab(0xf3);
1639                   outab(0x28 + v1);
1640                   break;
1641                 }
1642               else
1643                 aerr();
1644
1645               outab(e2.e_addr);
1646               outab(0x28 + v1);
1647             }
1648
1649           break;
1650         }
1651
1652       if(IS_REG_INDIRECT(t1) && t2 == S_R16)
1653         {
1654           int r;
1655
1656           r = GET_IND_REG(t1);
1657
1658           if(e1.e_addr == 0)
1659             {
1660               outab(0xe8 + r);
1661               outab(0x40 + v2);
1662               break;
1663             }
1664           else
1665             {
1666               if(r == HL) // HL+A
1667                 {
1668                   outab(0xF7);
1669                   outab(0x40 + v2);
1670                   break;
1671                 }
1672
1673               outab(0xF0 + r);
1674               outab(e1.e_addr);
1675               outab(0x40 + v2);
1676               break;
1677             }
1678         }
1679
1680       if(IS_REG_INDIRECT(t1) && t2 == S_IMMED)
1681         {
1682           int r;
1683
1684           r = GET_IND_REG(t1);
1685
1686           if(e1.e_addr == 0)
1687             {
1688               outab(0xe8 + r);
1689               outab(0x37);
1690               outrb(&e2,0);
1691               break;
1692             }
1693           else
1694             {
1695               if(r == HL) // HL+A
1696                 {
1697                   outab(0xF7);
1698                   outab(0x37);
1699                   outrb(&e2,0);
1700                   break;
1701                 }
1702
1703               outab(0xF0 + r);
1704               outab(e1.e_addr);
1705               outab(0x37);
1706               outrb(&e2,0);
1707               break;
1708             }
1709         }
1710
1711       if(t1 == S_R16 && IS_REG_INDIRECT(t2))
1712         {
1713           int r;
1714
1715           r = GET_IND_REG(t2);
1716
1717           if(e2.e_addr == 0)
1718             {
1719               outab(0xe0 + r);
1720               outab(0x48 + v1);
1721             }
1722           else
1723             {
1724               if(r == IX)
1725                 outab(0xf0);
1726               else if(r == IY)
1727                 outab(0xf1);
1728               else if(r == SP)
1729                 outab(0xf2);
1730               else if(r == HL) // HL+A
1731                 {
1732                   outab(0xf3);
1733                   outab(0x48 + v1);
1734                   break;
1735                 }
1736               else
1737                 aerr();
1738
1739               outab(e2.e_addr);
1740               outab(0x48 + v1);
1741             }
1742
1743           break;
1744         }
1745
1746       if(t1 == S_R8 && t2 == S_IMMED)
1747         {
1748           outab(0x30 + v1);
1749           outrb(&e2,0);
1750           break;
1751         }
1752
1753       if(t1 == S_R8 && t2 == S_INDM)
1754         {
1755           if(IS_DIRECT_MEM(v2) && v1 == A)
1756             {
1757               outab(0x27);
1758               outab(v2 & 0xff);
1759               break;
1760             }
1761
1762           if(IS_DIRECT_MEM(v2))
1763             {
1764               outab(0xE7);
1765               outab(v2 & 0xff);
1766               outab(0x28 + v1);
1767               break;
1768             }
1769           else
1770             {
1771               // normal access
1772               outab(0xE3);
1773               outrw(&e2, 0); // reloc!?
1774               outab(0x28 + v1);
1775               break;
1776             }
1777
1778           aerr();
1779         }
1780
1781 #if 0
1782       // alternate encodings or disassmbler bug?
1783       if(t1 == S_R8 && t2 == S_INDM)
1784         {
1785           if(v1 == B)
1786             {
1787               outab(0xE3);
1788               outrw(&e2, 0);
1789               outab(0x28);
1790               break;
1791             }
1792           if(v1 == C)
1793             {
1794               outab(0xE3);
1795               outrw(&e2, 0);
1796               outab(0x29);
1797               break;
1798             }
1799           if(v1 == D)
1800             {
1801               outab(0xE3);
1802               outrw(&e2, 0);
1803               outab(0x2A);
1804               break;
1805             }
1806           if(v1 == A)
1807             {
1808               outab(0xE3);
1809               outrw(&e2, 0);
1810               outab(0x2E);
1811               break;
1812             }
1813         }
1814 #endif
1815
1816       if(t1 == S_R16 && t2 == S_R16)
1817         {
1818           if(v1 == HL)
1819             {
1820               outab(0x40 + v2);
1821               break;
1822             }
1823           if(v2 == HL)
1824             {
1825               outab(0x48 + v1);
1826               break;
1827             }
1828
1829           outab(0xF8 + v2);
1830           outab(0x38 + v1);
1831
1832           break;
1833         }
1834
1835       if(t1 == S_R16 && t2 == S_IMMED)
1836         {
1837           if(IS_16BIT_IMMED(v2))
1838             {
1839               outab(0x38 + v1);
1840               outrw(&e2, 0);
1841               break;
1842             }
1843         }
1844
1845       if(t1 == S_R16 && t2 == S_INDM)
1846         {
1847           if(IS_DIRECT_MEM(v2))
1848             {
1849               if(v1 == HL)
1850                 {
1851                   outab(0x47);
1852                   outab(v2 & 0xFF);
1853                   break;
1854                 }
1855               else
1856                 {
1857                   outab(0xE7);
1858                   outab(v2 & 0xFF);
1859                   outab(0x48 + v1);
1860                   break;
1861                 }
1862             }
1863           else
1864             {
1865               outab(0xE3);
1866               outrw(&e2, 0); // reloc!?
1867               outab(0x48 + v1);
1868               break;
1869             }
1870         }
1871
1872       if(t1 == S_INDM && t2 == S_R8)
1873         {
1874           if(IS_DIRECT_MEM(v1) && v2 == A)
1875             {
1876               outab(0x2F);
1877               outab(v1 & 0xff);
1878               break;
1879             }
1880           else if(IS_DIRECT_MEM(v1))
1881             {
1882               outab(0xEF);
1883               outab(v1 & 0xff);
1884               outab(0x20 + v2);
1885               break;
1886             }
1887           else
1888             {
1889               outab(0xEB);
1890               outrw(&e1, 0);
1891               outab(0x20 + v2);
1892               break;
1893             }
1894
1895           aerr();
1896         }
1897
1898       if(t1 == S_INDM && t2 == S_R16)
1899         {
1900           if(IS_DIRECT_MEM(v1))
1901             {
1902               if(v2 == HL)
1903                 {
1904                   outab(0x4F);
1905                   outab(v1 & 0xFF);
1906                   break;
1907                 }
1908               else
1909                 {
1910                   outab(0xEF);
1911                   outab(v1 & 0xFF);
1912                   outab(0x40 + v2);
1913                   break;
1914                 }
1915             }
1916           else
1917             {
1918               outab(0xEB);
1919               outrw(&e1, 0);
1920               outab(0x40 + v2);
1921               break;
1922             }
1923         }
1924       if(t1 == S_INDM && t2 == S_IMMED)
1925         {
1926           if(IS_DIRECT_MEM(v1))
1927             {
1928               outab(0x37);
1929               outab(v1 & 0xff);
1930               outab(v2 & 0xff);
1931               break;
1932             }
1933           else
1934             {
1935               outab(0xeb);
1936               outrw(&e1, 0);
1937               outab(0x37);
1938               outab(v2 & 0xff);
1939               break;
1940             }
1941
1942           aerr();
1943         }
1944
1945       aerr();
1946       break;
1947
1948       //////////////////////////////////////////////////////////////////////
1949
1950     case S_RLD:
1951     case S_RRD:
1952
1953       // implicit (hl) operand
1954       outab(0xE2);
1955       outab(op);
1956       break;
1957
1958       //////////////////////////////////////////////////////////////////////
1959
1960     case S_CPU:
1961       opcycles = OPCY_CPU;
1962       //mchtyp = op;
1963       sym[2].s_addr = op;
1964       lmode = SLIST;
1965       break;
1966
1967       //////////////////////////////////////////////////////////////////////
1968
1969     default:
1970       opcycles = OPCY_ERR;
1971       err('o');
1972       break;
1973     }
1974
1975   if (opcycles == OPCY_NONE)
1976     {
1977       opcycles = t90pg1[cb[0] & 0xFF];
1978       while ((opcycles & OPCY_NONE) && (opcycles & OPCY_MASK))
1979         {
1980           switch (opcycles) {
1981           case P2:        /* CB xx        */
1982           case P3:        /* DD xx        */
1983           case P4:        /* ED xx        */
1984           case P5:        /* FD xx        */
1985             opcycles = t90Page[opcycles & OPCY_MASK][cb[1] & 0xFF];
1986             break;
1987           case P6:        /* DD CB -- xx  */
1988           case P7:        /* FD CB -- xx  */
1989             opcycles = t90Page[opcycles & OPCY_MASK][cb[3] & 0xFF];
1990             break;
1991           default:
1992             opcycles = OPCY_NONE;
1993             break;
1994           }
1995         }
1996     }
1997 }
1998
1999 /*
2000  * Branch/Jump PCR Mode Check
2001  */
2002
2003 int
2004 mchpcr(struct expr *esp)
2005 {
2006   if (esp->e_base.e_ap == dot.s_area)
2007     {
2008       return(1);
2009     }
2010
2011   if (esp->e_flag==0 && esp->e_base.e_ap==NULL)
2012     {
2013       /*
2014        * Absolute Destination
2015        *
2016        * Use the global symbol '.__.ABS.'
2017        * of value zero and force the assembler
2018        * to use this absolute constant as the
2019        * base value for the relocation.
2020        */
2021       esp->e_flag = 1;
2022       esp->e_base.e_sp = &sym[1];
2023     }
2024
2025   return(0);
2026 }
2027
2028 /*
2029  * Machine dependent initialization
2030  */
2031
2032 VOID
2033 minit()
2034 {
2035   /*
2036    * Byte Order
2037    */
2038   hilo = 0;
2039
2040   if (pass == 0)
2041     {
2042       sym[2].s_addr = X_T90;
2043     }
2044 }