sdcc/support/cpp/gcc/insn-constants.h

   1 /* Generated automatically by the program `genconstants'
   2    from the machine description file `md'.  */
   3
   4 #ifndef GCC_INSN_CONSTANTS_H
   5 #define GCC_INSN_CONSTANTS_H
   6
   7 #define MM7_REG 35
   8 #define XMM27_REG 63
   9 #define ST6_REG 14
  10 #define R13_REG 41
  11 #define XMM14_REG 50
  12 #define XMM19_REG 55
  13 #define ARGP_REG 16
  14 #define PCOM_TRUE 1
  15 #define PPERM_ZERO 0x80
  16 #define XMM6_REG 26
  17 #define ST3_REG 11
  18 #define R10_REG 38
  19 #define XMM11_REG 47
  20 #define XMM24_REG 60
  21 #define DX_REG 1
  22 #define FLAGS_REG 17
  23 #define ST1_REG 9
  24 #define MM5_REG 33
  25 #define MASK7_REG 75
  26 #define PPERM_SRC 0x00
  27 #define MM4_REG 32
  28 #define ST7_REG 15
  29 #define COM_FALSE_P 3
  30 #define XMM3_REG 23
  31 #define ST0_REG 8
  32 #define COM_FALSE_S 2
  33 #define SP_REG 7
  34 #define AX_REG 0
  35 #define MM1_REG 29
  36 #define MM3_REG 31
  37 #define XMM1_REG 21
  38 #define MASK5_REG 73
  39 #define ROUND_ZERO 3
  40 #define PPERM_SRC1 0x00
  41 #define XMM16_REG 52
  42 #define PCOM_FALSE 0
  43 #define XMM8_REG 44
  44 #define XMM4_REG 24
  45 #define ST5_REG 13
  46 #define XMM29_REG 65
  47 #define XMM23_REG 59
  48 #define R12_REG 40
  49 #define R9_REG 37
  50 #define XMM20_REG 56
  51 #define ROUND_MXCSR 0x4
  52 #define MASK4_REG 72
  53 #define PPERM_INVERT 0x20
  54 #define MM6_REG 34
  55 #define XMM26_REG 62
  56 #define PPERM_SRC2 0x10
  57 #define ST2_REG 10
  58 #define MASK1_REG 69
  59 #define ABI_VZEROUPPER 1
  60 #define NO_ROUND 4
  61 #define XMM10_REG 46
  62 #define ROUND_TRUNC 0x3
  63 #define PPERM_SIGN 0xc0
  64 #define R8_REG 36
  65 #define XMM9_REG 45
  66 #define XMM18_REG 54
  67 #define MASK3_REG 71
  68 #define DI_REG 5
  69 #define XMM25_REG 61
  70 #define ABI_DEFAULT 0
  71 #define BP_REG 6
  72 #define ROUND_ROUNDEVEN 0x0
  73 #define XMM12_REG 48
  74 #define XMM5_REG 25
  75 #define COM_TRUE_S 4
  76 #define ROUND_FLOOR 0x1
  77 #define FPSR_REG 18
  78 #define MASK6_REG 74
  79 #define R14_REG 42
  80 #define XMM15_REG 51
  81 #define XMM28_REG 64
  82 #define R15_REG 43
  83 #define XMM13_REG 49
  84 #define ROUND_NEAREST_INT 0
  85 #define ROUND_CEIL 0x2
  86 #define MM0_REG 28
  87 #define XMM31_REG 67
  88 #define BX_REG 3
  89 #define XMM7_REG 27
  90 #define XMM30_REG 66
  91 #define ST4_REG 12
  92 #define PPERM_INV_SIGN 0xe0
  93 #define R11_REG 39
  94 #define FIRST_PSEUDO_REG 76
  95 #define PPERM_REVERSE 0x40
  96 #define CX_REG 2
  97 #define ABI_UNKNOWN 2
  98 #define MASK0_REG 68
  99 #define COM_TRUE_P 5
 100 #define SI_REG 4
 101 #define XMM22_REG 58
 102 #define XMM0_REG 20
 103 #define XMM17_REG 53
 104 #define ROUND_NEG_INF 1
 105 #define ROUND_POS_INF 2
 106 #define XMM2_REG 22
 107 #define FRAME_REG 19
 108 #define PPERM_ONES 0xa0
 109 #define XMM21_REG 57
 110 #define ROUND_NO_EXC 0x8
 111 #define MM2_REG 30
 112 #define ROUND_SAE 8
 113 #define MASK2_REG 70
 114 #define PPERM_REV_INV 0x60
 115
 116 enum unspec {
 117   UNSPEC_GOT = 0,
 118   UNSPEC_GOTOFF = 1,
 119   UNSPEC_GOTPCREL = 2,
 120   UNSPEC_GOTTPOFF = 3,
 121   UNSPEC_TPOFF = 4,
 122   UNSPEC_NTPOFF = 5,
 123   UNSPEC_DTPOFF = 6,
 124   UNSPEC_GOTNTPOFF = 7,
 125   UNSPEC_INDNTPOFF = 8,
 126   UNSPEC_PLTOFF = 9,
 127   UNSPEC_MACHOPIC_OFFSET = 10,
 128   UNSPEC_PCREL = 11,
 129   UNSPEC_SIZEOF = 12,
 130   UNSPEC_STACK_ALLOC = 13,
 131   UNSPEC_SET_GOT = 14,
 132   UNSPEC_SET_RIP = 15,
 133   UNSPEC_SET_GOT_OFFSET = 16,
 134   UNSPEC_MEMORY_BLOCKAGE = 17,
 135   UNSPEC_PROBE_STACK = 18,
 136   UNSPEC_TP = 19,
 137   UNSPEC_TLS_GD = 20,
 138   UNSPEC_TLS_LD_BASE = 21,
 139   UNSPEC_TLSDESC = 22,
 140   UNSPEC_TLS_IE_SUN = 23,
 141   UNSPEC_SCAS = 24,
 142   UNSPEC_FNSTSW = 25,
 143   UNSPEC_SAHF = 26,
 144   UNSPEC_NOTRAP = 27,
 145   UNSPEC_PARITY = 28,
 146   UNSPEC_FSTCW = 29,
 147   UNSPEC_REP = 30,
 148   UNSPEC_LD_MPIC = 31,
 149   UNSPEC_TRUNC_NOOP = 32,
 150   UNSPEC_DIV_ALREADY_SPLIT = 33,
 151   UNSPEC_PAUSE = 34,
 152   UNSPEC_LEA_ADDR = 35,
 153   UNSPEC_XBEGIN_ABORT = 36,
 154   UNSPEC_STOS = 37,
 155   UNSPEC_PEEPSIB = 38,
 156   UNSPEC_INSN_FALSE_DEP = 39,
 157   UNSPEC_SBB = 40,
 158   UNSPEC_FIX_NOTRUNC = 41,
 159   UNSPEC_MASKMOV = 42,
 160   UNSPEC_MOVCC_MASK = 43,
 161   UNSPEC_MOVMSK = 44,
 162   UNSPEC_BLENDV = 45,
 163   UNSPEC_PSHUFB = 46,
 164   UNSPEC_XOP_PERMUTE = 47,
 165   UNSPEC_RCP = 48,
 166   UNSPEC_RSQRT = 49,
 167   UNSPEC_PSADBW = 50,
 168   UNSPEC_SCALEF = 51,
 169   UNSPEC_PCMP = 52,
 170   UNSPEC_IEEE_MIN = 53,
 171   UNSPEC_IEEE_MAX = 54,
 172   UNSPEC_SIN = 55,
 173   UNSPEC_COS = 56,
 174   UNSPEC_FPATAN = 57,
 175   UNSPEC_FYL2X = 58,
 176   UNSPEC_FYL2XP1 = 59,
 177   UNSPEC_FRNDINT = 60,
 178   UNSPEC_FIST = 61,
 179   UNSPEC_F2XM1 = 62,
 180   UNSPEC_TAN = 63,
 181   UNSPEC_FXAM = 64,
 182   UNSPEC_FRNDINT_ROUNDEVEN = 65,
 183   UNSPEC_FRNDINT_FLOOR = 66,
 184   UNSPEC_FRNDINT_CEIL = 67,
 185   UNSPEC_FRNDINT_TRUNC = 68,
 186   UNSPEC_FIST_FLOOR = 69,
 187   UNSPEC_FIST_CEIL = 70,
 188   UNSPEC_SINCOS_COS = 71,
 189   UNSPEC_SINCOS_SIN = 72,
 190   UNSPEC_XTRACT_FRACT = 73,
 191   UNSPEC_XTRACT_EXP = 74,
 192   UNSPEC_FSCALE_FRACT = 75,
 193   UNSPEC_FSCALE_EXP = 76,
 194   UNSPEC_FPREM_F = 77,
 195   UNSPEC_FPREM_U = 78,
 196   UNSPEC_FPREM1_F = 79,
 197   UNSPEC_FPREM1_U = 80,
 198   UNSPEC_C2_FLAG = 81,
 199   UNSPEC_FXAM_MEM = 82,
 200   UNSPEC_SP_SET = 83,
 201   UNSPEC_SP_TEST = 84,
 202   UNSPEC_ROUND = 85,
 203   UNSPEC_CRC32 = 86,
 204   UNSPEC_LZCNT = 87,
 205   UNSPEC_TZCNT = 88,
 206   UNSPEC_BEXTR = 89,
 207   UNSPEC_PDEP = 90,
 208   UNSPEC_PEXT = 91,
 209   UNSPEC_INTERRUPT_RETURN = 92,
 210   UNSPEC_MOVDIRI = 93,
 211   UNSPEC_MOVDIR64B = 94,
 212   UNSPEC_CALLEE_ABI = 95
 213 };
 214 #define NUM_UNSPEC_VALUES 96
 215 extern const char *const unspec_strings[];
 216
 217 enum unspecv {
 218   UNSPECV_UD2 = 0,
 219   UNSPECV_BLOCKAGE = 1,
 220   UNSPECV_STACK_PROBE = 2,
 221   UNSPECV_PROBE_STACK_RANGE = 3,
 222   UNSPECV_ALIGN = 4,
 223   UNSPECV_PROLOGUE_USE = 5,
 224   UNSPECV_SPLIT_STACK_RETURN = 6,
 225   UNSPECV_CLD = 7,
 226   UNSPECV_NOPS = 8,
 227   UNSPECV_RDTSC = 9,
 228   UNSPECV_RDTSCP = 10,
 229   UNSPECV_RDPMC = 11,
 230   UNSPECV_LLWP_INTRINSIC = 12,
 231   UNSPECV_SLWP_INTRINSIC = 13,
 232   UNSPECV_LWPVAL_INTRINSIC = 14,
 233   UNSPECV_LWPINS_INTRINSIC = 15,
 234   UNSPECV_RDFSBASE = 16,
 235   UNSPECV_RDGSBASE = 17,
 236   UNSPECV_WRFSBASE = 18,
 237   UNSPECV_WRGSBASE = 19,
 238   UNSPECV_FXSAVE = 20,
 239   UNSPECV_FXRSTOR = 21,
 240   UNSPECV_FXSAVE64 = 22,
 241   UNSPECV_FXRSTOR64 = 23,
 242   UNSPECV_XSAVE = 24,
 243   UNSPECV_XRSTOR = 25,
 244   UNSPECV_XSAVE64 = 26,
 245   UNSPECV_XRSTOR64 = 27,
 246   UNSPECV_XSAVEOPT = 28,
 247   UNSPECV_XSAVEOPT64 = 29,
 248   UNSPECV_XSAVES = 30,
 249   UNSPECV_XRSTORS = 31,
 250   UNSPECV_XSAVES64 = 32,
 251   UNSPECV_XRSTORS64 = 33,
 252   UNSPECV_XSAVEC = 34,
 253   UNSPECV_XSAVEC64 = 35,
 254   UNSPECV_XGETBV = 36,
 255   UNSPECV_XSETBV = 37,
 256   UNSPECV_WBINVD = 38,
 257   UNSPECV_WBNOINVD = 39,
 258   UNSPECV_FNSTENV = 40,
 259   UNSPECV_FLDENV = 41,
 260   UNSPECV_FNSTSW = 42,
 261   UNSPECV_FNCLEX = 43,
 262   UNSPECV_RDRAND = 44,
 263   UNSPECV_RDSEED = 45,
 264   UNSPECV_XBEGIN = 46,
 265   UNSPECV_XEND = 47,
 266   UNSPECV_XABORT = 48,
 267   UNSPECV_XTEST = 49,
 268   UNSPECV_NLGR = 50,
 269   UNSPECV_CLWB = 51,
 270   UNSPECV_CLFLUSHOPT = 52,
 271   UNSPECV_MONITORX = 53,
 272   UNSPECV_MWAITX = 54,
 273   UNSPECV_CLZERO = 55,
 274   UNSPECV_PKU = 56,
 275   UNSPECV_RDPID = 57,
 276   UNSPECV_NOP_ENDBR = 58,
 277   UNSPECV_NOP_RDSSP = 59,
 278   UNSPECV_INCSSP = 60,
 279   UNSPECV_SAVEPREVSSP = 61,
 280   UNSPECV_RSTORSSP = 62,
 281   UNSPECV_WRSS = 63,
 282   UNSPECV_WRUSS = 64,
 283   UNSPECV_SETSSBSY = 65,
 284   UNSPECV_CLRSSBSY = 66,
 285   UNSPECV_XSUSLDTRK = 67,
 286   UNSPECV_XRESLDTRK = 68,
 287   UNSPECV_UMWAIT = 69,
 288   UNSPECV_UMONITOR = 70,
 289   UNSPECV_TPAUSE = 71,
 290   UNSPECV_CLUI = 72,
 291   UNSPECV_STUI = 73,
 292   UNSPECV_TESTUI = 74,
 293   UNSPECV_SENDUIPI = 75,
 294   UNSPECV_CLDEMOTE = 76,
 295   UNSPECV_SPECULATION_BARRIER = 77,
 296   UNSPECV_PTWRITE = 78,
 297   UNSPECV_ENQCMD = 79,
 298   UNSPECV_ENQCMDS = 80,
 299   UNSPECV_SERIALIZE = 81,
 300   UNSPECV_PATCHABLE_AREA = 82,
 301   UNSPECV_HRESET = 83
 302 };
 303 #define NUM_UNSPECV_VALUES 84
 304 extern const char *const unspecv_strings[];
 305
 306 #endif /* GCC_INSN_CONSTANTS_H */