sdcc/support/sdbinutils/include/opcode/i370.h

   1 /* i370.h -- Header file for S/390 opcode table
   2    Copyright (C) 1994-2018 Free Software Foundation, Inc.
   3    PowerPC version written by Ian Lance Taylor, Cygnus Support
   4    Rewritten for i370 ESA/390 support, Linas Vepstas <linas@linas.org>
   5
   6    This file is part of GDB, GAS, and the GNU binutils.
   7
   8    GDB, GAS, and the GNU binutils are free software; you can redistribute
   9    them and/or modify them under the terms of the GNU General Public
  10    License as published by the Free Software Foundation; either version 3,
  11    or (at your option) any later version.
  12
  13    GDB, GAS, and the GNU binutils are distributed in the hope that they
  14    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  15    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  16    the GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this file; see the file COPYING3.  If not, write to the Free
  20    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  21    MA 02110-1301, USA.  */
  22
  23 #ifndef I370_H
  24 #define I370_H
  25
  26 /* The opcode table is an array of struct i370_opcode.  */
  27 typedef union
  28 {
  29    unsigned int   i[2];
  30    unsigned short s[4];
  31    unsigned char  b[8];
  32 }  i370_insn_t;
  33
  34 struct i370_opcode
  35 {
  36   /* The opcode name.  */
  37   const char *name;
  38
  39   /* the length of the instruction */
  40   char len;
  41
  42   /* The opcode itself.  Those bits which will be filled in with
  43      operands are zeroes.  */
  44   i370_insn_t opcode;
  45
  46   /* The opcode mask.  This is used by the disassembler.  This is a
  47      mask containing ones indicating those bits which must match the
  48      opcode field, and zeroes indicating those bits which need not
  49      match (and are presumably filled in by operands).  */
  50   i370_insn_t mask;
  51
  52   /* One bit flags for the opcode.  These are used to indicate which
  53      specific processors support the instructions.  The defined values
  54      are listed below.  */
  55   unsigned long flags;
  56
  57   /* An array of operand codes.  Each code is an index into the
  58      operand table.  They appear in the order which the operands must
  59      appear in assembly code, and are terminated by a zero.  */
  60   unsigned char operands[8];
  61 };
  62
  63 /* The table itself is sorted by major opcode number, and is otherwise
  64    in the order in which the disassembler should consider
  65    instructions.  */
  66 extern const struct i370_opcode i370_opcodes[];
  67 extern const int i370_num_opcodes;
  68
  69 /* Values defined for the flags field of a struct i370_opcode.  */
  70
  71 /* Opcode is defined for the original 360 architecture.  */
  72 #define I370_OPCODE_360 (0x01)
  73
  74 /* Opcode is defined for the 370 architecture.  */
  75 #define I370_OPCODE_370 (0x02)
  76
  77 /* Opcode is defined for the 370-XA architecture.  */
  78 #define I370_OPCODE_370_XA (0x04)
  79
  80 /* Opcode is defined for the ESA/370 architecture.  */
  81 #define I370_OPCODE_ESA370 (0x08)
  82
  83 /* Opcode is defined for the ESA/390 architecture.  */
  84 #define I370_OPCODE_ESA390 (0x10)
  85
  86 /* Opcode is defined for the ESA/390 w/ BFP facility.  */
  87 #define I370_OPCODE_ESA390_BF (0x20)
  88
  89 /* Opcode is defined for the ESA/390 w/ branch & set authority facility.  */
  90 #define I370_OPCODE_ESA390_BS (0x40)
  91
  92 /* Opcode is defined for the ESA/390 w/ checksum facility.  */
  93 #define I370_OPCODE_ESA390_CK (0x80)
  94
  95 /* Opcode is defined for the ESA/390 w/ compare & move extended facility.  */
  96 #define I370_OPCODE_ESA390_CM (0x100)
  97
  98 /* Opcode is defined for the ESA/390 w/ flt.pt. support extensions facility. */
  99 #define I370_OPCODE_ESA390_FX (0x200)
 100
 101 /* Opcode is defined for the ESA/390 w/ HFP facility. */
 102 #define I370_OPCODE_ESA390_HX (0x400)
 103
 104 /* Opcode is defined for the ESA/390 w/ immediate & relative facility.  */
 105 #define I370_OPCODE_ESA390_IR (0x800)
 106
 107 /* Opcode is defined for the ESA/390 w/ move-inverse facility.  */
 108 #define I370_OPCODE_ESA390_MI (0x1000)
 109
 110 /* Opcode is defined for the ESA/390 w/ program-call-fast facility.  */
 111 #define I370_OPCODE_ESA390_PC (0x2000)
 112
 113 /* Opcode is defined for the ESA/390 w/ perform-locked-op facility.  */
 114 #define I370_OPCODE_ESA390_PL (0x4000)
 115
 116 /* Opcode is defined for the ESA/390 w/ square-root facility.  */
 117 #define I370_OPCODE_ESA390_QR (0x8000)
 118
 119 /* Opcode is defined for the ESA/390 w/ resume-program facility.  */
 120 #define I370_OPCODE_ESA390_RP (0x10000)
 121
 122 /* Opcode is defined for the ESA/390 w/ set-address-space-fast facility.  */
 123 #define I370_OPCODE_ESA390_SA (0x20000)
 124
 125 /* Opcode is defined for the ESA/390 w/ subspace group facility.  */
 126 #define I370_OPCODE_ESA390_SG (0x40000)
 127
 128 /* Opcode is defined for the ESA/390 w/ string facility.  */
 129 #define I370_OPCODE_ESA390_SR (0x80000)
 130
 131 /* Opcode is defined for the ESA/390 w/ trap facility.  */
 132 #define I370_OPCODE_ESA390_TR (0x100000)
 133
 134 #define I370_OPCODE_ESA390_SUPERSET (0x1fffff)
 135
 136 \f
 137 /* The operands table is an array of struct i370_operand.  */
 138
 139 struct i370_operand
 140 {
 141   /* The number of bits in the operand.  */
 142   int bits;
 143
 144   /* How far the operand is left shifted in the instruction.  */
 145   int shift;
 146
 147   /* Insertion function.  This is used by the assembler.  To insert an
 148      operand value into an instruction, check this field.
 149
 150      If it is NULL, execute
 151          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 152      (i is the instruction which we are filling in, o is a pointer to
 153      this structure, and op is the opcode value; this assumes twos
 154      complement arithmetic).
 155
 156      If this field is not NULL, then simply call it with the
 157      instruction and the operand value.  It will return the new value
 158      of the instruction.  If the ERRMSG argument is not NULL, then if
 159      the operand value is illegal, *ERRMSG will be set to a warning
 160      string (the operand will be inserted in any case).  If the
 161      operand value is legal, *ERRMSG will be unchanged (most operands
 162      can accept any value).  */
 163   i370_insn_t (*insert)
 164     (i370_insn_t instruction, long op, const char **errmsg);
 165
 166   /* Extraction function.  This is used by the disassembler.  To
 167      extract this operand type from an instruction, check this field.
 168
 169      If it is NULL, compute
 170          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 171          if ((o->flags & I370_OPERAND_SIGNED) != 0
 172            && (op & (1 << (o->bits - 1))) != 0)
 173            op -= 1 << o->bits;
 174      (i is the instruction, o is a pointer to this structure, and op
 175      is the result; this assumes twos complement arithmetic).
 176
 177      If this field is not NULL, then simply call it with the
 178      instruction value.  It will return the value of the operand.  If
 179      the INVALID argument is not NULL, *INVALID will be set to
 180      non-zero if this operand type can not actually be extracted from
 181      this operand (i.e., the instruction does not match).  If the
 182      operand is valid, *INVALID will not be changed.  */
 183   long (*extract) (i370_insn_t instruction, int *invalid);
 184
 185   /* One bit syntax flags.  */
 186   unsigned long flags;
 187
 188   /* name -- handy for debugging, otherwise pointless */
 189   char * name;
 190 };
 191
 192 /* Elements in the table are retrieved by indexing with values from
 193    the operands field of the i370_opcodes table.  */
 194
 195 extern const struct i370_operand i370_operands[];
 196
 197 /* Values defined for the flags field of a struct i370_operand.  */
 198
 199 /* This operand should be wrapped in parentheses rather than
 200    separated from the previous by a comma.  This is used for S, RS and
 201    SS form instructions which want their operands to look like
 202    reg,displacement(basereg) */
 203 #define I370_OPERAND_SBASE (0x01)
 204
 205 /* This operand is a base register.  It may or may not appear next
 206    to an index register, i.e. either of the two forms
 207    reg,displacement(basereg)
 208    reg,displacement(index,basereg) */
 209 #define I370_OPERAND_BASE (0x02)
 210
 211 /* This pair of operands should be wrapped in parentheses rather than
 212    separated from the last by a comma.  This is used for the RX form
 213    instructions which want their operands to look like
 214    reg,displacement(index,basereg) */
 215 #define I370_OPERAND_INDEX (0x04)
 216
 217 /* This operand names a register.  The disassembler uses this to print
 218    register names with a leading 'r'.  */
 219 #define I370_OPERAND_GPR (0x08)
 220
 221 /* This operand names a floating point register.  The disassembler
 222    prints these with a leading 'f'.  */
 223 #define I370_OPERAND_FPR (0x10)
 224
 225 /* This operand is a displacement.  */
 226 #define I370_OPERAND_RELATIVE (0x20)
 227
 228 /* This operand is a length, such as that in SS form instructions.  */
 229 #define I370_OPERAND_LENGTH (0x40)
 230
 231 /* This operand is optional, and is zero if omitted.  This is used for
 232    the optional B2 field in the shift-left, shift-right instructions.  The
 233    assembler must count the number of operands remaining on the line,
 234    and the number of operands remaining for the opcode, and decide
 235    whether this operand is present or not.  The disassembler should
 236    print this operand out only if it is not zero.  */
 237 #define I370_OPERAND_OPTIONAL (0x80)
 238
 239 \f
 240 /* Define some misc macros.  We keep them with the operands table
 241    for simplicity.  The macro table is an array of struct i370_macro.  */
 242
 243 struct i370_macro
 244 {
 245   /* The macro name.  */
 246   const char *name;
 247
 248   /* The number of operands the macro takes.  */
 249   unsigned int operands;
 250
 251   /* One bit flags for the opcode.  These are used to indicate which
 252      specific processors support the instructions.  The values are the
 253      same as those for the struct i370_opcode flags field.  */
 254   unsigned long flags;
 255
 256   /* A format string to turn the macro into a normal instruction.
 257      Each %N in the string is replaced with operand number N (zero
 258      based).  */
 259   const char *format;
 260 };
 261
 262 extern const struct i370_macro i370_macros[];
 263 extern const int i370_num_macros;
 264
 265
 266 #endif /* I370_H */