sdcc/support/sdbinutils/include/opcode/riscv.h

   1 /* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
   2    Copyright (C) 2011-2022 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    3, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef _RISCV_H_
  22 #define _RISCV_H_
  23
  24 #include "riscv-opc.h"
  25 #include <stdlib.h>
  26 #include <stdint.h>
  27
  28 typedef uint64_t insn_t;
  29
  30 static inline unsigned int riscv_insn_length (insn_t insn)
  31 {
  32   if ((insn & 0x3) != 0x3) /* RVC instructions.  */
  33     return 2;
  34   if ((insn & 0x1f) != 0x1f) /* 32-bit instructions.  */
  35     return 4;
  36   if ((insn & 0x3f) == 0x1f) /* 48-bit instructions.  */
  37     return 6;
  38   if ((insn & 0x7f) == 0x3f) /* 64-bit instructions.  */
  39     return 8;
  40   /* Longer instructions not supported at the moment.  */
  41   return 2;
  42 }
  43
  44 static const char * const riscv_rm[8] =
  45 {
  46   "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
  47 };
  48
  49 static const char * const riscv_pred_succ[16] =
  50 {
  51   0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
  52   "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
  53 };
  54
  55 #define RVC_JUMP_BITS 11
  56 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
  57
  58 #define RVC_BRANCH_BITS 8
  59 #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
  60
  61 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
  62 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
  63
  64 #define EXTRACT_ITYPE_IMM(x) \
  65   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
  66 #define EXTRACT_STYPE_IMM(x) \
  67   (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
  68 #define EXTRACT_BTYPE_IMM(x) \
  69   ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
  70 #define EXTRACT_UTYPE_IMM(x) \
  71   ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
  72 #define EXTRACT_JTYPE_IMM(x) \
  73   ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
  74 #define EXTRACT_CITYPE_IMM(x) \
  75   (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
  76 #define EXTRACT_CITYPE_LUI_IMM(x) \
  77   (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
  78 #define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
  79   ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
  80 #define EXTRACT_CITYPE_LWSP_IMM(x) \
  81   ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
  82 #define EXTRACT_CITYPE_LDSP_IMM(x) \
  83   ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
  84 #define EXTRACT_CSSTYPE_IMM(x) \
  85   (RV_X(x, 7, 6) << 0)
  86 #define EXTRACT_CSSTYPE_SWSP_IMM(x) \
  87   ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
  88 #define EXTRACT_CSSTYPE_SDSP_IMM(x) \
  89   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
  90 #define EXTRACT_CIWTYPE_IMM(x) \
  91   (RV_X(x, 5, 8))
  92 #define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
  93   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
  94 #define EXTRACT_CLTYPE_IMM(x) \
  95   ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
  96 #define EXTRACT_CLTYPE_LW_IMM(x) \
  97   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
  98 #define EXTRACT_CLTYPE_LD_IMM(x) \
  99   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
 100 #define EXTRACT_CBTYPE_IMM(x) \
 101   ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
 102 #define EXTRACT_CJTYPE_IMM(x) \
 103   ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
 104 #define EXTRACT_RVV_VI_IMM(x) \
 105   (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
 106 #define EXTRACT_RVV_VI_UIMM(x) \
 107   (RV_X(x, 15, 5))
 108 #define EXTRACT_RVV_OFFSET(x) \
 109   (RV_X(x, 29, 3))
 110 #define EXTRACT_RVV_VB_IMM(x) \
 111   (RV_X(x, 20, 10))
 112 #define EXTRACT_RVV_VC_IMM(x) \
 113   (RV_X(x, 20, 11))
 114
 115 #define ENCODE_ITYPE_IMM(x) \
 116   (RV_X(x, 0, 12) << 20)
 117 #define ENCODE_STYPE_IMM(x) \
 118   ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
 119 #define ENCODE_BTYPE_IMM(x) \
 120   ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
 121 #define ENCODE_UTYPE_IMM(x) \
 122   (RV_X(x, 12, 20) << 12)
 123 #define ENCODE_JTYPE_IMM(x) \
 124   ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
 125 #define ENCODE_CITYPE_IMM(x) \
 126   ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
 127 #define ENCODE_CITYPE_LUI_IMM(x) \
 128   ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
 129 #define ENCODE_CITYPE_ADDI16SP_IMM(x) \
 130   ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
 131 #define ENCODE_CITYPE_LWSP_IMM(x) \
 132   ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
 133 #define ENCODE_CITYPE_LDSP_IMM(x) \
 134   ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
 135 #define ENCODE_CSSTYPE_IMM(x) \
 136   (RV_X(x, 0, 6) << 7)
 137 #define ENCODE_CSSTYPE_SWSP_IMM(x) \
 138   ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
 139 #define ENCODE_CSSTYPE_SDSP_IMM(x) \
 140   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
 141 #define ENCODE_CIWTYPE_IMM(x) \
 142   (RV_X(x, 0, 8) << 5)
 143 #define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
 144   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
 145 #define ENCODE_CLTYPE_IMM(x) \
 146   ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
 147 #define ENCODE_CLTYPE_LW_IMM(x) \
 148   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
 149 #define ENCODE_CLTYPE_LD_IMM(x) \
 150   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
 151 #define ENCODE_CBTYPE_IMM(x) \
 152   ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
 153 #define ENCODE_CJTYPE_IMM(x) \
 154   ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
 155 #define ENCODE_RVV_VB_IMM(x) \
 156   (RV_X(x, 0, 10) << 20)
 157 #define ENCODE_RVV_VC_IMM(x) \
 158   (RV_X(x, 0, 11) << 20)
 159
 160 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 161 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
 162 #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
 163 #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
 164 #define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
 165 #define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
 166 #define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
 167                                  && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
 168 #define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
 169                                       && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
 170 #define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
 171 #define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
 172 #define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
 173 #define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
 174 #define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
 175 #define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
 176 #define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
 177 #define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
 178 #define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
 179 #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
 180 #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
 181 #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
 182 #define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
 183 #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
 184
 185 #define RISCV_RTYPE(insn, rd, rs1, rs2) \
 186   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
 187 #define RISCV_ITYPE(insn, rd, rs1, imm) \
 188   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
 189 #define RISCV_STYPE(insn, rs1, rs2, imm) \
 190   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
 191 #define RISCV_BTYPE(insn, rs1, rs2, target) \
 192   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
 193 #define RISCV_UTYPE(insn, rd, bigimm) \
 194   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
 195 #define RISCV_JTYPE(insn, rd, target) \
 196   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))
 197
 198 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
 199 #define RVC_NOP MATCH_C_ADDI
 200
 201 #define RISCV_CONST_HIGH_PART(VALUE) \
 202   (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
 203 #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
 204 #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
 205 #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
 206
 207 #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
 208 #define RISCV_JUMP_ALIGN_BITS 1
 209 #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
 210 #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
 211
 212 #define RISCV_IMM_BITS 12
 213 #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
 214 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
 215 #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
 216 #define RISCV_RVC_IMM_REACH (1LL << 6)
 217 #define RISCV_BRANCH_BITS RISCV_IMM_BITS
 218 #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
 219 #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
 220 #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
 221
 222 /* RV fields.  */
 223
 224 #define OP_MASK_OP              0x7f
 225 #define OP_SH_OP                0
 226 #define OP_MASK_RS2             0x1f
 227 #define OP_SH_RS2               20
 228 #define OP_MASK_RS1             0x1f
 229 #define OP_SH_RS1               15
 230 #define OP_MASK_RS3             0x1fU
 231 #define OP_SH_RS3               27
 232 #define OP_MASK_RD              0x1f
 233 #define OP_SH_RD                7
 234 #define OP_MASK_SHAMT           0x3f
 235 #define OP_SH_SHAMT             20
 236 #define OP_MASK_SHAMTW          0x1f
 237 #define OP_SH_SHAMTW            20
 238 #define OP_MASK_RM              0x7
 239 #define OP_SH_RM                12
 240 #define OP_MASK_PRED            0xf
 241 #define OP_SH_PRED              24
 242 #define OP_MASK_SUCC            0xf
 243 #define OP_SH_SUCC              20
 244 #define OP_MASK_AQ              0x1
 245 #define OP_SH_AQ                26
 246 #define OP_MASK_RL              0x1
 247 #define OP_SH_RL                25
 248
 249 #define OP_MASK_CSR             0xfffU
 250 #define OP_SH_CSR               20
 251
 252 #define OP_MASK_FUNCT3          0x7
 253 #define OP_SH_FUNCT3            12
 254 #define OP_MASK_FUNCT7          0x7fU
 255 #define OP_SH_FUNCT7            25
 256 #define OP_MASK_FUNCT2          0x3
 257 #define OP_SH_FUNCT2            25
 258
 259 /* RVC fields.  */
 260
 261 #define OP_MASK_OP2             0x3
 262 #define OP_SH_OP2               0
 263
 264 #define OP_MASK_CRS2            0x1f
 265 #define OP_SH_CRS2              2
 266 #define OP_MASK_CRS1S           0x7
 267 #define OP_SH_CRS1S             7
 268 #define OP_MASK_CRS2S           0x7
 269 #define OP_SH_CRS2S             2
 270
 271 #define OP_MASK_CFUNCT6         0x3f
 272 #define OP_SH_CFUNCT6           10
 273 #define OP_MASK_CFUNCT4         0xf
 274 #define OP_SH_CFUNCT4           12
 275 #define OP_MASK_CFUNCT3         0x7
 276 #define OP_SH_CFUNCT3           13
 277 #define OP_MASK_CFUNCT2         0x3
 278 #define OP_SH_CFUNCT2           5
 279
 280 /* Scalar crypto fields. */
 281
 282 #define OP_SH_BS        30
 283 #define OP_MASK_BS      3
 284 #define OP_SH_RNUM      20
 285 #define OP_MASK_RNUM    0xf
 286
 287 /* RVV fields.  */
 288
 289 #define OP_MASK_VD              0x1f
 290 #define OP_SH_VD                7
 291 #define OP_MASK_VS1             0x1f
 292 #define OP_SH_VS1               15
 293 #define OP_MASK_VS2             0x1f
 294 #define OP_SH_VS2               20
 295 #define OP_MASK_VIMM            0x1f
 296 #define OP_SH_VIMM              15
 297 #define OP_MASK_VMASK           0x1
 298 #define OP_SH_VMASK             25
 299 #define OP_MASK_VFUNCT6         0x3f
 300 #define OP_SH_VFUNCT6           26
 301 #define OP_MASK_VLMUL           0x7
 302 #define OP_SH_VLMUL             0
 303 #define OP_MASK_VSEW            0x7
 304 #define OP_SH_VSEW              3
 305 #define OP_MASK_VTA             0x1
 306 #define OP_SH_VTA               6
 307 #define OP_MASK_VMA             0x1
 308 #define OP_SH_VMA               7
 309 #define OP_MASK_VWD             0x1
 310 #define OP_SH_VWD               26
 311
 312 #define NVECR 32
 313 #define NVECM 1
 314
 315 /* ABI names for selected x-registers.  */
 316
 317 #define X_RA 1
 318 #define X_SP 2
 319 #define X_GP 3
 320 #define X_TP 4
 321 #define X_T0 5
 322 #define X_T1 6
 323 #define X_T2 7
 324 #define X_T3 28
 325
 326 #define NGPR 32
 327 #define NFPR 32
 328
 329 /* These fake label defines are use by both the assembler, and
 330    libopcodes.  The assembler uses this when it needs to generate a fake
 331    label, and libopcodes uses it to hide the fake labels in its output.  */
 332 #define RISCV_FAKE_LABEL_NAME ".L0 "
 333 #define RISCV_FAKE_LABEL_CHAR ' '
 334
 335 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
 336    VALUE << SHIFT.  VALUE is evaluated exactly once.  */
 337 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
 338   (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
 339               | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
 340
 341 /* Extract bits MASK << SHIFT from STRUCT and shift them right
 342    SHIFT places.  */
 343 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
 344   (((STRUCT) >> (SHIFT)) & (MASK))
 345
 346 /* Extract the operand given by FIELD from integer INSN.  */
 347 #define EXTRACT_OPERAND(FIELD, INSN) \
 348   EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
 349
 350 /* The maximal number of subset can be required.  */
 351 #define MAX_SUBSET_NUM 4
 352
 353 /* All RISC-V instructions belong to at least one of these classes.  */
 354 enum riscv_insn_class
 355 {
 356   INSN_CLASS_NONE,
 357
 358   INSN_CLASS_I,
 359   INSN_CLASS_C,
 360   INSN_CLASS_A,
 361   INSN_CLASS_M,
 362   INSN_CLASS_F,
 363   INSN_CLASS_D,
 364   INSN_CLASS_Q,
 365   INSN_CLASS_F_AND_C,
 366   INSN_CLASS_D_AND_C,
 367   INSN_CLASS_ZICSR,
 368   INSN_CLASS_ZIFENCEI,
 369   INSN_CLASS_ZIHINTPAUSE,
 370   INSN_CLASS_F_OR_ZFINX,
 371   INSN_CLASS_D_OR_ZDINX,
 372   INSN_CLASS_Q_OR_ZQINX,
 373   INSN_CLASS_ZBA,
 374   INSN_CLASS_ZBB,
 375   INSN_CLASS_ZBC,
 376   INSN_CLASS_ZBS,
 377   INSN_CLASS_ZBKB,
 378   INSN_CLASS_ZBKC,
 379   INSN_CLASS_ZBKX,
 380   INSN_CLASS_ZKND,
 381   INSN_CLASS_ZKNE,
 382   INSN_CLASS_ZKNH,
 383   INSN_CLASS_ZKSED,
 384   INSN_CLASS_ZKSH,
 385   INSN_CLASS_ZBB_OR_ZBKB,
 386   INSN_CLASS_ZBC_OR_ZBKC,
 387   INSN_CLASS_ZKND_OR_ZKNE,
 388   INSN_CLASS_V,
 389   INSN_CLASS_ZVEF,
 390   INSN_CLASS_SVINVAL,
 391 };
 392
 393 /* This structure holds information for a particular instruction.  */
 394 struct riscv_opcode
 395 {
 396   /* The name of the instruction.  */
 397   const char *name;
 398
 399   /* The requirement of xlen for the instruction, 0 if no requirement.  */
 400   unsigned xlen_requirement;
 401
 402   /* Class to which this instruction belongs.  Used to decide whether or
 403      not this instruction is legal in the current -march context.  */
 404   enum riscv_insn_class insn_class;
 405
 406   /* A string describing the arguments for this instruction.  */
 407   const char *args;
 408
 409   /* The basic opcode for the instruction.  When assembling, this
 410      opcode is modified by the arguments to produce the actual opcode
 411      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 412   insn_t match;
 413
 414   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 415      relevant portions of the opcode when disassembling.  If the
 416      actual opcode anded with the match field equals the opcode field,
 417      then we have found the correct instruction.  If pinfo is
 418      INSN_MACRO, then this field is the macro identifier.  */
 419   insn_t mask;
 420
 421   /* A function to determine if a word corresponds to this instruction.
 422      Usually, this computes ((word & mask) == match).  */
 423   int (*match_func) (const struct riscv_opcode *op, insn_t word);
 424
 425   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 426      of bits describing the instruction, notably any relevant hazard
 427      information.  */
 428   unsigned long pinfo;
 429 };
 430
 431 /* Instruction is a simple alias (e.g. "mv" for "addi").  */
 432 #define INSN_ALIAS              0x00000001
 433
 434 /* These are for setting insn_info fields.
 435
 436    Nonbranch is the default.  Noninsn is used only if there is no match.
 437    There are no condjsr or dref2 instructions.  So that leaves condbranch,
 438    branch, jsr, and dref that we need to handle here, encoded in 3 bits.  */
 439 #define INSN_TYPE               0x0000000e
 440
 441 /* Instruction is an unconditional branch.  */
 442 #define INSN_BRANCH             0x00000002
 443 /* Instruction is a conditional branch.  */
 444 #define INSN_CONDBRANCH         0x00000004
 445 /* Instruction is a jump to subroutine.  */
 446 #define INSN_JSR                0x00000006
 447 /* Instruction is a data reference.  */
 448 #define INSN_DREF               0x00000008
 449 /* Instruction is allowed when eew >= 64.  */
 450 #define INSN_V_EEW64            0x10000000
 451
 452 /* We have 5 data reference sizes, which we can encode in 3 bits.  */
 453 #define INSN_DATA_SIZE          0x00000070
 454 #define INSN_DATA_SIZE_SHIFT    4
 455 #define INSN_1_BYTE             0x00000010
 456 #define INSN_2_BYTE             0x00000020
 457 #define INSN_4_BYTE             0x00000030
 458 #define INSN_8_BYTE             0x00000040
 459 #define INSN_16_BYTE            0x00000050
 460
 461 /* Instruction is actually a macro.  It should be ignored by the
 462    disassembler, and requires special treatment by the assembler.  */
 463 #define INSN_MACRO              0xffffffff
 464
 465 /* This is a list of macro expanded instructions.  */
 466 enum
 467 {
 468   M_LA,
 469   M_LLA,
 470   M_LA_TLS_GD,
 471   M_LA_TLS_IE,
 472   M_LB,
 473   M_LBU,
 474   M_LH,
 475   M_LHU,
 476   M_LW,
 477   M_LWU,
 478   M_LD,
 479   M_SB,
 480   M_SH,
 481   M_SW,
 482   M_SD,
 483   M_FLW,
 484   M_FLD,
 485   M_FLQ,
 486   M_FSW,
 487   M_FSD,
 488   M_FSQ,
 489   M_CALL,
 490   M_J,
 491   M_LI,
 492   M_ZEXTH,
 493   M_ZEXTW,
 494   M_SEXTB,
 495   M_SEXTH,
 496   M_VMSGE,
 497   M_VMSGEU,
 498   M_NUM_MACROS
 499 };
 500
 501 /* The mapping symbol states.  */
 502 enum riscv_seg_mstate
 503 {
 504   MAP_NONE = 0,         /* Must be zero, for seginfo in new sections.  */
 505   MAP_DATA,             /* Data.  */
 506   MAP_INSN,             /* Instructions.  */
 507 };
 508
 509 extern const char * const riscv_gpr_names_numeric[NGPR];
 510 extern const char * const riscv_gpr_names_abi[NGPR];
 511 extern const char * const riscv_fpr_names_numeric[NFPR];
 512 extern const char * const riscv_fpr_names_abi[NFPR];
 513 extern const char * const riscv_vecr_names_numeric[NVECR];
 514 extern const char * const riscv_vecm_names_numeric[NVECM];
 515 extern const char * const riscv_vsew[8];
 516 extern const char * const riscv_vlmul[8];
 517 extern const char * const riscv_vta[2];
 518 extern const char * const riscv_vma[2];
 519
 520 extern const struct riscv_opcode riscv_opcodes[];
 521 extern const struct riscv_opcode riscv_insn_types[];
 522
 523 #endif /* _RISCV_H_ */