sdcc-extra/emu/rrz80/cpu/z80_op1.c

   1 /*
   2  * Copyright (C) 1996-1998 Szeredi Miklos
   3  * Email: mszeredi@inf.bme.hu
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version. See the file COPYING.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  */
  20
  21 #ifndef NO_OPDEF
  22 #include "z80_def.h"
  23 #include "z80_op1.h"
  24 #endif
  25
  26 OPDEF(nop, 0x00)
  27 {
  28   ENTIME(4);
  29 }
  30
  31 OPDEF(ex_af_afb, 0x08)
  32 {
  33   register byte *ptmp;
  34
  35   ptmp = DANM(br)[ZI_AF].p;
  36   DANM(br)[ZI_AF].p = DANM(nr)[ZI_AF].p;
  37   DANM(nr)[ZI_AF].p = ptmp;
  38
  39   ENTIME(4);
  40 }
  41
  42 OPDEF(djnz_e, 0x10)
  43 {
  44   if(!--RB) {
  45     PC++;
  46     ENTIME(8);
  47   }
  48   else {
  49     PC += IPCS; PC++;
  50     ENTIME(13);
  51   }
  52 }
  53
  54 OPDEF(jr_e, 0x18)
  55 {
  56   PC += IPCS; PC++;
  57   ENTIME(12);
  58 }
  59
  60 #define JR_CC_E(ccn, cc, n) \
  61 OPDEF(jr_ ## ccn ## _e, 0x20+n*8)  \
  62 {                                  \
  63   if(!(cc)) {                      \
  64     PC++;                          \
  65     ENTIME(7);                     \
  66   }                                \
  67   else {                           \
  68     PC += IPCS; PC++;              \
  69     ENTIME(12);                    \
  70   }                                \
  71 }
  72
  73 JR_CC_E(nz, !TESTZF, 0)
  74 JR_CC_E(z,  TESTZF,  1)
  75 JR_CC_E(nc, !TESTCF, 2)
  76 JR_CC_E(c,  TESTCF,  3)
  77
  78
  79 #define LD_RR_NN(rrn, rr, n) \
  80 OPDEF(ld_ ## rrn ## _nn, 0x01+n*0x10)         \
  81 {                                             \
  82   FETCHD(rr);                                 \
  83   ENTIME(10);                                 \
  84 }
  85
  86 LD_RR_NN(bc, BC, 0)
  87 LD_RR_NN(de, DE, 1)
  88 LD_RR_NN(hl, HL, 2)
  89 LD_RR_NN(sp, SP, 3)
  90
  91 #define DADD(rr1, rr2) \
  92   register dbyte dtmp;             \
  93   register int idx;                \
  94   dtmp = rr1;                      \
  95   rr1 = dtmp + rr2;                \
  96   idx = DIDXCALC(dtmp, rr2, rr1);  \
  97   SETFLAGS(CF | NF | HF, TAB(addf_tbl)[idx] & (CF | HF))
  98
  99
 100 #define ADD_RR_RR(rrn1, rr1, rrn2, rr2, n) \
 101 OPDEF(add_## rrn1 ## _ ## rrn2, 0x09+n*0x10) \
 102 {                                  \
 103   DADD(rr1, rr2);                  \
 104   ENTIME(11);                      \
 105 }
 106
 107 ADD_RR_RR(hl, HL, bc, BC, 0)
 108 ADD_RR_RR(hl, HL, de, DE, 1)
 109 ADD_RR_RR(hl, HL, hl, HL, 2)
 110 ADD_RR_RR(hl, HL, sp, SP, 3)
 111
 112 #define INC_RR(rrn, rr, n) \
 113 OPDEF(inc_ ## rrn, 0x03+n*0x10)    \
 114 {                                  \
 115   rr++;                            \
 116   ENTIME(6);                       \
 117 }
 118
 119 INC_RR(bc, BC, 0)
 120 INC_RR(de, DE, 1)
 121 INC_RR(hl, HL, 2)
 122 INC_RR(sp, SP, 3)
 123
 124 #define DEC_RR(rrn, rr, n) \
 125 OPDEF(dec_ ## rrn, 0x0B+n*0x10)    \
 126 {                                  \
 127   rr--;                            \
 128   ENTIME(6);                       \
 129 }
 130
 131 DEC_RR(bc, BC, 0)
 132 DEC_RR(de, DE, 1)
 133 DEC_RR(hl, HL, 2)
 134 DEC_RR(sp, SP, 3)
 135
 136 OPDEF(ld_ibc_a, 0x02)
 137 {
 138   PUTMEM(BC, BCP, RA);
 139   ENTIME(7);
 140 }
 141
 142 OPDEF(ld_ide_a, 0x12)
 143 {
 144   PUTMEM(DE, DEP, RA);
 145   ENTIME(7);
 146 }
 147
 148 #define LD_INN_RR(rrn, rr) \
 149 OPDEF(ld_inn_ ## rrn, 0x22)        \
 150 {                                  \
 151   register dbyte dtmp;             \
 152   FETCHD(dtmp);                    \
 153   DWRITE(dtmp, rr);                \
 154   ENTIME(16);                      \
 155 }
 156
 157 LD_INN_RR(hl, HL)
 158
 159
 160 OPDEF(ld_inn_a, 0x32)
 161 {
 162   register dbyte dtmp;
 163   FETCHD(dtmp);
 164   WRITE(dtmp, RA);
 165   ENTIME(13);
 166 }
 167
 168 OPDEF(ld_a_ibc, 0x0A)
 169 {
 170   RA = *BCP;
 171   ENTIME(7);
 172 }
 173
 174 OPDEF(ld_a_ide, 0x1A)
 175 {
 176   RA = *DEP;
 177   ENTIME(7);
 178 }
 179
 180
 181 #define LD_RR_INN(rrn, rr) \
 182 OPDEF(ld_ ## rrn ## _inn, 0x2A)    \
 183 {                                  \
 184   register dbyte dtmp;             \
 185   FETCHD(dtmp);                    \
 186   rr = DREAD(dtmp);                \
 187   ENTIME(16);                      \
 188 }
 189
 190 LD_RR_INN(hl, HL)
 191
 192
 193 OPDEF(ld_a_inn, 0x3A)
 194 {
 195   register dbyte dtmp;
 196   FETCHD(dtmp);
 197   RA = READ(dtmp);
 198   ENTIME(13);
 199 }
 200
 201
 202 #define INC(r) \
 203   r++;                             \
 204   SETFLAGS(SF | ZF | PVF | B3F | B5F, TAB(incf_tbl)[r])
 205
 206
 207
 208 #define INC_R(rn, r, n) \
 209 OPDEF(inc_ ## rn, 0x04+n*8)        \
 210 {                                  \
 211   INC(r);                          \
 212   ENTIME(4);                       \
 213 }
 214
 215 INC_R(b, RB, 0)
 216 INC_R(c, RC, 1)
 217 INC_R(d, RD, 2)
 218 INC_R(e, RE, 3)
 219 INC_R(h, RH, 4)
 220 INC_R(l, RL, 5)
 221 INC_R(a, RA, 7)
 222
 223
 224 OPDEF(inc_ihl, 0x34)
 225 {
 226   MODMEM(INC);
 227   ENTIME(11);
 228 }
 229
 230
 231 #define DEC(r) \
 232   r--;                             \
 233   SETFLAGS(SF | ZF | PVF | B3F | B5F, TAB(decf_tbl)[r])
 234
 235
 236 #define DEC_R(rn, r, n) \
 237 OPDEF(dec_ ## rn, 0x05+n*8)        \
 238 {                                  \
 239   DEC(r);                          \
 240   ENTIME(4);                       \
 241 }
 242
 243 DEC_R(b, RB, 0)
 244 DEC_R(c, RC, 1)
 245 DEC_R(d, RD, 2)
 246 DEC_R(e, RE, 3)
 247 DEC_R(h, RH, 4)
 248 DEC_R(l, RL, 5)
 249 DEC_R(a, RA, 7)
 250
 251
 252 OPDEF(dec_ihl, 0x35)
 253 {
 254   MODMEM(DEC);
 255   ENTIME(11);
 256 }
 257
 258 #define LD_R_N(rn, r, n) \
 259 OPDEF(ld_ ## rn ## _n, 0x06+n*8)   \
 260 {                                  \
 261   r = *PCP;                        \
 262   PC++;                            \
 263   ENTIME(7);                       \
 264 }
 265
 266 LD_R_N(b, RB, 0)
 267 LD_R_N(c, RC, 1)
 268 LD_R_N(d, RD, 2)
 269 LD_R_N(e, RE, 3)
 270 LD_R_N(h, RH, 4)
 271 LD_R_N(l, RL, 5)
 272 LD_R_N(a, RA, 7)
 273
 274
 275 OPDEF(ld_ihl_n, 0x36)
 276 {
 277   PUTMEM(HL, HLP, *PCP);
 278   PC++;
 279   ENTIME(10);
 280 }
 281
 282 OPDEF(rlca, 0x07)
 283 {
 284   register byte btmp;
 285   btmp = (RA & 0x80) >> 7;
 286   SETFLAGS(HF | NF | CF, btmp);
 287   RA = (RA << 1) | btmp;
 288   ENTIME(4);
 289 }
 290
 291 OPDEF(rrca, 0x0F)
 292 {
 293   register byte btmp;
 294   btmp = (RA & 0x01);
 295   SETFLAGS(HF | NF | CF, btmp);
 296   if(btmp) {
 297     RA = (RA >> 1) | 0x80;
 298     ENTIME(4);
 299   }
 300   else {
 301     RA >>= 1;
 302     ENTIME(4);
 303   }
 304 }
 305
 306
 307 OPDEF(rla, 0x17)
 308 {
 309   register byte btmp;
 310   btmp = RA & 0x80;
 311   RA = (RA << 1) | (RF & CF);
 312   SETFLAGS(HF | NF | CF, btmp >> 7);
 313   ENTIME(4);
 314 }
 315
 316 OPDEF(rra, 0x1F)
 317 {
 318   register byte btmp;
 319   btmp = TESTCF;
 320   SETFLAGS(HF | NF | CF, RA & 0x01);
 321   if(btmp) {
 322     RA = (RA >> 1) | 0x80;
 323     ENTIME(4);
 324   }
 325   else {
 326     RA >>= 1;
 327     ENTIME(4);
 328   }
 329 }
 330
 331 OPDEF(daa, 0x27)
 332 {
 333   register int flag;
 334   flag = RF;
 335
 336   if(!TESTNF) {
 337     if(flag & CF) RA += 0x60;
 338     else if(RA > 0x99) RA += 0x60, flag |= CF;
 339
 340     if(flag & HF) RA += 0x06;
 341     else if((RA & 0x0F) > 9) RA += 0x06, flag |= HF;
 342   }
 343   else {
 344     if(flag & CF) RA -= 0x60;
 345     else if(RA > 0x99) RA -= 0x60, flag |= CF;
 346
 347     if(flag & HF) RA -= 0x06;
 348     else if((RA & 0x0F) > 9) RA -= 0x06, flag |= HF;
 349   }
 350   flag = (flag & ~(SF | ZF | PVF | B3F | B5F)) | TAB(orf_tbl)[RA];
 351   RF = flag;
 352
 353   ENTIME(4);
 354 }
 355
 356 OPDEF(cpl, 0x2F)
 357 {
 358   RA = ~RA;
 359   SET_FL(HF | NF);
 360   ENTIME(4);
 361 }
 362
 363 OPDEF(scf, 0x37)
 364 {
 365   SETFLAGS(HF | NF, CF);
 366   ENTIME(4);
 367 }
 368
 369 OPDEF(ccf, 0x3F)
 370 {
 371   RF = (RF ^ CF) & ~(NF);
 372 /* HF undefined */
 373   ENTIME(4);
 374 }
 375
 376 #include "z80_op1x.c"