sdcc-extra/emu/rrz80/cpu/z80_op4.c

   1 /*
   2  * Copyright (C) 1996-1998 Szeredi Miklos
   3  * Email: mszeredi@inf.bme.hu
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version. See the file COPYING.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  */
  20
  21 #ifndef NO_OPDEF
  22 #include "z80_def.h"
  23 #include "z80_op4.h"
  24 #include "z80_ari.h"
  25 #endif
  26
  27 #if RETURN_HOOK
  28 void returnHook(void);
  29 #define RETURNHOOK      returnHook()
  30 #else
  31 #define RETURNHOOK
  32 #endif
  33
  34 #define RET_CC(ccn, cc, n) \
  35 OPDEF(ret_ ## ccn, 0xC0+n*8)       \
  36 {                                  \
  37   RETURNHOOK;                      \
  38   if(!(cc)) {                      \
  39     ENTIME(5);                     \
  40   }                                \
  41   else {                           \
  42     POP(PC);                       \
  43     ENTIME(11);                    \
  44   }                                \
  45 }
  46
  47 RET_CC(nz, !TESTZF, 0)
  48 RET_CC(z,  TESTZF,  1)
  49 RET_CC(nc, !TESTCF, 2)
  50 RET_CC(c,  TESTCF,  3)
  51 RET_CC(po, !TESTPF, 4)
  52 RET_CC(pe, TESTPF,  5)
  53 RET_CC(p,  !TESTSF, 6)
  54 RET_CC(m,  TESTSF,  7)
  55
  56 #define POP_RR(rrn, rr, n) \
  57 OPDEF(pop_ ## rrn, 0xC1+n*0x10)    \
  58 {                                  \
  59   POP(rr);                         \
  60   ENTIME(10);                      \
  61 }
  62
  63 POP_RR(bc, BC, 0)
  64 POP_RR(de, DE, 1)
  65 POP_RR(hl, HL, 2)
  66 POP_RR(af, AF, 3)
  67
  68 OPDEF(ret, 0xC9)
  69 {
  70   RETURNHOOK;
  71   POP(PC);
  72   ENTIME(10);
  73 }
  74
  75 OPDEF(exx, 0xD9)
  76 {
  77   register dbyte dtmp;
  78
  79   dtmp = BCBK, BCBK = BC, BC = dtmp;
  80   dtmp = DEBK, DEBK = DE, DE = dtmp;
  81   dtmp = HLBK, HLBK = HL, HL = dtmp;
  82
  83   ENTIME(4);
  84 }
  85
  86 #define JP_RR(rrn, rr) \
  87 OPDEF(jp_ ## rrn, 0xE9)            \
  88 {                                  \
  89   PC = rr;                         \
  90   ENTIME(4);                       \
  91 }
  92
  93 JP_RR(hl, HL)
  94
  95 #define LD_SP_RR(rrn, rr) \
  96 OPDEF(ld_sp_ ## rrn, 0xF9)         \
  97 {                                  \
  98   SP = rr;                         \
  99   ENTIME(6);                       \
 100 }
 101
 102 LD_SP_RR(hl, HL)
 103
 104 #define JP_CC(ccn, cc, n) \
 105 OPDEF(jp_ ## ccn ## _nn, 0xC2+n*8) \
 106 {                                  \
 107   if(!(cc)) {                      \
 108     PC+=2;                         \
 109     ENTIME(10);                    \
 110   }                                \
 111   else {                           \
 112     PC = DREAD(PC);                \
 113     ENTIME(10);                    \
 114   }                                \
 115 }
 116
 117 JP_CC(nz, !TESTZF, 0)
 118 JP_CC(z,  TESTZF,  1)
 119 JP_CC(nc, !TESTCF, 2)
 120 JP_CC(c,  TESTCF,  3)
 121 JP_CC(po, !TESTPF, 4)
 122 JP_CC(pe, TESTPF,  5)
 123 JP_CC(p,  !TESTSF, 6)
 124 JP_CC(m,  TESTSF,  7)
 125
 126 OPDEF(jp_nn, 0xC3)
 127 {
 128   PC = DREAD(PC);
 129   ENTIME(10);
 130 }
 131
 132
 133 OPDEF(out_in_a, 0xD3)
 134 {
 135   OUT(RA, *PCP, RA);
 136   PC++;
 137   ENTIME(11);
 138 }
 139
 140 OPDEF(in_a_in, 0xDB)
 141 {
 142   IN(RA, *PCP, RA);
 143   PC++;
 144   ENTIME(11);
 145 }
 146
 147 #define EX_ISP_RR(rrn, rr) \
 148 OPDEF(ex_isp_ ## rrn, 0xE3)        \
 149 {                                  \
 150   register dbyte dtmp;             \
 151   dtmp = DREAD(SP);                \
 152   DWRITE(SP, rr);                  \
 153   rr = dtmp;                       \
 154   ENTIME(19);                      \
 155 }
 156
 157 EX_ISP_RR(hl, HL)
 158
 159 OPDEF(ex_de_hl, 0xEB)
 160 {
 161   register dbyte dtmp;
 162   dtmp = DE;
 163   DE = HL;
 164   HL = dtmp;
 165   ENTIME(4);
 166 }
 167
 168 OPDEF(di, 0xF3)
 169 {
 170   DANM(iff1) = 0;
 171   DANM(iff2) = 0;
 172   DI_CHECK
 173   ENTIME(4);
 174 }
 175
 176 OPDEF(ei, 0xFB)
 177 {
 178   DANM(iff1) = 1;
 179   DANM(iff2) = 1;
 180   ENTIME(4);
 181 }
 182
 183
 184
 185 #define CALL_CC(ccn, cc, n) \
 186 OPDEF(call_ ## ccn ## _nn, 0xC4+n*8) \
 187 {                                  \
 188   if(!(cc)) {                      \
 189     PC+=2;                         \
 190     ENTIME(10);                    \
 191   }                                \
 192   else {                           \
 193     register dbyte dtmp;           \
 194     dtmp = PC;                     \
 195     PC = DREAD(dtmp);              \
 196     dtmp += 2;                     \
 197     PUSH(dtmp);                    \
 198     ENTIME(17);                    \
 199   }                                \
 200 }
 201
 202 CALL_CC(nz, !TESTZF, 0)
 203 CALL_CC(z,  TESTZF,  1)
 204 CALL_CC(nc, !TESTCF, 2)
 205 CALL_CC(c,  TESTCF,  3)
 206 CALL_CC(po, !TESTPF, 4)
 207 CALL_CC(pe, TESTPF,  5)
 208 CALL_CC(p,  !TESTSF, 6)
 209 CALL_CC(m,  TESTSF,  7)
 210
 211
 212
 213 #define PUSH_RR(rrn, rr, n) \
 214 OPDEF(push_ ## rrn, 0xC5+n*0x10)   \
 215 {                                  \
 216   PUSH(rr);                        \
 217   ENTIME(11);                      \
 218 }
 219
 220 PUSH_RR(bc, BC, 0)
 221 PUSH_RR(de, DE, 1)
 222 PUSH_RR(hl, HL, 2)
 223 PUSH_RR(af, AF, 3)
 224
 225
 226 OPDEF(call_nn, 0xCD)
 227 {
 228   register dbyte dtmp;
 229   dtmp = PC;
 230   PC = DREAD(dtmp);
 231   dtmp += 2;
 232   PUSH(dtmp);
 233   ENTIME(17);
 234 }
 235
 236
 237 OPDEF(add_a_n, 0xC6)
 238 {
 239   ADD(*PCP);
 240   PC++;
 241   ENTIME(7);
 242 }
 243
 244
 245 OPDEF(adc_a_n, 0xCE)
 246 {
 247   ADC(*PCP);
 248   PC++;
 249   ENTIME(7);
 250 }
 251
 252 OPDEF(sub_n, 0xD6)
 253 {
 254   SUB(*PCP);
 255   PC++;
 256   ENTIME(7);
 257 }
 258
 259
 260 OPDEF(sbc_a_n, 0xDE)
 261 {
 262   SBC(*PCP);
 263   PC++;
 264   ENTIME(7);
 265 }
 266
 267 OPDEF(and_n, 0xE6)
 268 {
 269   AND(*PCP);
 270   PC++;
 271   ENTIME(7);
 272 }
 273
 274
 275 OPDEF(xor_n, 0xEE)
 276 {
 277   XOR(*PCP);
 278   PC++;
 279   ENTIME(7);
 280 }
 281
 282 OPDEF(or_n, 0xF6)
 283 {
 284   OR(*PCP);
 285   PC++;
 286   ENTIME(7);
 287 }
 288
 289
 290 OPDEF(cp_n, 0xFE)
 291 {
 292   CP(*PCP);
 293   PC++;
 294   ENTIME(7);
 295 }
 296
 297 #define RST_NN(nnn, n) \
 298 OPDEF(rst_ ## nnn, 0xC7+n*8)       \
 299 {                                  \
 300   PUSH(PC);                        \
 301   PC = n*8;                        \
 302   ENTIME(11);                      \
 303 }
 304
 305 RST_NN(00, 0)
 306 #if !HIJACK_RST_08
 307 RST_NN(08, 1)
 308 #endif
 309 RST_NN(10, 2)
 310 RST_NN(18, 3)
 311 RST_NN(20, 4)
 312 RST_NN(28, 5)
 313 RST_NN(30, 6)
 314 RST_NN(38, 7)
 315
 316 #include "z80_op4x.c"