sdcc-extra/historygraphs/dhrystone-r3ka/portme.c

   1 #include <stdio.h>
   2 #include <stdint.h>
   3
   4 #define REG(addr, reg)  __sfr __at(addr) reg
   5
   6 REG(0x00, GCSR);  // global control / status register
   7 REG(0x01, RTCCR); // Real Time Clock Control Register
   8 REG(0x02, RTC0R); // Real Time Clock Data Register 0
   9 REG(0x03, RTC1R); // Real Time Clock Data Register 1
  10 REG(0x04, RTC2R); // Real Time Clock Data Register 2
  11 REG(0x05, RTC3R); // Real Time Clock Data Register 3
  12 REG(0x06, RTC4R); // Real Time Clock Data Register 4
  13 REG(0x07, RTC5R); // Real Time Clock Data Register 5
  14 REG(0x08, WDTCR); // watch-dog timer control register
  15 REG(0x09, WDTTR); // watch-dog timer test register
  16 REG(0x0F, GCDR);  // global clock double register
  17 REG(0x14, MB0CR); // Memory Bank 0 Control Register
  18 REG(0x16, MB2CR); // Memory Bank 2 Control Register
  19 REG(0x55, PCFR);  // Port C Function Register
  20 REG(0xA0, TACSR); // Timer A Control/Status Register
  21 REG(0xA9, TAT4R); // Timer A Time Constant 4 Register
  22 REG(0xC0, SADR);  // Serial Port A Data Register
  23 REG(0xC3, SASR);  // Serial Port A Status Register
  24 REG(0xC4, SACR);  // Serial Port A Control Register
  25
  26 #if __SDCC_REVISION >= 13762
  27 unsigned char __sdcc_external_startup(void)
  28 #else
  29 unsigned char _sdcc_external_startup(void)
  30 #endif
  31 {
  32         // Disable watchdog
  33         WDTTR = 0x51;
  34         WDTTR = 0x54;
  35
  36         // normal oscillator, processor and peripheral from main clock, no periodic interrupt
  37         GCSR = 0x08;
  38
  39         GCDR = 0x07; // Double clock to get more speed
  40
  41         // Configure memory wait states
  42         MB0CR = 0x88; // Flash - 1 wait state (for 45 ns Flash @ 44.2 MHz) with write-protection
  43         MB2CR = 0x85; // RAM - 1 wait states (for 55 ns RAM @ 44.2 MHz)
  44 }
  45
  46 void init(void)
  47 {
  48         PCFR = 0x40;    // Use pin PC6 as TXA
  49         TAT4R = 36 - 1; // Use divider for 38400 baud - value in register is one less than the divider used (e.g. a value of 0 will result in clock division by 1).
  50         TACSR = 0x01;   // Enable timer A
  51         SACR = 0x00;    // No interrupts, 8-bit async mode
  52 }
  53
  54 unsigned long clock(void)
  55 {
  56         unsigned long clock0, clock1;
  57         do
  58         {
  59                 RTC0R = 0;
  60                 clock0 = ((unsigned long)(RTC0R) << 0) | ((unsigned long)(RTC1R) << 8) | ((unsigned long)(RTC2R) << 16) | ((unsigned long)(RTC3R) << 24);
  61                 clock1 = ((unsigned long)(RTC0R) << 0) | ((unsigned long)(RTC1R) << 8) | ((unsigned long)(RTC2R) << 16) | ((unsigned long)(RTC3R) << 24);
  62         } while (clock0 != clock1);
  63         return(clock1);
  64 }
  65
  66 #if defined(__SDCC) && __SDCC_REVISION < 9624 // Old SDCC weirdness
  67 void putchar(char c)
  68 {
  69         while (SASR & 0x04);    // Wait for empty transmitter data register
  70         SADR = c;
  71 }
  72 #else // Standard C
  73 int putchar(int c)
  74 {
  75         while (SASR & 0x04);    // Wait for empty transmitter data register
  76         SADR = c;
  77         return c;
  78 }
  79 #endif
  80