sdcc-extra/historygraphs/whetstone-mcs51/portme.c

   1 /* Target-specific functions for making Whetstone work on the STM8
   2    Author: Philipp Klaus Krause */
   3
   4 #include <stdio.h>
   5 #include <stdint.h>
   6 #include <stdbool.h>
   7
   8 // #include <C8051F120.h> conflict with P0 and P3 from whetstone.c
   9
  10 __sfr __at(0xa2) _XPAGE;
  11 __sfr __at(0x84) SFRPAGE;
  12
  13 __sfr __at(0xe1) XBR0;
  14 __sfr __at(0xe3) XBR2;
  15 __sfr __at(0xff) WDTCN;
  16 __sfr __at(0x8a) OSCICN;
  17 __sfr __at(0xa8) IE;
  18
  19 __sfr __at(0xa4) P0MDOUT;
  20 __sfr __at(0x88) TCON;
  21 __sfr __at(0x89) TMOD;
  22 __sfr __at(0x8a) TL0;
  23 __sfr __at(0x8c) TH0;
  24 __sfr __at(0x8d) TH1;
  25 __sfr __at(0x98) SCON0;
  26 __sfr __at(0x99) SBUF0;
  27
  28 __sfr __at(0xb7) FLSCL;
  29
  30 __sfr __at(0x89) PLL0CN;
  31 __sfr __at(0x8e) PLL0MUL;
  32 __sfr __at(0x8f) PLL0FLT;
  33
  34 __sfr __at(0x97) CLKSEL;
  35
  36 volatile unsigned long int clocktime;
  37 volatile bool clockupdate;
  38
  39 void clockinc(void) __interrupt(1)
  40 {
  41         TH0 = (65536 - 8167) / 256;
  42         TL0 = (65536 - 8167) % 256;
  43         clocktime++;
  44         clockupdate = true;
  45 }
  46
  47 unsigned long int clock(void)
  48 {
  49         unsigned long int ctmp;
  50
  51         do
  52         {
  53                 clockupdate = false;
  54                 ctmp = clocktime;
  55         } while (clockupdate);
  56
  57         return(ctmp);
  58 }
  59
  60 #if __SDCC_REVISION >= 13762
  61 unsigned char __sdcc_external_startup(void)
  62 #else
  63 unsigned char _sdcc_external_startup(void)
  64 #endif
  65 {
  66         // Disable watchdog timer
  67         WDTCN = 0xde;
  68         WDTCN = 0xad;
  69
  70         return 0; // perform normal initialization
  71 }
  72
  73 void init(void)
  74 {
  75         unsigned char i;
  76
  77         // Initialize I/O pins
  78         SFRPAGE = 0xf;
  79         XBR0 = 0x04;                            // UART0 on P0.0 and P0.1
  80         P0MDOUT = 0x01;                         // Set port P0.0 (Uart tx) to push-pull
  81         XBR2 = 0x40;                            // Enable crossbar
  82
  83         OSCICN = 0xc3;                          // Run internal oscillator at full 24.5 Mhz
  84
  85         // Use PLL to get SYSCLK to 98 Mhz for higher benchmark scores
  86         SFRPAGE = 0x0;
  87         FLSCL = 0xb0;
  88         SFRPAGE = 0xf;
  89         PLL0CN = 0x01;
  90         PLL0FLT = 0x01;
  91         PLL0MUL = 0x04;
  92         for (i = 0; i < 31; i++) // Wait 5 µs
  93         {
  94           __asm
  95           nop
  96           nop
  97           nop
  98           nop
  99           __endasm;
 100         }
 101         PLL0CN = 0x03;
 102         while (!(PLL0CN & 0x10));
 103         CLKSEL = 0x02;
 104
 105         // Configure timer for 24.5 Mhz SYSCLK
 106         // 1000 ticks per second
 107         SFRPAGE = 0x0;
 108         TH0 = (65536 - 8167) / 256;
 109         TL0 = (65536 - 8167) % 256;
 110         TMOD = 0x01;
 111         IE |= 0x82;
 112         TCON |= 0x10; // Start timer
 113
 114         // Configure UART for 4800 baud, 8 data bits, 1 stop bit.
 115         SFRPAGE = 0x0;
 116         TMOD = 0x21;
 117         SCON0 = 0x40;
 118         TH1 = 203;
 119         TCON |= 0x40;
 120         SCON0 |= 0x02;                          // Tell putchar() the UART is ready to send.
 121 }
 122
 123 #if __SDCC_REVISION >= 9624
 124 int putchar(int c)
 125 {
 126         while(!(SCON0 & 0x02));
 127         SCON0 &= ~0x02;
 128         SBUF0 = c;
 129         return (c);
 130 }
 131 #else
 132 void putchar(char c)
 133 {
 134         while(!(SCON0 & 0x02));
 135         SCON0 &= ~0x02;
 136         SBUF0 = c;
 137 }
 138 #endif
 139