sdcc/device/include/mcs51/8051.h

   1 /*-------------------------------------------------------------------------
   2    8051.h: Register Declarations for the Intel 8051 Processor
   3
   4    Copyright (C) 2000, Bela Torok / bela.torok@kssg.ch
   5
   6    This library is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published by the
   8    Free Software Foundation; either version 2, or (at your option) any
   9    later version.
  10
  11    This library is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this library; see the file COPYING. If not, write to the
  18    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  19    MA 02110-1301, USA.
  20
  21    As a special exception, if you link this library with other files,
  22    some of which are compiled with SDCC, to produce an executable,
  23    this library does not by itself cause the resulting executable to
  24    be covered by the GNU General Public License. This exception does
  25    not however invalidate any other reasons why the executable file
  26    might be covered by the GNU General Public License.
  27 -------------------------------------------------------------------------*/
  28
  29 #ifndef REG8051_H
  30 #define REG8051_H
  31
  32 /*  BYTE Register  */
  33 __sfr __at (0x80) P0   ;
  34 __sfr __at (0x81) SP   ;
  35 __sfr __at (0x82) DPL  ;
  36 __sfr __at (0x83) DPH  ;
  37 __sfr __at (0x87) PCON ;
  38 __sfr __at (0x88) TCON ;
  39 __sfr __at (0x89) TMOD ;
  40 __sfr __at (0x8A) TL0  ;
  41 __sfr __at (0x8B) TL1  ;
  42 __sfr __at (0x8C) TH0  ;
  43 __sfr __at (0x8D) TH1  ;
  44 __sfr __at (0x90) P1   ;
  45 __sfr __at (0x98) SCON ;
  46 __sfr __at (0x99) SBUF ;
  47 __sfr __at (0xA0) P2   ;
  48 __sfr __at (0xA8) IE   ;
  49 __sfr __at (0xB0) P3   ;
  50 __sfr __at (0xB8) IP   ;
  51 __sfr __at (0xD0) PSW  ;
  52 __sfr __at (0xE0) ACC  ;
  53 __sfr __at (0xF0) B    ;
  54
  55
  56 /*  BIT Register  */
  57 /* P0 */
  58 __sbit __at (0x80) P0_0 ;
  59 __sbit __at (0x81) P0_1 ;
  60 __sbit __at (0x82) P0_2 ;
  61 __sbit __at (0x83) P0_3 ;
  62 __sbit __at (0x84) P0_4 ;
  63 __sbit __at (0x85) P0_5 ;
  64 __sbit __at (0x86) P0_6 ;
  65 __sbit __at (0x87) P0_7 ;
  66
  67 /*  TCON  */
  68 __sbit __at (0x88) IT0  ;
  69 __sbit __at (0x89) IE0  ;
  70 __sbit __at (0x8A) IT1  ;
  71 __sbit __at (0x8B) IE1  ;
  72 __sbit __at (0x8C) TR0  ;
  73 __sbit __at (0x8D) TF0  ;
  74 __sbit __at (0x8E) TR1  ;
  75 __sbit __at (0x8F) TF1  ;
  76
  77 /* P1 */
  78 __sbit __at (0x90) P1_0 ;
  79 __sbit __at (0x91) P1_1 ;
  80 __sbit __at (0x92) P1_2 ;
  81 __sbit __at (0x93) P1_3 ;
  82 __sbit __at (0x94) P1_4 ;
  83 __sbit __at (0x95) P1_5 ;
  84 __sbit __at (0x96) P1_6 ;
  85 __sbit __at (0x97) P1_7 ;
  86
  87 /*  SCON  */
  88 __sbit __at (0x98) RI   ;
  89 __sbit __at (0x99) TI   ;
  90 __sbit __at (0x9A) RB8  ;
  91 __sbit __at (0x9B) TB8  ;
  92 __sbit __at (0x9C) REN  ;
  93 __sbit __at (0x9D) SM2  ;
  94 __sbit __at (0x9E) SM1  ;
  95 __sbit __at (0x9F) SM0  ;
  96
  97 /* P2 */
  98 __sbit __at (0xA0) P2_0 ;
  99 __sbit __at (0xA1) P2_1 ;
 100 __sbit __at (0xA2) P2_2 ;
 101 __sbit __at (0xA3) P2_3 ;
 102 __sbit __at (0xA4) P2_4 ;
 103 __sbit __at (0xA5) P2_5 ;
 104 __sbit __at (0xA6) P2_6 ;
 105 __sbit __at (0xA7) P2_7 ;
 106
 107 /*  IE   */
 108 __sbit __at (0xA8) EX0  ;
 109 __sbit __at (0xA9) ET0  ;
 110 __sbit __at (0xAA) EX1  ;
 111 __sbit __at (0xAB) ET1  ;
 112 __sbit __at (0xAC) ES   ;
 113 __sbit __at (0xAF) EA   ;
 114
 115 /*  P3  */
 116 __sbit __at (0xB0) P3_0 ;
 117 __sbit __at (0xB1) P3_1 ;
 118 __sbit __at (0xB2) P3_2 ;
 119 __sbit __at (0xB3) P3_3 ;
 120 __sbit __at (0xB4) P3_4 ;
 121 __sbit __at (0xB5) P3_5 ;
 122 __sbit __at (0xB6) P3_6 ;
 123 __sbit __at (0xB7) P3_7 ;
 124
 125 __sbit __at (0xB0) RXD  ;
 126 __sbit __at (0xB1) TXD  ;
 127 __sbit __at (0xB2) INT0 ;
 128 __sbit __at (0xB3) INT1 ;
 129 __sbit __at (0xB4) T0   ;
 130 __sbit __at (0xB5) T1   ;
 131 __sbit __at (0xB6) WR   ;
 132 __sbit __at (0xB7) RD   ;
 133
 134 /*  IP   */
 135 __sbit __at (0xB8) PX0  ;
 136 __sbit __at (0xB9) PT0  ;
 137 __sbit __at (0xBA) PX1  ;
 138 __sbit __at (0xBB) PT1  ;
 139 __sbit __at (0xBC) PS   ;
 140
 141 /*  PSW   */
 142 __sbit __at (0xD0) P    ;
 143 __sbit __at (0xD1) F1   ;
 144 __sbit __at (0xD2) OV   ;
 145 __sbit __at (0xD3) RS0  ;
 146 __sbit __at (0xD4) RS1  ;
 147 __sbit __at (0xD5) F0   ;
 148 __sbit __at (0xD6) AC   ;
 149 __sbit __at (0xD7) CY   ;
 150
 151 /* BIT definitions for bits that are not directly accessible */
 152 /* PCON bits */
 153 #define IDL             0x01
 154 #define PD              0x02
 155 #define GF0             0x04
 156 #define GF1             0x08
 157 #define SMOD            0x80
 158
 159 /* TMOD bits */
 160 #define T0_M0           0x01
 161 #define T0_M1           0x02
 162 #define T0_CT           0x04
 163 #define T0_GATE         0x08
 164 #define T1_M0           0x10
 165 #define T1_M1           0x20
 166 #define T1_CT           0x40
 167 #define T1_GATE         0x80
 168
 169 #define T0_MASK         0x0F
 170 #define T1_MASK         0xF0
 171
 172 /* Interrupt numbers: address = (number * 8) + 3 */
 173 #define IE0_VECTOR      0       /* 0x03 external interrupt 0 */
 174 #define TF0_VECTOR      1       /* 0x0b timer 0 */
 175 #define IE1_VECTOR      2       /* 0x13 external interrupt 1 */
 176 #define TF1_VECTOR      3       /* 0x1b timer 1 */
 177 #define SI0_VECTOR      4       /* 0x23 serial port 0 */
 178
 179 #endif