sdcc/device/include/mcs51/ADuC84x.h

   1 /*-------------------------------------------------------------------------
   2    ADuC84x.h: Register Declarations for Analog Devices
   3    ADuC841/ADuC842/ADuC843 (Based on datasheet Rev 0, 11/2003 )
   4
   5    Copyright (C) 2007, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef REG_ADUC84X_H
  31 #define REG_ADUC84X_H
  32
  33 #include <compiler.h>
  34
  35 SFR(CFG841, 0xAF); // ADuC841 Configuration SFR.
  36 SFR(CFG842, 0xAF); // ADuC842/ADuC843 Configuration SFR.
  37         //For the two SFRs above these are the bits.  Warning: some are different for
  38         //the ADuC841 and ADuC842/ADuC843.  Check the datasheet!
  39     #define EPM2   0x10 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 2.
  40     #define EPM1   0x08 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 1.
  41     #define EPM0   0x04 // Flash/EE Controller and PWM Clock Frequency Configuration Bit 0.
  42     #define EXSP   0x80 // Extended SP Enable.
  43     #define PWPO   0x40 // PWM Pin Out Selection.
  44     #define DBUF   0x20 // DAC Output Buffer.
  45     #define EXTCLK 0x10 // Set by the user to 1 to select an external clock input on P3.4.
  46     #define MSPI   0x02 // Set to 1 by the user to move the SPI functionality of.
  47     #define XRAMEN 0x01 // XRAM Enable Bit.
  48
  49 SFR(SP,    0x81); // Stack Pointer.
  50 SFR(SPH,   0xB7); // Stack pointer high.
  51
  52 SFR(DPL,   0x82); // Data Pointer Low.
  53 SFR(DPH,   0x83); // Data Pointer High.
  54 SFR(DPP,   0x84); // Data Pointer Page Byte.
  55 SFR(DPCON, 0xA7); // Data Pointer Control SFR.
  56
  57 SFR(PCON, 0x87); // Power Control.
  58    #define SMOD   0x80 //Double UART Baud Rate.
  59    #define SERIPD 0x40 //I2C/SPI Power-Down Interrupt Enable.
  60    #define INT0PD 0x20 //INT0 Power-Down Interrupt Enable.
  61    #define ALEOFF 0x10 //Disable ALE Output.
  62    #define GF1    0x08 //General-Purpose Flag Bit.
  63    #define GF0    0x04 //General-Purpose Flag Bit.
  64    #define PD     0x02 //Power-Down Mode Enable.
  65    #define IDL    0x01 //Idle Mode Enable.
  66
  67 SFR(TCON, 0x88); // Timer/Counter Control.
  68     SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
  69     SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
  70     SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
  71     SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
  72     SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
  73     SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
  74     SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
  75     SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
  76
  77 SFR(TMOD, 0x89); // Timer/Counter Mode Control.
  78    #define GATE1 0x80 // External enable for timer 1.
  79    #define C_T1  0x40 // Timer or counter select for timer 1.
  80    #define M1_1  0x20 // Operation mode bit 1 for timer 1.
  81    #define M0_1  0x10 // Operation mode bit 0 for timer 1.
  82    #define GATE0 0x08 // External enable for timer 0.
  83    #define C_T0  0x04 // Timer or counter select for timer 0.
  84    #define M1_0  0x02 // Operation mode bit 1 for timer 0.
  85    #define M0_0  0x01 // Operation mode bit 0 for timer 0.
  86
  87 SFR(TL0, 0x8A); // Timer 0 LSB.
  88 SFR(TL1, 0x8B); // Timer 1 LSB.
  89 SFR(TH0, 0x8C); // Timer 0 MSB.
  90 SFR(TH1, 0x8D); // Timer 1 MSB.
  91
  92 SFR(P0, 0x80); // Port 0
  93     SBIT(P0_0, 0x80, 0); // Port 0 bit 0.
  94     SBIT(P0_1, 0x80, 1); // Port 0 bit 1.
  95     SBIT(P0_2, 0x80, 2); // Port 0 bit 2.
  96     SBIT(P0_3, 0x80, 3); // Port 0 bit 3.
  97     SBIT(P0_4, 0x80, 4); // Port 0 bit 4.
  98     SBIT(P0_5, 0x80, 5); // Port 0 bit 5.
  99     SBIT(P0_6, 0x80, 6); // Port 0 bit 6.
 100     SBIT(P0_7, 0x80, 7); // Port 0 bit 7.
 101
 102 SFR(P1, 0x90); // Port 1
 103     SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
 104     SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
 105     SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
 106     SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
 107     SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
 108     SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
 109     SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
 110     SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
 111     // Alternate names
 112     SBIT(T2EX, 0x90, 1); //Capture/reload trigger for Counter 2.
 113     SBIT(T2,   0x90, 0); //Input to Timer/Counter 2.
 114
 115 SFR(P2, 0xA0); // Port 2
 116    SBIT(P2_0, 0xA0, 0); // Port 2 bit 0.
 117    SBIT(P2_1, 0xA0, 1); // Port 2 bit 1.
 118    SBIT(P2_2, 0xA0, 2); // Port 2 bit 2.
 119    SBIT(P2_3, 0xA0, 3); // Port 2 bit 3.
 120    SBIT(P2_4, 0xA0, 4); // Port 2 bit 4.
 121    SBIT(P2_5, 0xA0, 5); // Port 2 bit 5.
 122    SBIT(P2_6, 0xA0, 6); // Port 2 bit 6.
 123    SBIT(P2_7, 0xA0, 7); // Port 2 bit 7.
 124
 125 SFR(P3, 0xB0); // Port 3
 126    SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
 127    SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
 128    SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
 129    SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
 130    SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
 131    SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
 132    SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
 133    SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
 134    // Alternate names.
 135    SBIT(RXD,  0xB0, 0);
 136    SBIT(TXD,  0xB0, 1);
 137    SBIT(INT0, 0xB0, 2);
 138    SBIT(INT1, 0xB0, 3);
 139    SBIT(T0,   0xB0, 4);
 140    SBIT(T1,   0xB0, 5);
 141    SBIT(WR,   0xB0, 6);
 142    SBIT(RD,   0xB0, 7);
 143
 144 SFR(I2CADD,  0x9B); // I2C Address Register 1.
 145 SFR(I2CADD1, 0x91); // I2C Address Register 2.
 146 SFR(I2CADD2, 0x92); // I2C Address Register 3.
 147 SFR(I2CADD3, 0x93); // I2C Address Register 4.
 148 SFR(I2CDAT,  0x9A); // I2C Data Register.
 149
 150 SFR(SCON, 0x98); // Serial Port Control.
 151    SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
 152    SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
 153    SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
 154    SBIT(REN, 0x98, 4); // Enables serial reception.
 155    SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
 156    SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
 157    SBIT(TI,  0x98, 1); // Transmit interrupt flag.
 158    SBIT(RI,  0x98, 0); // Receive interrupt flag.
 159
 160 SFR(SBUF, 0x99); // Serial Data Buffer.
 161
 162 //For these two, you may want to check page 68 of the datasheet...
 163 SFR(T3FD,  0x9D);       // Fractional divider ratio.
 164 SFR(T3CON, 0x9E);       // T3CON is the baud rate control SFR, allowing Timer 3 to be
 165                         // used to set up the UART baud rate, and setting up the binary
 166                         // divider (DIV).
 167 #define T3BAUDEN 0x80   // T3 UART BAUD Enable.
 168 #define DIV2 0x04       // Binary Divider Factor bit 3.
 169 #define DIV1 0x02       // Binary Divider Factor bit 2.
 170 #define DIV0 0x01       // Binary Divider Factor bit 1.
 171
 172 SFR(TIMECON, 0xA1); // TIC Control Register.
 173     #define TFH  0x40 // Twenty-Four Hour Select Bit.
 174     #define ITS1 0x20 // Interval Timebase Selection Bit 1.
 175     #define ITS0 0x10 // Interval Timebase Selection Bit 1.
 176     #define STI  0x08 // Single Time Interval Bit.
 177     #define TII  0x04 // TIC Interrupt Bit.
 178     #define TIEN 0x02 // Time Interval Enable Bit.
 179     #define TCEN 0x01 // Time Clock Enable Bit.
 180
 181 SFR(HTHSEC, 0xA2); // Hundredths Seconds Time Register.
 182 SFR(SEC,    0xA3); // Seconds Time Register.
 183 SFR(MIN,    0xA4); // Minutes Time Register.
 184 SFR(HOUR,   0xA5); // Hours Time Register.
 185 SFR(INTVAL, 0xA6); // User Time Interval Select Register.
 186
 187 SFR(IE,  0xA8); // Interrupt Enable.
 188    SBIT(EA,   0xA8, 7); // Global Interrupt Enable.
 189    SBIT(EADC, 0xA8, 6); // ADC Interrupt Enable.
 190    SBIT(ET2,  0xA8, 5); // Timer 2 Interrupt Enable.
 191    SBIT(ES,   0xA8, 4); // Serial Interrupt Enable.
 192    SBIT(ET1,  0xA8, 3); // Timer 1 Interrupt Enable.
 193    SBIT(EX1,  0xA8, 2); // External 1 Interrupt Enable.
 194    SBIT(ET0,  0xA8, 1); // Timer 0 Interrupt Enable.
 195    SBIT(EX0,  0xA8, 0); // External 0 Interrupt Enable.
 196
 197 SFR(IEIP2, 0xA9); // Secondary Interrupt Enable Register
 198     #define PTI   0x40 // Priority for time interval interrupt.
 199     #define PPSM  0x20 // Priority for power supply monitor interrupt.
 200     #define PSI2  0x10 // Priority for SPI/I2C interrupt. Same name as bit in IP???
 201     #define ETI   0x04 // Enable time interval counter interrupts.
 202     #define EPSMI 0x02 // Enable power supply monitor interrupts.
 203     #define ESI   0x01 // Enable SPI or I2C serial port interrupts.
 204
 205 SFR(PWMCON, 0xAE); //PWM control.
 206     #define SNGL  0x80 // Turns off PMW output at P2.6 or P3.4.
 207     #define MD2   0x40 // PWM Mode Bit 2.
 208     #define MD1   0x20 // PWM Mode Bit 2.
 209     #define MD0   0x10 // PWM Mode Bit 2.
 210     #define CDIV1 0x08 // PWM Clock Divider bit 1.
 211     #define CDIV0 0x04 // PWM Clock Divider bit 1.
 212     #define CSEL1 0x02 // PWM Clock Select bit 1. (Typo in datasheet???)
 213     #define CSEL0 0x01 // PWM Clock Select bit 0.
 214
 215 SFR(PWM0L, 0xB1); // PWM 0 duty cycle low.
 216 SFR(PWM0H, 0xB2); // PWM 0 duty cycle high.
 217 SFR(PWM1L, 0xB3); // PWM 1 duty cycle low.
 218 SFR(PWM1H, 0xB4); // PWM 1 duty cycle high.
 219
 220 SFR(IP,  0xB8); // Interrupt Priority Reg.
 221    SBIT(PSI,  0xB8, 7); // Priority for SPI/I2C interrupt.
 222    SBIT(PADC, 0xB8, 6); // ADC interrupt priority bit.
 223    SBIT(PT2,  0xB8, 5); // Timer 2 interrupt priority bit.
 224    SBIT(PS,   0xB8, 4); // Serial Port interrupt priority bit.
 225    SBIT(PT1,  0xB8, 3); // Timer 1 interrupt priority bit.
 226    SBIT(PX1,  0xB8, 2); // External interrupt 1 priority bit.
 227    SBIT(PT0,  0xB8, 1); // Timer 0 interrupt priority bit.
 228    SBIT(PX0,  0xB8, 0); // External interrupt 0 priority bit.
 229
 230 SFR(ECON,   0xB9); // Flash/EE Memory Control SFR.
 231 SFR(EDATA1, 0xBC); // EE page data byte 1.
 232 SFR(EDATA2, 0xBD); // EE page data byte 2.
 233 SFR(EDATA3, 0xBE); // EE page data byte 3.
 234 SFR(EDATA4, 0xBF); // EE page data byte 4.
 235 SFR(EADRL,  0xC6); // EE address low.
 236 SFR(EADRH,  0xC7); // EE address high.
 237
 238 SFR(WDCON, 0xC0); //Watchdog Timer Control Register.
 239     SBIT(PRE3, 0xc0, 7); // Timeout period bit 4.
 240     SBIT(PRE2, 0xc0, 6); // Timeout period bit 3.
 241     SBIT(PRE1, 0xc0, 5); // Timeout period bit 2.
 242     SBIT(PRE0, 0xc0, 4); // Timeout period bit 1.
 243     SBIT(WDIR, 0xc0, 3); // Watchdog Interrupt Response Enable Bit.
 244     SBIT(WDS,  0xc0, 2); // Watchdog Status Bit.
 245     SBIT(WDE,  0xc0, 1); // Watchdog Enable Bit.
 246     SBIT(WDWR, 0xc0, 0); // Watchdog Write Enable Bit.
 247
 248 SFR(CHIPID, 0xC2); // System Self-Identification? WARNING: No description in the datasheet.
 249
 250 SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
 251    SBIT(TF2,   0xC8, 7); // Timer 2 overflow flag.
 252    SBIT(EXF2,  0xC8, 6); // Timer 2 external flag.
 253    SBIT(RCLK,  0xC8, 5); // Receive clock flag.
 254    SBIT(TCLK,  0xC8, 4); // Transmit clock flag.
 255    SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
 256    SBIT(TR2,   0xC8, 2); // Start/stop control for timer 2.
 257    SBIT(CNT2,  0xC8, 1); // Timer or coutner select.
 258    SBIT(CAP2,  0xC8, 0); // Capture/reload flag.
 259
 260 SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
 261 SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
 262 SFR(TL2,    0xCC); // Timer 2 LSB.
 263 SFR(TH2,    0xCD); // Timer 2 MSB.
 264
 265 SFR(PSW, 0xD0); // Program Status Word.
 266    SBIT(CY,  0xD0, 7); // Carry Flag.
 267    SBIT(AC,  0xD0, 6); // Auxiliary Carry Flag.
 268    SBIT(F0,  0xD0, 5); // User-Defined Flag.
 269    SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
 270    SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
 271    SBIT(OV,  0xD0, 2); // Overflow Flag.
 272    SBIT(F1,  0xD0, 1); // User-Defined Flag.
 273    SBIT(P,   0xD0, 0); // Parity Flag.
 274
 275 SFR(DMAL,   0xD2); // DMA mode address pointer low.
 276 SFR(DMAH,   0xD3); // DMA mode address pointer high.
 277 SFR(DMAP,   0xD4); // DMA mode address pointer page. (?)
 278 SFR(PLLCON, 0xD7); // PLL Control Register.
 279
 280 SFR(PSMCON, 0xDF); // Power supply monitor.
 281     #define CMPD  0x40 // DVDD Comparator Bit.
 282     #define PSMI  0x20 // Power Supply Monitor Interrupt Bit.
 283     #define TPD1  0x10 // DVDD Trip Point Selection Bit 2.
 284     #define TPD0  0x08 // DVDD Trip Point Selection Bit 1.
 285     #define PSMEN 0x01 // Power Supply Monitor Enable Bit.
 286
 287 SFR(ACC, 0xE0); // Accumulator
 288    SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
 289    SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
 290    SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
 291    SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
 292    SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
 293    SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
 294    SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
 295    SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
 296
 297 SFR(I2CCON, 0xE8); // I2C Control Register
 298     // Master mode
 299     SBIT(MDO,    0xE8, 7); // I2C Software Master Data Output Bit.
 300     SBIT(MDE,    0xE8, 6); // I2C Software Master Data Output Enable Bit.
 301     SBIT(MCO,    0xE8, 5); // I2C Software Master Clock Output Bit.
 302     SBIT(MDI,    0xE8, 4); // I2C Software Master Data Input Bit.
 303     // Slave mode
 304     SBIT(I2CSI,  0xE8, 7); // I2C Stop Interrupt Enable Bit.
 305     SBIT(I2CGC,  0xE8, 6); // I2C General Call Status Bit.
 306     SBIT(I2CID1, 0xE8, 5); // I2C Interrupt Decode Bit 2.
 307     SBIT(I2CID0, 0xE8, 4); // I2C Interrupt Decode Bit 1.
 308     SBIT(I2CM,   0xE8, 3); // I2C Master/Slave Mode Bit.
 309     SBIT(I2CRS,  0xE8, 2); // I2C Reset Bit.
 310     SBIT(I2CTX,  0xE8, 1); // I2C Direction Transfer Bit.
 311     SBIT(I2CI,   0xE8, 0); // I2C Interrupt Bit.
 312
 313 SFR(B,   0xF0); // B Register
 314    SBIT(B_0, 0xF0, 0); // Register B bit 0.
 315    SBIT(B_1, 0xF0, 1); // Register B bit 1.
 316    SBIT(B_2, 0xF0, 2); // Register B bit 2.
 317    SBIT(B_3, 0xF0, 3); // Register B bit 3.
 318    SBIT(B_4, 0xF0, 4); // Register B bit 4.
 319    SBIT(B_5, 0xF0, 5); // Register B bit 5.
 320    SBIT(B_6, 0xF0, 6); // Register B bit 6.
 321    SBIT(B_7, 0xF0, 7); // Register B bit 7.
 322
 323 SFR(ADCCON1,  0xEF); //ADC Control SFR 1
 324         //WARNING: bit 7 is named MD1 in the datasheet, but that name is already used.
 325     #define MD      0x80 // The mode bit selects the active operating mode of the ADC.
 326     #define EXT_REF 0x40 // Set by the user to select an external reference.
 327     #define CK1     0x20 // The ADC clock divide bit 1.
 328     #define CK0     0x10 // The ADC clock divide bit 0.
 329     #define AQ1     0x08 // ADC acquisition select bit 1.
 330     #define AQ0     0x04 // ADC acquisition select bit 0.
 331     #define T2C     0x02 // The Timer 2 conversion bit.
 332     #define EXC     0x01 // The external trigger enable bit.
 333
 334 SFR(ADCCON2,  0xD8); // ADC Control SFR 2.
 335     SBIT(ADCI,  0xD8, 7); // ADC Interrupt Bit.
 336     SBIT(DMA,   0xD8, 6); // DMA Mode Enable Bit.
 337     SBIT(CCONV, 0xD8, 5); // Continuous Conversion Bit.
 338     SBIT(SCONV, 0xD8, 4); // Single Conversion Bit.
 339     SBIT(CS3,   0xD8, 3); // Channel Selection Bit 4.
 340     SBIT(CS2,   0xD8, 2); // Channel Selection Bit 3.
 341     SBIT(CS1,   0xD8, 1); // Channel Selection Bit 2.
 342     SBIT(CS0,   0xD8, 0); // Channel Selection Bit 1.
 343
 344 SFR(ADCCON3,  0xF5); //ADC Control SFR 3
 345     #define BUSY    0x80 // ADC Busy Status Bit.
 346     #define AVGS1   0x20 // Number of Average Selection Bit 2.
 347     #define AVGS0   0x10 // Number of Average Selection Bit 1.
 348     #define TYPICAL 0x02 // Calibration Type Select Bit.
 349     #define SCAL    0x01 // Start Calibration Cycle Bit.
 350
 351 SFR(ADCDATAL, 0xD9); // ADC Result byte low.
 352 SFR(ADCDATAH, 0xDA); // ADC Result byte high.  WARNING: bits 4 to 7 are the ADC channel!
 353 SFR(ADCOFSL,  0xF1); // Offset calibration coefficient byte (low).
 354 SFR(ADCOFSH,  0xF2); // Offset calibration coefficient byte (high).
 355 SFR(ADCGAINL, 0xF3); // Gain calibration coefficient byte (low).
 356 SFR(ADCGAINH, 0xF4); // Gain calibration coefficient byte (high).
 357
 358 SFR(SPIDAT, 0xF7); // SPI Data Register.
 359
 360 SFR(SPICON, 0xF8); // SPI Control Register.
 361     SBIT(ISPI, 0xF8, 7); // SPI Interrupt Bit.
 362     SBIT(WCOL, 0xF8, 6); // Write Collision Error Bit.
 363     SBIT(SPE,  0xF8, 5); // SPI Interface Enable Bit.
 364     SBIT(SPIM, 0xF8, 4); // SPI Master/Slave Mode Select Bit.
 365     SBIT(CPOL, 0xF8, 3); // Clock Polarity Select Bit.
 366     SBIT(CPHA, 0xF8, 2); // Clock Phase Select Bit.
 367     SBIT(SPR1, 0xF8, 1); // SPI Bit Rate Select Bit 2.
 368     SBIT(SPR0, 0xF8, 0); // SPI Bit Rate Select Bit 1.
 369
 370 SFR(DAC0L,  0xF9); // DAC0 Data Low Byte.
 371 SFR(DAC0H,  0xFA); // DAC0 Data High Byte.
 372 SFR(DAC1L,  0xFB); // DAC1 Data Low Byte.
 373 SFR(DAC1H,  0xFC); // DAC1 Data High Byte.
 374 SFR(DACCON, 0xFD); // DAC Control Register.
 375     #define MODE 0x80 // 8/12 bit selection.
 376     #define RNG1 0x40 // DAC1 Range Select Bit.
 377     #define RNG0 0x20 // DAC0 Range Select Bit.
 378     #define CLR1 0x10 // DAC1 Clear Bit.
 379     #define CLR0 0x08 // DAC0 Clear Bit.
 380     #define SYNC 0x04 // DAC0/1 Update Synchronization Bit.
 381     #define PD1  0x02 // DAC1 Power-Down Bit.
 382     #define PD0  0x01 // DAC0 Power-Down Bit.
 383
 384 #endif //REG_ADUC84X_H