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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / C8051F020.h
blob38bc5d35034b1938301143a76a19e3627b913e93
1 /*-------------------------------------------------------------------------
2 C8051F020.h - Register Declarations for the Cygnal/SiLabs C8051F02x
3 Processor Range
4
5 Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 #ifndef C8051F020_H
31 #define C8051F020_H
32
33
34 /* BYTE Registers */
35 __sfr __at (0x80) P0 ; /* PORT 0 */
36 __sfr __at (0x81) SP ; /* STACK POINTER */
37 __sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
38 __sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
39 __sfr __at (0x84) P4 ; /* PORT 4 */
40 __sfr __at (0x85) P5 ; /* PORT 5 */
41 __sfr __at (0x86) P6 ; /* PORT 6 */
42 __sfr __at (0x87) PCON ; /* POWER CONTROL */
43 __sfr __at (0x88) TCON ; /* TIMER CONTROL */
44 __sfr __at (0x89) TMOD ; /* TIMER MODE */
45 __sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
46 __sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
47 __sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
48 __sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
49 __sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
50 __sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
51 __sfr __at (0x90) P1 ; /* PORT 1 */
52 __sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
53 __sfr __at (0x92) TMR3RLL ; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
54 __sfr __at (0x93) TMR3RLH ; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
55 __sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
56 __sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
57 __sfr __at (0x96) P7 ; /* PORT 7 */
58 __sfr __at (0x98) SCON ; /* UART0 CONTROL */
59 __sfr __at (0x98) SCON0 ; /* UART0 CONTROL */
60 __sfr __at (0x99) SBUF ; /* UART0 BUFFER */
61 __sfr __at (0x99) SBUF0 ; /* UART0 BUFFER */
62 __sfr __at (0x9A) SPI0CFG ; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
63 __sfr __at (0x9B) SPI0DAT ; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
64 __sfr __at (0x9C) ADC1 ; /* ADC 1 DATA */
65 __sfr __at (0x9D) SPI0CKR ; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
66 __sfr __at (0x9E) CPT0CN ; /* COMPARATOR 0 CONTROL */
67 __sfr __at (0x9F) CPT1CN ; /* COMPARATOR 1 CONTROL */
68 __sfr __at (0xA0) P2 ; /* PORT 2 */
69 __sfr __at (0xA1) EMI0TC ; /* External Memory Timing Control */
70 __sfr __at (0xA3) EMI0CF ; /* EMIF CONFIGURATION */
71 __sfr __at (0xA4) PRT0CF ; /* PORT 0 CONFIGURATION */
72 __sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
73 __sfr __at (0xA5) PRT1CF ; /* PORT 1 CONFIGURATION */
74 __sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
75 __sfr __at (0xA6) PRT2CF ; /* PORT 2 CONFIGURATION */
76 __sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
77 __sfr __at (0xA7) PRT3CF ; /* PORT 3 CONFIGURATION */
78 __sfr __at (0xA7) P3MDOUT ; /* PORT 3 OUTPUT MODE CONFIGURATION */
79 __sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
80 __sfr __at (0xA9) SADDR0 ; /* UART0 Slave Address */
81 __sfr __at (0xAA) ADC1CN ; /* ADC 1 CONTROL */
82 __sfr __at (0xAB) ADC1CF ; /* ADC 1 CONFIGURATION */
83 __sfr __at (0xAC) AMX1SL ; /* ADC 1 MUX CHANNEL SELECTION */
84 __sfr __at (0xAD) P3IF ; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
85 __sfr __at (0xAE) SADEN1 ; /* UART1 Slave Address Enable */
86 __sfr __at (0xAF) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
87 __sfr __at (0xAF) _XPAGE ; /* XDATA/PDATA PAGE */
88 __sfr __at (0xB0) P3 ; /* PORT 3 */
89 __sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
90 __sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
91 __sfr __at (0xB5) P74OUT ; /* PORT 4 THROUGH 7 OUTPUT MODE CONFIGURATION */
92 __sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
93 __sfr __at (0xB7) FLACL ; /* FLASH ACESS LIMIT */
94 __sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
95 __sfr __at (0xB9) SADEN0 ; /* UART0 Slave Address Enable */
96 __sfr __at (0xBA) AMX0CF ; /* ADC 0 MUX CONFIGURATION */
97 __sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
98 __sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
99 __sfr __at (0xBD) P1MDIN ; /* PORT 1 Input Mode */
100 __sfr __at (0xBE) ADC0L ; /* ADC 0 DATA - LOW BYTE */
101 __sfr __at (0xBF) ADC0H ; /* ADC 0 DATA - HIGH BYTE */
102 __sfr __at (0xC0) SMB0CN ; /* SMBUS 0 CONTROL */
103 __sfr __at (0xC1) SMB0STA ; /* SMBUS 0 STATUS */
104 __sfr __at (0xC2) SMB0DAT ; /* SMBUS 0 DATA */
105 __sfr __at (0xC3) SMB0ADR ; /* SMBUS 0 SLAVE ADDRESS */
106 __sfr __at (0xC4) ADC0GTL ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
107 __sfr __at (0xC5) ADC0GTH ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
108 __sfr __at (0xC6) ADC0LTL ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
109 __sfr __at (0xC7) ADC0LTH ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
110 __sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
111 __sfr __at (0xC9) T4CON ; /* TIMER 4 CONTROL */
112 __sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
113 __sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
114 __sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
115 __sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
116 __sfr __at (0xCF) SMB0CR ; /* SMBUS 0 CLOCK RATE */
117 __sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
118 __sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
119 __sfr __at (0xD2) DAC0L ; /* DAC 0 REGISTER - LOW BYTE */
120 __sfr __at (0xD3) DAC0H ; /* DAC 0 REGISTER - HIGH BYTE */
121 __sfr __at (0xD4) DAC0CN ; /* DAC 0 CONTROL */
122 __sfr __at (0xD5) DAC1L ; /* DAC 1 REGISTER - LOW BYTE */
123 __sfr __at (0xD6) DAC1H ; /* DAC 1 REGISTER - HIGH BYTE */
124 __sfr __at (0xD7) DAC1CN ; /* DAC 1 CONTROL */
125 __sfr __at (0xD8) PCA0CN ; /* PCA 0 COUNTER CONTROL */
126 __sfr __at (0xD9) PCA0MD ; /* PCA 0 COUNTER MODE */
127 __sfr __at (0xDA) PCA0CPM0 ; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
128 __sfr __at (0xDB) PCA0CPM1 ; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
129 __sfr __at (0xDC) PCA0CPM2 ; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
130 __sfr __at (0xDD) PCA0CPM3 ; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
131 __sfr __at (0xDE) PCA0CPM4 ; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
132 __sfr __at (0xE0) ACC ; /* ACCUMULATOR */
133 __sfr __at (0xE1) XBR0 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
134 __sfr __at (0xE2) XBR1 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
135 __sfr __at (0xE3) XBR2 ; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
136 __sfr __at (0xE4) RCAP4L ; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
137 __sfr __at (0xE5) RCAP4H ; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
138 __sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
139 __sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
140 __sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
141 __sfr __at (0xE9) PCA0L ; /* PCA 0 TIMER - LOW BYTE */
142 __sfr __at (0xEA) PCA0CPL0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
143 __sfr __at (0xEB) PCA0CPL1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
144 __sfr __at (0xEC) PCA0CPL2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
145 __sfr __at (0xED) PCA0CPL3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
146 __sfr __at (0xEE) PCA0CPL4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
147 __sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
148 __sfr __at (0xF0) B ; /* B REGISTER */
149 __sfr __at (0xF1) SCON1 ; /* UART1 CONTROL */
150 __sfr __at (0xF2) SBUF1 ; /* UART1 DATA */
151 __sfr __at (0xF3) SADDR1 ; /* UART1 Slave Address */
152 __sfr __at (0xF4) TL4 ; /* TIMER 4 DATA - LOW BYTE */
153 __sfr __at (0xF5) TH4 ; /* TIMER 4 DATA - HIGH BYTE */
154 __sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
155 __sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
156 __sfr __at (0xF8) SPI0CN ; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
157 __sfr __at (0xF9) PCA0H ; /* PCA 0 TIMER - HIGH BYTE */
158 __sfr __at (0xFA) PCA0CPH0 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
159 __sfr __at (0xFB) PCA0CPH1 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
160 __sfr __at (0xFC) PCA0CPH2 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
161 __sfr __at (0xFD) PCA0CPH3 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
162 __sfr __at (0xFE) PCA0CPH4 ; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
163 __sfr __at (0xFF) WDTCN ; /* WATCHDOG TIMER CONTROL */
164
165
166 /* WORD/DWORD Registers */
167
168 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
169 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
170 __sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
171 __sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
172 __sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
173 __sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
174 __sfr16 __at (0xF5F4) TMR4 ; /* TIMER 4 COUNTER */
175 __sfr16 __at (0xE5E4) RCAP4 ; /* TIMER 4 CAPTURE REGISTER WORD */
176 __sfr16 __at (0xBFBE) ADC0 ; /* ADC 0 DATA WORD */
177 __sfr16 __at (0xC5C4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
178 __sfr16 __at (0xC7C6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
179 __sfr16 __at (0xD3D2) DAC0 ; /* DAC 0 REGISTER WORD */
180 __sfr16 __at (0xD6D5) DAC1 ; /* DAC 1 REGISTER WORD */
181 __sfr16 __at (0xF9E9) PCA0 ; /* PCA COUNTER */
182 __sfr16 __at (0xFAEA) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
183 __sfr16 __at (0xFBEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
184 __sfr16 __at (0xFCEC) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
185 __sfr16 __at (0xFDED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
186 __sfr16 __at (0xFEEE) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
187
188
189 /* BIT Registers */
190
191 /* P0 0x80 */
192 __sbit __at (0x80) P0_0 ;
193 __sbit __at (0x81) P0_1 ;
194 __sbit __at (0x82) P0_2 ;
195 __sbit __at (0x83) P0_3 ;
196 __sbit __at (0x84) P0_4 ;
197 __sbit __at (0x85) P0_5 ;
198 __sbit __at (0x86) P0_6 ;
199 __sbit __at (0x87) P0_7 ;
200
201 /* TCON 0x88 */
202 __sbit __at (0x88) IT0 ; /* EXT. INTERRUPT 0 TYPE */
203 __sbit __at (0x89) IE0 ; /* EXT. INTERRUPT 0 EDGE FLAG */
204 __sbit __at (0x8A) IT1 ; /* EXT. INTERRUPT 1 TYPE */
205 __sbit __at (0x8B) IE1 ; /* EXT. INTERRUPT 1 EDGE FLAG */
206 __sbit __at (0x8C) TR0 ; /* TIMER 0 ON/OFF CONTROL */
207 __sbit __at (0x8D) TF0 ; /* TIMER 0 OVERFLOW FLAG */
208 __sbit __at (0x8E) TR1 ; /* TIMER 1 ON/OFF CONTROL */
209 __sbit __at (0x8F) TF1 ; /* TIMER 1 OVERFLOW FLAG */
210
211 /* P1 0x90 */
212 __sbit __at (0x90) P1_0 ;
213 __sbit __at (0x91) P1_1 ;
214 __sbit __at (0x92) P1_2 ;
215 __sbit __at (0x93) P1_3 ;
216 __sbit __at (0x94) P1_4 ;
217 __sbit __at (0x95) P1_5 ;
218 __sbit __at (0x96) P1_6 ;
219 __sbit __at (0x97) P1_7 ;
220
221 /* SCON 0x98 */
222 __sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
223 __sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
224 __sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
225 __sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
226 __sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
227 __sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
228 __sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
229 __sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
230 __sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
231 __sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
232 __sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
233 __sbit __at (0x9D) SM20 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
234 __sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
235 __sbit __at (0x9E) SM1 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
236 __sbit __at (0x9E) SM10 ; /* SCON.6 - SERIAL MODE CONTROL BIT 1 */
237 __sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
238 __sbit __at (0x9F) SM00 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
239 __sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
240
241 /* P2 0xA0 */
242 __sbit __at (0xA0) P2_0 ;
243 __sbit __at (0xA1) P2_1 ;
244 __sbit __at (0xA2) P2_2 ;
245 __sbit __at (0xA3) P2_3 ;
246 __sbit __at (0xA4) P2_4 ;
247 __sbit __at (0xA5) P2_5 ;
248 __sbit __at (0xA6) P2_6 ;
249 __sbit __at (0xA7) P2_7 ;
250
251 /* IE 0xA8 */
252 __sbit __at (0xA8) EX0 ; /* EXTERNAL INTERRUPT 0 ENABLE */
253 __sbit __at (0xA9) ET0 ; /* TIMER 0 INTERRUPT ENABLE */
254 __sbit __at (0xAA) EX1 ; /* EXTERNAL INTERRUPT 1 ENABLE */
255 __sbit __at (0xAB) ET1 ; /* TIMER 1 INTERRUPT ENABLE */
256 __sbit __at (0xAC) ES0 ; /* SERIAL PORT 0 INTERRUPT ENABLE */
257 __sbit __at (0xAC) ES ; /* SERIAL PORT 0 INTERRUPT ENABLE */
258 __sbit __at (0xAD) ET2 ; /* TIMER 2 INTERRUPT ENABLE */
259 __sbit __at (0xAF) EA ; /* GLOBAL INTERRUPT ENABLE */
260
261 /* P3 0xB0 */
262 __sbit __at (0xB0) P3_0 ;
263 __sbit __at (0xB1) P3_1 ;
264 __sbit __at (0xB2) P3_2 ;
265 __sbit __at (0xB3) P3_3 ;
266 __sbit __at (0xB4) P3_4 ;
267 __sbit __at (0xB5) P3_5 ;
268 __sbit __at (0xB6) P3_6 ;
269 __sbit __at (0xB7) P3_7 ;
270
271 /* IP 0xB8 */
272 __sbit __at (0xB8) PX0 ; /* EXTERNAL INTERRUPT 0 PRIORITY */
273 __sbit __at (0xB9) PT0 ; /* TIMER 0 PRIORITY */
274 __sbit __at (0xBA) PX1 ; /* EXTERNAL INTERRUPT 1 PRIORITY */
275 __sbit __at (0xBB) PT1 ; /* TIMER 1 PRIORITY */
276 __sbit __at (0xBC) PS0 ; /* SERIAL PORT PRIORITY */
277 __sbit __at (0xBC) PS ; /* SERIAL PORT PRIORITY */
278 __sbit __at (0xBD) PT2 ; /* TIMER 2 PRIORITY */
279
280 /* SMB0CN 0xC0 */
281 __sbit __at (0xC0) SMBTOE ; /* SMBUS 0 TIMEOUT ENABLE */
282 __sbit __at (0xC1) SMBFTE ; /* SMBUS 0 FREE TIMER ENABLE */
283 __sbit __at (0xC2) AA ; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
284 __sbit __at (0xC3) SI ; /* SMBUS 0 INTERRUPT PENDING FLAG */
285 __sbit __at (0xC4) STO ; /* SMBUS 0 STOP FLAG */
286 __sbit __at (0xC5) STA ; /* SMBUS 0 START FLAG */
287 __sbit __at (0xC6) ENSMB ; /* SMBUS 0 ENABLE */
288 __sbit __at (0xC7) BUSY ; /* SMBUS 0 BUSY */
289
290 /* T2CON 0xC8 */
291 __sbit __at (0xC8) CPRL2 ; /* CAPTURE OR RELOAD SELECT */
292 __sbit __at (0xC9) CT2 ; /* TIMER OR COUNTER SELECT */
293 __sbit __at (0xCA) TR2 ; /* TIMER 2 ON/OFF CONTROL */
294 __sbit __at (0xCB) EXEN2 ; /* TIMER 2 EXTERNAL ENABLE FLAG */
295 __sbit __at (0xCC) TCLK ; /* TRANSMIT CLOCK FLAG */
296 __sbit __at (0xCD) RCLK ; /* RECEIVE CLOCK FLAG */
297 __sbit __at (0xCE) EXF2 ; /* EXTERNAL FLAG */
298 __sbit __at (0xCF) TF2 ; /* TIMER 2 OVERFLOW FLAG */
299
300 /* PSW 0xD0 */
301 __sbit __at (0xD0) P ; /* ACCUMULATOR PARITY FLAG */
302 __sbit __at (0xD1) F1 ; /* USER FLAG 1 */
303 __sbit __at (0xD2) OV ; /* OVERFLOW FLAG */
304 __sbit __at (0xD3) RS0 ; /* REGISTER BANK SELECT 0 */
305 __sbit __at (0xD4) RS1 ; /* REGISTER BANK SELECT 1 */
306 __sbit __at (0xD5) F0 ; /* USER FLAG 0 */
307 __sbit __at (0xD6) AC ; /* AUXILIARY CARRY FLAG */
308 __sbit __at (0xD7) CY ; /* CARRY FLAG */
309
310 /* PCA0CN 0xD8H */
311 __sbit __at (0xD8) CCF0 ; /* PCA 0 MODULE 0 INTERRUPT FLAG */
312 __sbit __at (0xD9) CCF1 ; /* PCA 0 MODULE 1 INTERRUPT FLAG */
313 __sbit __at (0xDA) CCF2 ; /* PCA 0 MODULE 2 INTERRUPT FLAG */
314 __sbit __at (0xDB) CCF3 ; /* PCA 0 MODULE 3 INTERRUPT FLAG */
315 __sbit __at (0xDC) CCF4 ; /* PCA 0 MODULE 4 INTERRUPT FLAG */
316 __sbit __at (0xDE) CR ; /* PCA 0 COUNTER RUN CONTROL BIT */
317 __sbit __at (0xDF) CF ; /* PCA 0 COUNTER OVERFLOW FLAG */
318
319 /* ADC0CN 0xE8H */
320 __sbit __at (0xE8) ADLJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
321 __sbit __at (0xE8) AD0LJST ; /* ADC 0 RIGHT JUSTIFY DATA BIT */
322 __sbit __at (0xE9) ADWINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
323 __sbit __at (0xE9) AD0WINT ; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
324 __sbit __at (0xEA) ADSTM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
325 __sbit __at (0xEA) AD0CM0 ; /* ADC 0 START OF CONVERSION MODE BIT 0 */
326 __sbit __at (0xEB) ADSTM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
327 __sbit __at (0xEB) AD0CM1 ; /* ADC 0 START OF CONVERSION MODE BIT 1 */
328 __sbit __at (0xEC) ADBUSY ; /* ADC 0 BUSY FLAG */
329 __sbit __at (0xEC) AD0BUSY ; /* ADC 0 BUSY FLAG */
330 __sbit __at (0xED) ADCINT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
331 __sbit __at (0xED) AD0INT ; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
332 __sbit __at (0xEE) ADCTM ; /* ADC 0 TRACK MODE */
333 __sbit __at (0xEE) AD0TM ; /* ADC 0 TRACK MODE */
334 __sbit __at (0xEF) ADCEN ; /* ADC 0 ENABLE */
335 __sbit __at (0xEF) AD0EN ; /* ADC 0 ENABLE */
336
337 /* SPI0CN 0xF8H */
338 __sbit __at (0xF8) SPIEN ; /* SPI 0 SPI ENABLE */
339 __sbit __at (0xF9) MSTEN ; /* SPI 0 MASTER ENABLE */
340 __sbit __at (0xFA) SLVSEL ; /* SPI 0 SLAVE SELECT */
341 __sbit __at (0xFB) TXBSY ; /* SPI 0 TX BUSY FLAG */
342 __sbit __at (0xFC) RXOVRN ; /* SPI 0 RX OVERRUN FLAG */
343 __sbit __at (0xFD) MODF ; /* SPI 0 MODE FAULT FLAG */
344 __sbit __at (0xFE) WCOL ; /* SPI 0 WRITE COLLISION FLAG */
345 __sbit __at (0xFF) SPIF ; /* SPI 0 INTERRUPT FLAG */
346
347
348 /* Predefined SFR Bit Masks */
349
350 #define PCON_IDLE 0x01 /* PCON */
351 #define PCON_STOP 0x02 /* PCON */
352 #define PCON_SMOD0 0x80 /* PCON */
353 #define TF3 0x80 /* TMR3CN */
354 #define CPFIF 0x10 /* CPTnCN */
355 #define CPRIF 0x20 /* CPTnCN */
356 #define CPOUT 0x40 /* CPTnCN */
357 #define TR4 0x04 /* T4CON */
358 #define TF4 0x80 /* T4CON */
359 #define ECCF 0x01 /* PCA0CPMn */
360 #define PWM 0x02 /* PCA0CPMn */
361 #define TOG 0x04 /* PCA0CPMn */
362 #define MAT 0x08 /* PCA0CPMn */
363 #define CAPN 0x10 /* PCA0CPMn */
364 #define CAPP 0x20 /* PCA0CPMn */
365 #define ECOM 0x40 /* PCA0CPMn */
366 #define PWM16 0x80 /* PCA0CPMn */
367 #define PORSF 0x02 /* RSTSRC */
368 #define SWRSF 0x10 /* RSTSRC */
369 #define RI1 0x01 /* SCON1 */
370 #define TI1 0x02 /* SCON1 */
371 #define RB81 0x04 /* SCON1 */
372 #define TB81 0x08 /* SCON1 */
373 #define REN1 0x10 /* SCON1 */
374 #define SM21 0x20 /* SCON1 */
375 #define SM11 0x40 /* SCON1 */
376 #define SM01 0x80 /* SCON1 */
377
378 #endif
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