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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / C8051F060.h
blob5090ead1b4402245f27f5f7d1842886f18559796
1 /*-------------------------------------------------------------------------
2 C8051F060.h - Register Declarations for the Cygnal/SiLabs C8051F06x
3 Processor Range
4
5 Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 #ifndef C8051F060_H
31 #define C8051F060_H
32
33 #include <compiler.h>
34
35 /* BYTE Registers */
36
37 /* All Pages */
38 SFR(P0, 0x80); /* PORT 0 */
39 SFR(SP, 0x81); /* STACK POINTER */
40 SFR(DPL, 0x82); /* DATA POINTER - LOW BYTE */
41 SFR(DPH, 0x83); /* DATA POINTER - HIGH BYTE */
42 SFR(SFRPAGE, 0x84); /* SFR PAGE SELECT */
43 SFR(SFRNEXT, 0x85); /* SFR STACK NEXT PAGE */
44 SFR(SFRLAST, 0x86); /* SFR STACK LAST PAGE */
45 SFR(PCON, 0x87); /* POWER CONTROL */
46 SFR(P1, 0x90); /* PORT 1 */
47 SFR(P2, 0xA0); /* PORT 2 */
48 SFR(IE, 0xA8); /* INTERRUPT ENABLE */
49 SFR(P3, 0xB0); /* PORT 3 */
50 SFR(IP, 0xB8); /* INTERRUPT PRIORITY */
51 SFR(PSW, 0xD0); /* PROGRAM STATUS WORD */
52 SFR(ACC, 0xE0); /* ACCUMULATOR */
53 SFR(EIE1, 0xE6); /* EXTERNAL INTERRUPT ENABLE 1 */
54 SFR(EIE2, 0xE7); /* EXTERNAL INTERRUPT ENABLE 2 */
55 SFR(B, 0xF0); /* B REGISTER */
56 SFR(EIP1, 0xF6); /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
57 SFR(EIP2, 0xF7); /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
58 SFR(WDTCN, 0xFF); /* WATCHDOG TIMER CONTROL */
59
60 /* Page 0x00 */
61 SFR(TCON, 0x88); /* TIMER CONTROL */
62 SFR(TMOD, 0x89); /* TIMER MODE */
63 SFR(TL0, 0x8A); /* TIMER 0 - LOW BYTE */
64 SFR(TL1, 0x8B); /* TIMER 1 - LOW BYTE */
65 SFR(TH0, 0x8C); /* TIMER 0 - HIGH BYTE */
66 SFR(TH1, 0x8D); /* TIMER 1 - HIGH BYTE */
67 SFR(CKCON, 0x8E); /* TIMER 0/1 CLOCK CONTROL */
68 SFR(PSCTL, 0x8F); /* FLASH WRITE/ERASE CONTROL */
69 SFR(SSTA0, 0x91); /* UART 0 STATUS */
70 SFR(SCON0, 0x98); /* UART 0 CONTROL */
71 SFR(SCON, 0x98); /* UART 0 CONTROL */
72 SFR(SBUF0, 0x99); /* UART 0 BUFFER */
73 SFR(SBUF, 0x99); /* UART 0 BUFFER */
74 SFR(SPI0CFG, 0x9A); /* SPI 0 CONFIGURATION */
75 SFR(SPI0DAT, 0x9B); /* SPI 0 DATA */
76 SFR(SPI0CKR, 0x9D); /* SPI 0 CLOCK RATE CONTROL */
77 SFR(EMI0TC, 0xA1); /* EMIF TIMING CONTROL */
78 SFR(EMI0CN, 0xA2); /* EMIF CONTROL */
79 SFR(_XPAGE, 0xA2); /* XDATA/PDATA PAGE */
80 SFR(EMI0CF, 0xA3); /* EMIF CONFIGURATION */
81 SFR(SADDR0, 0xA9); /* UART 0 SLAVE ADDRESS */
82 SFR(FLSCL, 0xB7); /* FLASH SCALE */
83 SFR(SADEN0, 0xB9); /* UART 0 SLAVE ADDRESS MASK */
84 SFR(AMX0SL, 0xBB); /* ADC 0 MUX CHANNEL SELECTION */
85 SFR(ADC0CF, 0xBC); /* ADC 0 CONFIGURATION */
86 SFR(ADC0L, 0xBE); /* ADC 0 DATA - LOW BYTE */
87 SFR(ADC0H, 0xBF); /* ADC 0 DATA - HIGH BYTE */
88 SFR(SMB0CN, 0xC0); /* SMBUS 0 CONTROL */
89 SFR(SMB0STA, 0xC1); /* SMBUS 0 STATUS */
90 SFR(SMB0DAT, 0xC2); /* SMBUS 0 DATA */
91 SFR(SMB0ADR, 0xC3); /* SMBUS 0 SLAVE ADDRESS */
92 SFR(ADC0GTL, 0xC4); /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
93 SFR(ADC0GTH, 0xC5); /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
94 SFR(ADC0LTL, 0xC6); /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
95 SFR(ADC0LTH, 0xC7); /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
96 SFR(TMR2CN, 0xC8); /* TIMER 2 CONTROL */
97 SFR(TMR2CF, 0xC9); /* TIMER 2 CONFIGURATION */
98 SFR(RCAP2L, 0xCA); /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
99 SFR(RCAP2H, 0xCB); /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
100 SFR(TMR2L, 0xCC); /* TIMER 2 - LOW BYTE */
101 SFR(TL2, 0xCC); /* TIMER 2 - LOW BYTE */
102 SFR(TMR2H, 0xCD); /* TIMER 2 - HIGH BYTE */
103 SFR(TH2, 0xCD); /* TIMER 2 - HIGH BYTE */
104 SFR(SMB0CR, 0xCF); /* SMBUS 0 CLOCK RATE */
105 SFR(REF0CN, 0xD1); /* VOLTAGE REFERENCE 0 CONTROL */
106 SFR(DAC0L, 0xD2); /* DAC 0 REGISTER - LOW BYTE */
107 SFR(DAC0H, 0xD3); /* DAC 0 REGISTER - HIGH BYTE */
108 SFR(DAC0CN, 0xD4); /* DAC 0 CONTROL */
109 SFR(PCA0CN, 0xD8); /* PCA 0 COUNTER CONTROL */
110 SFR(PCA0MD, 0xD9); /* PCA 0 COUNTER MODE */
111 SFR(PCA0CPM0, 0xDA); /* PCA 0 MODULE 0 CONTROL */
112 SFR(PCA0CPM1, 0xDB); /* PCA 0 MODULE 1 CONTROL */
113 SFR(PCA0CPM2, 0xDC); /* PCA 0 MODULE 2 CONTROL */
114 SFR(PCA0CPM3, 0xDD); /* PCA 0 MODULE 3 CONTROL */
115 SFR(PCA0CPM4, 0xDE); /* PCA 0 MODULE 4 CONTROL */
116 SFR(PCA0CPM5, 0xDF); /* PCA 0 MODULE 5 CONTROL */
117 SFR(PCA0CPL5, 0xE1); /* PCA 0 MODULE 5 CAPTURE/COMPARE - LOW BYTE */
118 SFR(PCA0CPH5, 0xE2); /* PCA 0 MODULE 5 CAPTURE/COMPARE - HIGH BYTE */
119 SFR(ADC0CN, 0xE8); /* ADC 0 CONTROL */
120 SFR(PCA0CPL2, 0xE9); /* PCA 0 MODULE 2 CAPTURE/COMPARE - LOW BYTE */
121 SFR(PCA0CPH2, 0xEA); /* PCA 0 MODULE 2 CAPTURE/COMPARE - HIGH BYTE */
122 SFR(PCA0CPL3, 0xEB); /* PCA 0 MODULE 3 CAPTURE/COMPARE - LOW BYTE */
123 SFR(PCA0CPH3, 0xEC); /* PCA 0 MODULE 3 CAPTURE/COMPARE - HIGH BYTE */
124 SFR(PCA0CPL4, 0xED); /* PCA 0 MODULE 4 CAPTURE/COMPARE - LOW BYTE */
125 SFR(PCA0CPH4, 0xEE); /* PCA 0 MODULE 4 CAPTURE/COMPARE - HIGH BYTE */
126 SFR(RSTSRC, 0xEF); /* RESET SOURCE */
127 SFR(SPI0CN, 0xF8); /* SPI 0 CONTROL */
128 SFR(PCA0L, 0xF9); /* PCA 0 TIMER - LOW BYTE */
129 SFR(PCA0H, 0xFA); /* PCA 0 TIMER - HIGH BYTE */
130 SFR(PCA0CPL0, 0xFB); /* PCA 0 MODULE 0 CAPTURE/COMPARE - LOW BYTE */
131 SFR(PCA0CPH0, 0xFC); /* PCA 0 MODULE 0 CAPTURE/COMPARE - HIGH BYTE */
132 SFR(PCA0CPL1, 0xFD); /* PCA 0 MODULE 1 CAPTURE/COMPARE - LOW BYTE */
133 SFR(PCA0CPH1, 0xFE); /* PCA 0 MODULE 1 CAPTURE/COMPARE - HIGH BYTE */
134
135 /* Page 0x01 */
136 SFR(CPT0CN, 0x88); /* COMPARATOR 0 CONTROL */
137 SFR(CPT0MD, 0x89); /* COMPARATOR 0 CONFIGURATION */
138 SFR(SCON1, 0x98); /* UART 1 CONTROL */
139 SFR(SBUF1, 0x99); /* UART 1 BUFFER */
140 SFR(ADC1CF, 0xBC); /* ADC 1 CONFIGURATION */
141 SFR(ADC1L, 0xBE); /* ADC 1 DATA - LOW BYTE */
142 SFR(ADC1H, 0xBF); /* ADC 1 DATA - HIGH BYTE */
143 SFR(CAN0STA, 0xC0); /* CAN 0 STATUS */
144 SFR(TMR3CN, 0xC8); /* TIMER 3 CONTROL */
145 SFR(TMR3CF, 0xC9); /* TIMER 3 CONFIGURATION */
146 SFR(RCAP3L, 0xCA); /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
147 SFR(RCAP3H, 0xCB); /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
148 SFR(TMR3L, 0xCC); /* TIMER 3 - LOW BYTE */
149 SFR(TMR3H, 0xCD); /* TIMER 3 - HIGH BYTE */
150 SFR(REF1CN, 0xD1); /* VOLTAGE REFERENCE 1 CONTROL */
151 SFR(DAC1L, 0xD2); /* DAC 1 REGISTER - LOW BYTE */
152 SFR(DAC1H, 0xD3); /* DAC 1 REGISTER - HIGH BYTE */
153 SFR(DAC1CN, 0xD4); /* DAC 1 CONTROL */
154 SFR(CAN0DATL, 0xD8); /* CAN 0 DATA REGISTER LOW */
155 SFR(CAN0DATH, 0xD9); /* CAN 0 DATA REGISTER HIGH */
156 SFR(CAN0ADR, 0xDA); /* CAN 0 ADDRESS */
157 SFR(CAN0TST, 0xDB); /* CAN 0 TEST REGISTER */
158 SFR(ADC1CN, 0xE8); /* ADC 1 CONTROL */
159 SFR(CAN0CN, 0xF8); /* CAN 0 CONTROL */
160
161 /* Page 0x02 */
162 SFR(CPT1CN, 0x88); /* COMPARATOR 1 CONTROL */
163 SFR(CPT1MD, 0x89); /* COMPARATOR 1 CONFIGURATION */
164 SFR(AMX2CF, 0xBA); /* ADC 2 MUX CONFIGURATION */
165 SFR(AMX2SL, 0xBB); /* ADC 2 MUX CHANNEL SELECTION */
166 SFR(ADC2CF, 0xBC); /* ADC 2 CONFIGURATION */
167 SFR(ADC2L, 0xBE); /* ADC 2 DATA - LOW BYTE */
168 SFR(ADC2H, 0xBF); /* ADC 2 DATA - HIGH BYTE */
169 SFR(ADC2GTL, 0xC4); /* ADC 2 GREATER-THAN REGISTER - LOW BYTE */
170 SFR(ADC2GTH, 0xC5); /* ADC 2 GREATER-THAN REGISTER - HIGH BYTE */
171 SFR(ADC2LTL, 0xC6); /* ADC 2 LESS-THAN REGISTER - LOW BYTE */
172 SFR(ADC2LTH, 0xC7); /* ADC 2 LESS-THAN REGISTER - HIGH BYTE */
173 SFR(TMR4CN, 0xC8); /* TIMER 4 CONTROL */
174 SFR(TMR4CF, 0xC9); /* TIMER 4 CONFIGURATION */
175 SFR(RCAP4L, 0xCA); /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
176 SFR(RCAP4H, 0xCB); /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
177 SFR(TMR4L, 0xCC); /* TIMER 4 - LOW BYTE */
178 SFR(TMR4H, 0xCD); /* TIMER 4 - HIGH BYTE */
179 SFR(REF2CN, 0xD1); /* VOLTAGE REFERENCE 2 CONTROL */
180 SFR(ADC2CN, 0xE8); /* ADC 2 CONTROL */
181
182 /* Page 0x03 */
183 SFR(CPT2CN, 0x88); /* COMPARATOR 2 CONTROL */
184 SFR(CPT2MD, 0x89); /* COMPARATOR 2 CONFIGURATION */
185 SFR(DMA0CN, 0xD8); /* DMA0 CONTROL */
186 SFR(DMA0DAL, 0xD9); /* DMA0 DATA ADDRESS BEGINNING LOW BYTE */
187 SFR(DMA0DAH, 0xDA); /* DMA0 DATA ADDRESS BEGINNING HIGH BYTE */
188 SFR(DMA0DSL, 0xDB); /* DMA0 DATA ADDRESS POINTER LOW BYTE */
189 SFR(DMA0DSH, 0xDC); /* DMA0 DATA ADDRESS POINTER HIGH BYTE */
190 SFR(DMA0IPT, 0xDD); /* DMA0 INSTRUCTION WRITE ADDRESS */
191 SFR(DMA0IDT, 0xDE); /* DMA0 INSTRUCTION WRITE DATA */
192 SFR(DMA0CF, 0xF8); /* DMA0 CONFIGURATION */
193 SFR(DMA0CTL, 0xF9); /* DMA0 REPEAT COUNTER LIMIT LOW BYTE */
194 SFR(DMA0CTH, 0xFA); /* DMA0 REPEAT COUNTER LIMIT HIGH BYTE */
195 SFR(DMA0CSL, 0xFB); /* DMA0 REPEAT COUNTER STATUS LOW BYTE */
196 SFR(DMA0CSH, 0xFC); /* DMA0 REPEAT COUNTER STATUS HIGH BYTE */
197 SFR(DMA0BND, 0xFD); /* DMA0 INSTRUCTION BOUNDARY */
198 SFR(DMA0ISW, 0xFE); /* DMA0 INSTRUCTION STATUS */
199
200 /* Page 0x0F */
201 SFR(OSCICN, 0x8A); /* INTERNAL OSCILLATOR CONTROL */
202 SFR(OSCICL, 0x8B); /* INTERNAL OSCILLATOR CALIBRATION */
203 SFR(OSCXCN, 0x8C); /* EXTERNAL OSCILLATOR CONTROL */
204 SFR(SFRPGCN, 0x96); /* SFR PAGE CONTROL */
205 SFR(CLKSEL, 0x97); /* SYSTEM CLOCK SELECT */
206 SFR(P4MDOUT, 0x9C); /* PORT 4 OUTPUT MODE */
207 SFR(P5MDOUT, 0x9D); /* PORT 5 OUTPUT MODE */
208 SFR(P6MDOUT, 0x9E); /* PORT 6 OUTPUT MODE */
209 SFR(P7MDOUT, 0x9F); /* PORT 7 OUTPUT MODE */
210 SFR(P0MDOUT, 0xA4); /* PORT 0 OUTPUT MODE */
211 SFR(P1MDOUT, 0xA5); /* PORT 1 OUTPUT MODE */
212 SFR(P2MDOUT, 0xA6); /* PORT 2 OUTPUT MODE CONFIGURATION */
213 SFR(P3MDOUT, 0xA7); /* PORT 3 OUTPUT MODE CONFIGURATION */
214 SFR(P1MDIN, 0xAD); /* PORT 1 INPUT MODE */
215 SFR(P2MDIN, 0xAE); /* PORT 2 INPUT MODE */
216 SFR(FLACL, 0xB7); /* FLASH ACCESS LIMIT */
217 SFR(ADC0CPT, 0xBA); /* ADC0 CALIBRATION POINTER */
218 SFR(ADC0CCF, 0xBB); /* ADC0 CALIBRATION COEFFICIENT */
219 SFR(P4, 0xC8); /* PORT 4 */
220 SFR(P5, 0xD8); /* PORT 5 */
221 SFR(XBR0, 0xE1); /* CROSSBAR CONFIGURATION REGISTER 0 */
222 SFR(XBR1, 0xE2); /* CROSSBAR CONFIGURATION REGISTER 1 */
223 SFR(XBR2, 0xE3); /* CROSSBAR CONFIGURATION REGISTER 2 */
224 SFR(XBR3, 0xE4); /* CROSSBAR CONFIGURATION REGISTER 3 */
225 SFR(P6, 0xE8); /* PORT 6 */
226 SFR(P7, 0xF8); /* PORT 7 */
227
228
229 /* BIT Registers */
230
231 /* P0 0x80 */
232 SBIT(P0_0, 0x80, 0);
233 SBIT(P0_1, 0x80, 1);
234 SBIT(P0_2, 0x80, 2);
235 SBIT(P0_3, 0x80, 3);
236 SBIT(P0_4, 0x80, 4);
237 SBIT(P0_5, 0x80, 5);
238 SBIT(P0_6, 0x80, 6);
239 SBIT(P0_7, 0x80, 7);
240
241 /* TCON 0x88 */
242 SBIT(IT0, 0x88, 0); /* EXT. INTERRUPT 0 TYPE */
243 SBIT(IE0, 0x88, 1); /* EXT. INTERRUPT 0 EDGE FLAG */
244 SBIT(IT1, 0x88, 2); /* EXT. INTERRUPT 1 TYPE */
245 SBIT(IE1, 0x88, 3); /* EXT. INTERRUPT 1 EDGE FLAG */
246 SBIT(TR0, 0x88, 4); /* TIMER 0 ON/OFF CONTROL */
247 SBIT(TF0, 0x88, 5); /* TIMER 0 OVERFLOW FLAG */
248 SBIT(TR1, 0x88, 6); /* TIMER 1 ON/OFF CONTROL */
249 SBIT(TF1, 0x88, 7); /* TIMER 1 OVERFLOW FLAG */
250
251 /* CPT0CN 0x88 */
252 SBIT(CP0HYN0, 0x88, 0); /* COMPARATOR 0 NEGATIVE HYSTERESIS 0 */
253 SBIT(CP0HYN1, 0x88, 1); /* COMPARATOR 0 NEGATIVE HYSTERESIS 1 */
254 SBIT(CP0HYP0, 0x88, 2); /* COMPARATOR 0 POSITIVE HYSTERESIS 0 */
255 SBIT(CP0HYP1, 0x88, 3); /* COMPARATOR 0 POSITIVE HYSTERESIS 1 */
256 SBIT(CP0FIF, 0x88, 4); /* COMPARATOR 0 FALLING EDGE INTERRUPT */
257 SBIT(CP0RIF, 0x88, 5); /* COMPARATOR 0 RISING EDGE INTERRUPT */
258 SBIT(CP0OUT, 0x88, 6); /* COMPARATOR 0 OUTPUT */
259 SBIT(CP0EN, 0x88, 7); /* COMPARATOR 0 ENABLE */
260
261 /* CPT1CN 0x88 */
262 SBIT(CP1HYN0, 0x88, 0); /* COMPARATOR 1 NEGATIVE HYSTERESIS 0 */
263 SBIT(CP1HYN1, 0x88, 1); /* COMPARATOR 1 NEGATIVE HYSTERESIS 1 */
264 SBIT(CP1HYP0, 0x88, 2); /* COMPARATOR 1 POSITIVE HYSTERESIS 0 */
265 SBIT(CP1HYP1, 0x88, 3); /* COMPARATOR 1 POSITIVE HYSTERESIS 1 */
266 SBIT(CP1FIF, 0x88, 4); /* COMPARATOR 1 FALLING EDGE INTERRUPT */
267 SBIT(CP1RIF, 0x88, 5); /* COMPARATOR 1 RISING EDGE INTERRUPT */
268 SBIT(CP1OUT, 0x88, 6); /* COMPARATOR 1 OUTPUT */
269 SBIT(CP1EN, 0x88, 7); /* COMPARATOR 1 ENABLE */
270
271 /* CPT2CN 0x88 */
272 SBIT(CP2HYN0, 0x88, 0); /* COMPARATOR 2 NEGATIVE HYSTERESIS 0 */
273 SBIT(CP2HYN1, 0x88, 1); /* COMPARATOR 2 NEGATIVE HYSTERESIS 1 */
274 SBIT(CP2HYP0, 0x88, 2); /* COMPARATOR 2 POSITIVE HYSTERESIS 0 */
275 SBIT(CP2HYP1, 0x88, 3); /* COMPARATOR 2 POSITIVE HYSTERESIS 1 */
276 SBIT(CP2FIF, 0x88, 4); /* COMPARATOR 2 FALLING EDGE INTERRUPT */
277 SBIT(CP2RIF, 0x88, 5); /* COMPARATOR 2 RISING EDGE INTERRUPT */
278 SBIT(CP2OUT, 0x88, 6); /* COMPARATOR 2 OUTPUT */
279 SBIT(CP2EN, 0x88, 7); /* COMPARATOR 2 ENABLE */
280
281 /* P1 0x90 */
282 SBIT(P1_0, 0x90, 0);
283 SBIT(P1_1, 0x90, 1);
284 SBIT(P1_2, 0x90, 2);
285 SBIT(P1_3, 0x90, 3);
286 SBIT(P1_4, 0x90, 4);
287 SBIT(P1_5, 0x90, 5);
288 SBIT(P1_6, 0x90, 6);
289 SBIT(P1_7, 0x90, 7);
290
291 /* SCON0 0x98 */
292 SBIT(RI0, 0x98, 0); /* UART 0 RX INTERRUPT FLAG */
293 SBIT(RI, 0x98, 0); /* UART 0 RX INTERRUPT FLAG */
294 SBIT(TI0, 0x98, 1); /* UART 0 TX INTERRUPT FLAG */
295 SBIT(TI, 0x98, 1); /* UART 0 TX INTERRUPT FLAG */
296 SBIT(RB80, 0x98, 2); /* UART 0 RX BIT 8 */
297 SBIT(TB80, 0x98, 3); /* UART 0 TX BIT 8 */
298 SBIT(REN0, 0x98, 4); /* UART 0 RX ENABLE */
299 SBIT(REN, 0x98, 4); /* UART 0 RX ENABLE */
300 SBIT(SM20, 0x98, 5); /* UART 0 MULTIPROCESSOR EN */
301 SBIT(SM10, 0x98, 6); /* UART 0 MODE 1 */
302 SBIT(SM00, 0x98, 7); /* UART 0 MODE 0 */
303
304 /* SCON1 0x98 */
305 SBIT(RI1, 0x98, 0); /* UART 1 RX INTERRUPT FLAG */
306 SBIT(TI1, 0x98, 1); /* UART 1 TX INTERRUPT FLAG */
307 SBIT(RB81, 0x98, 2); /* UART 1 RX BIT 8 */
308 SBIT(TB81, 0x98, 3); /* UART 1 TX BIT 8 */
309 SBIT(REN1, 0x98, 4); /* UART 1 RX ENABLE */
310 SBIT(MCE1, 0x98, 5); /* UART 1 MCE */
311 SBIT(S1MODE, 0x98, 7); /* UART 1 MODE */
312
313 /* P2 0xA0 */
314 SBIT(P2_0, 0xA0, 0);
315 SBIT(P2_1, 0xA0, 1);
316 SBIT(P2_2, 0xA0, 2);
317 SBIT(P2_3, 0xA0, 3);
318 SBIT(P2_4, 0xA0, 4);
319 SBIT(P2_5, 0xA0, 5);
320 SBIT(P2_6, 0xA0, 6);
321 SBIT(P2_7, 0xA0, 7);
322
323 /* IE 0xA8 */
324 SBIT(EX0, 0xA8, 0); /* EXTERNAL INTERRUPT 0 ENABLE */
325 SBIT(ET0, 0xA8, 1); /* TIMER 0 INTERRUPT ENABLE */
326 SBIT(EX1, 0xA8, 2); /* EXTERNAL INTERRUPT 1 ENABLE */
327 SBIT(ET1, 0xA8, 3); /* TIMER 1 INTERRUPT ENABLE */
328 SBIT(ES0, 0xA8, 4); /* UART0 INTERRUPT ENABLE */
329 SBIT(ES, 0xA8, 4); /* UART0 INTERRUPT ENABLE */
330 SBIT(ET2, 0xA8, 5); /* TIMER 2 INTERRUPT ENABLE */
331 SBIT(EA, 0xA8, 7); /* GLOBAL INTERRUPT ENABLE */
332
333 /* P3 0xB0 */
334 SBIT(P3_0, 0xB0, 0);
335 SBIT(P3_1, 0xB0, 1);
336 SBIT(P3_2, 0xB0, 2);
337 SBIT(P3_3, 0xB0, 3);
338 SBIT(P3_4, 0xB0, 4);
339 SBIT(P3_5, 0xB0, 5);
340 SBIT(P3_6, 0xB0, 6);
341 SBIT(P3_7, 0xB0, 7);
342
343 /* IP 0xB8 */
344 SBIT(PX0, 0xB8, 0); /* EXTERNAL INTERRUPT 0 PRIORITY */
345 SBIT(PT0, 0xB8, 1); /* TIMER 0 PRIORITY */
346 SBIT(PX1, 0xB8, 2); /* EXTERNAL INTERRUPT 1 PRIORITY */
347 SBIT(PT1, 0xB8, 3); /* TIMER 1 PRIORITY */
348 SBIT(PS0, 0xB8, 4); /* SERIAL PORT PRIORITY */
349 SBIT(PS, 0xB8, 4); /* SERIAL PORT PRIORITY */
350 SBIT(PT2, 0xB8, 5); /* TIMER 2 PRIORITY */
351
352 /* SMB0CN 0xC0 */
353 SBIT(SMBTOE, 0xC0, 0); /* SMBUS 0 TIMEOUT ENABLE */
354 SBIT(SMBFTE, 0xC0, 1); /* SMBUS 0 FREE TIMER ENABLE */
355 SBIT(AA, 0xC0, 2); /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
356 SBIT(SI, 0xC0, 3); /* SMBUS 0 INTERRUPT PENDING FLAG */
357 SBIT(STO, 0xC0, 4); /* SMBUS 0 STOP FLAG */
358 SBIT(STA, 0xC0, 5); /* SMBUS 0 START FLAG */
359 SBIT(ENSMB, 0xC0, 6); /* SMBUS 0 ENABLE */
360 SBIT(BUSY, 0xC0, 7); /* SMBUS 0 BUSY */
361
362 /* CAN0STA 0xC0 */
363 SBIT(CANTXOK, 0xC0, 3); /* CAN TRANSMITTED A MESSAGE SUCCESSFULLY */
364 SBIT(CANRXOK, 0xC0, 4); /* CAN RECEIVED A MESSAGE SUCCESSFULLY */
365 SBIT(CANEPASS, 0xC0, 5); /* CAN ERROR PASSIVE */
366 SBIT(CANEWARN, 0xC0, 6); /* CAN WARNING STATUS */
367 SBIT(CANBOFF, 0xC0, 7); /* CAN BUSOFF STATUS */
368
369 /* TMR2CN 0xC8 */
370 SBIT(CPRL2, 0xC8, 0); /* TIMER 2 CAPTURE SELECT */
371 SBIT(CT2, 0xC8, 1); /* TIMER 2 COUNTER SELECT */
372 SBIT(TR2, 0xC8, 2); /* TIMER 2 ON/OFF CONTROL */
373 SBIT(EXEN2, 0xC8, 3); /* TIMER 2 EXTERNAL ENABLE FLAG */
374 SBIT(EXF2, 0xC8, 6); /* TIMER 2 EXTERNAL FLAG */
375 SBIT(TF2, 0xC8, 7); /* TIMER 2 OVERFLOW FLAG */
376
377 /* TMR3CN 0xC8 */
378 SBIT(CPRL3, 0xC8, 0); /* TIMER 3 CAPTURE SELECT */
379 SBIT(CT3, 0xC8, 1); /* TIMER 3 COUNTER SELECT */
380 SBIT(TR3, 0xC8, 2); /* TIMER 3 ON/OFF CONTROL */
381 SBIT(EXEN3, 0xC8, 3); /* TIMER 3 EXTERNAL ENABLE FLAG */
382 SBIT(EXF3, 0xC8, 6); /* TIMER 3 EXTERNAL FLAG */
383 SBIT(TF3, 0xC8, 7); /* TIMER 3 OVERFLOW FLAG */
384
385 /* TMR4CN 0xC8 */
386 SBIT(CPRL4, 0xC8, 0); /* TIMER 4 CAPTURE SELECT */
387 SBIT(CT4, 0xC8, 1); /* TIMER 4 COUNTER SELECT */
388 SBIT(TR4, 0xC8, 2); /* TIMER 4 ON/OFF CONTROL */
389 SBIT(EXEN4, 0xC8, 3); /* TIMER 4 EXTERNAL ENABLE FLAG */
390 SBIT(EXF4, 0xC8, 6); /* TIMER 4 EXTERNAL FLAG */
391 SBIT(TF4, 0xC8, 7); /* TIMER 4 OVERFLOW FLAG */
392
393 /* P4 0xC8 */
394 SBIT(P4_0, 0xC8, 0);
395 SBIT(P4_1, 0xC8, 1);
396 SBIT(P4_2, 0xC8, 2);
397 SBIT(P4_3, 0xC8, 3);
398 SBIT(P4_4, 0xC8, 4);
399 SBIT(P4_5, 0xC8, 5);
400 SBIT(P4_6, 0xC8, 6);
401 SBIT(P4_7, 0xC8, 7);
402
403 /* PSW 0xD0 */
404 SBIT(P, 0xD0, 0); /* ACCUMULATOR PARITY FLAG */
405 SBIT(F1, 0xD0, 1); /* USER FLAG 1 */
406 SBIT(OV, 0xD0, 2); /* OVERFLOW FLAG */
407 SBIT(RS0, 0xD0, 3); /* REGISTER BANK SELECT 0 */
408 SBIT(RS1, 0xD0, 4); /* REGISTER BANK SELECT 1 */
409 SBIT(F0, 0xD0, 5); /* USER FLAG 0 */
410 SBIT(AC, 0xD0, 6); /* AUXILIARY CARRY FLAG */
411 SBIT(CY, 0xD0, 7); /* CARRY FLAG */
412
413 /* PCA0CN 0xD8 */
414 SBIT(CCF0, 0xD8, 0); /* PCA 0 MODULE 0 INTERRUPT FLAG */
415 SBIT(CCF1, 0xD8, 1); /* PCA 0 MODULE 1 INTERRUPT FLAG */
416 SBIT(CCF2, 0xD8, 2); /* PCA 0 MODULE 2 INTERRUPT FLAG */
417 SBIT(CCF3, 0xD8, 3); /* PCA 0 MODULE 3 INTERRUPT FLAG */
418 SBIT(CCF4, 0xD8, 4); /* PCA 0 MODULE 4 INTERRUPT FLAG */
419 SBIT(CCF5, 0xD8, 5); /* PCA 0 MODULE 5 INTERRUPT FLAG */
420 SBIT(CR, 0xD8, 6); /* PCA 0 COUNTER RUN CONTROL BIT */
421 SBIT(CF, 0xD8, 7); /* PCA 0 COUNTER OVERFLOW FLAG */
422
423 /* DMA0CN 0xD8 */
424 SBIT(DMA0DO0, 0xD8, 0); /* ADC0 Data Overflow Warning Flag */
425 SBIT(DMA0DO1, 0xD8, 1); /* ADC1 Data Overflow Warning Flag */
426 SBIT(DMA0DOE, 0xD8, 2); /* Data Overflow Warning Interrupt Enable */
427 SBIT(DMA0DE0, 0xD8, 3); /* ADC0 Data Overflow Error Flag */
428 SBIT(DMA0DE1, 0xD8, 4); /* ADC1 Data Overflow Error Flag */
429 SBIT(DMA0MD, 0xD8, 5); /* DMA0 Mode Select */
430 SBIT(DMA0INT, 0xD8, 6); /* DMA0 Operations Complete Flag */
431 SBIT(DMA0EN, 0xD8, 7); /* DMA0 Enable */
432
433 /* P5 0xD8 */
434 SBIT(P5_0, 0xD8, 0);
435 SBIT(P5_1, 0xD8, 1);
436 SBIT(P5_2, 0xD8, 2);
437 SBIT(P5_3, 0xD8, 3);
438 SBIT(P5_4, 0xD8, 4);
439 SBIT(P5_5, 0xD8, 5);
440 SBIT(P5_6, 0xD8, 6);
441 SBIT(P5_7, 0xD8, 7);
442
443 /* ADC0CN 0xE8 */
444 SBIT(AD0WINT, 0xE8, 1); /* ADC 0 WINDOW INTERRUPT FLAG */
445 SBIT(AD0CM0, 0xE8, 2); /* ADC 0 CONVERT START MODE BIT 0 */
446 SBIT(AD0CM1, 0xE8, 3); /* ADC 0 CONVERT START MODE BIT 1 */
447 SBIT(AD0BUSY, 0xE8, 4); /* ADC 0 BUSY FLAG */
448 SBIT(AD0INT, 0xE8, 5); /* ADC 0 EOC INTERRUPT FLAG */
449 SBIT(AD0TM, 0xE8, 6); /* ADC 0 TRACK MODE */
450 SBIT(AD0EN, 0xE8, 7); /* ADC 0 ENABLE */
451
452 /* ADC1CN 0xE8 */
453 SBIT(AD1CM0, 0xE8, 1); /* ADC 1 CONVERT START MODE BIT 0 */
454 SBIT(AD1CM1, 0xE8, 2); /* ADC 1 CONVERT START MODE BIT 1 */
455 SBIT(AD1CM2, 0xE8, 3); /* ADC 1 CONVERT START MODE BIT 1 */
456 SBIT(AD1BUSY, 0xE8, 4); /* ADC 1 BUSY FLAG */
457 SBIT(AD1INT, 0xE8, 5); /* ADC 1 EOC INTERRUPT FLAG */
458 SBIT(AD1TM, 0xE8, 6); /* ADC 1 TRACK MODE */
459 SBIT(AD1EN, 0xE8, 7); /* ADC 1 ENABLE */
460
461 /* ADC2CN 0xE8 */
462 SBIT(AD2LJST, 0xE8, 0); /* ADC 2 LEFT JUSTIFY SELECT */
463 SBIT(AD2WINT, 0xE8, 1); /* ADC 2 WINDOW INTERRUPT FLAG */
464 SBIT(AD2CM0, 0xE8, 2); /* ADC 2 CONVERT START MODE BIT 0 */
465 SBIT(AD2CM1, 0xE8, 3); /* ADC 2 CONVERT START MODE BIT 1 */
466 SBIT(AD2BUSY, 0xE8, 4); /* ADC 2 BUSY FLAG */
467 SBIT(AD2INT, 0xE8, 5); /* ADC 2 EOC INTERRUPT FLAG */
468 SBIT(AD2TM, 0xE8, 6); /* ADC 2 TRACK MODE */
469 SBIT(AD2EN, 0xE8, 7); /* ADC 2 ENABLE */
470
471 /* P6 0xE8 */
472 SBIT(P6_0, 0xE8, 0);
473 SBIT(P6_1, 0xE8, 1);
474 SBIT(P6_2, 0xE8, 2);
475 SBIT(P6_3, 0xE8, 3);
476 SBIT(P6_4, 0xE8, 4);
477 SBIT(P6_5, 0xE8, 5);
478 SBIT(P6_6, 0xE8, 6);
479 SBIT(P6_7, 0xE8, 7);
480
481 /* SPI0CN 0xF8 */
482 SBIT(SPIEN, 0xF8, 0); /* SPI 0 SPI ENABLE */
483 SBIT(TXBMT, 0xF8, 1); /* SPI 0 TX BUFFER EMPTY FLAG */
484 SBIT(NSSMD0, 0xF8, 2); /* SPI 0 SLAVE SELECT MODE 0 */
485 SBIT(NSSMD1, 0xF8, 3); /* SPI 0 SLAVE SELECT MODE 1 */
486 SBIT(RXOVRN, 0xF8, 4); /* SPI 0 RX OVERRUN FLAG */
487 SBIT(MODF, 0xF8, 5); /* SPI 0 MODE FAULT FLAG */
488 SBIT(WCOL, 0xF8, 6); /* SPI 0 WRITE COLLISION FLAG */
489 SBIT(SPIF, 0xF8, 7); /* SPI 0 INTERRUPT FLAG */
490
491 /* CAN0CN 0xF8 */
492 SBIT(CANINIT, 0xF8, 0); /* CAN INITIALIZATION */
493 SBIT(CANIE, 0xF8, 1); /* CAN MODULE INTERRUPT ENABLE */
494 SBIT(CANSIE, 0xF8, 2); /* CAN STATUS CHANGE INTERRUPT ENABLE */
495 SBIT(CANEIE, 0xF8, 3); /* CAN ERROR INTERRUPT ENABLE */
496 SBIT(CANIF, 0xF8, 4); /* CAN INTERRUPT FLAG */
497 SBIT(CANDAR, 0xF8, 5); /* CAN DISABLE AUTOMATIC RETRANSMISSION */
498 SBIT(CANCCE, 0xF8, 6); /* CAN CONFIGURATION CHANGE ENABLE */
499 SBIT(CANTEST, 0xF8, 7); /* CAN TEST MODE ENABLE */
500
501 /* DMA0CF 0xF8 */
502 SBIT(DMA0EO, 0xF8, 0); /* END-OF-OPERATION FLAG */
503 SBIT(DMA0EOE, 0xF8, 1); /* END-OF-OPERATION INTERRUPT ENABLE */
504 SBIT(DMA0CI, 0xF8, 2); /* REPEAT COUNTER OVERFLOW FLAG */
505 SBIT(DMA0CIE, 0xF8, 3); /* REPEAT COUNTER OVERFLOW INTERRUPT ENABLE */
506 SBIT(DMA0XBY, 0xF8, 6); /* OFF-CHIP XRAM BUSY FLAG */
507 SBIT(DMA0HLT, 0xF8, 7); /* HALT DMA0 OFF-CHIP XRAM ACCESS */
508
509 /* P7 0xF8 */
510 SBIT(P7_0, 0xF8, 0);
511 SBIT(P7_1, 0xF8, 1);
512 SBIT(P7_2, 0xF8, 2);
513 SBIT(P7_3, 0xF8, 3);
514 SBIT(P7_4, 0xF8, 4);
515 SBIT(P7_5, 0xF8, 5);
516 SBIT(P7_6, 0xF8, 6);
517 SBIT(P7_7, 0xF8, 7);
518
519
520 /* Predefined SFR Bit Masks */
521
522 #define IDLE 0x01 /* PCON */
523 #define STOP 0x02 /* PCON */
524 #define ECCF 0x01 /* PCA0CPMn */
525 #define PWM 0x02 /* PCA0CPMn */
526 #define TOG 0x04 /* PCA0CPMn */
527 #define MAT 0x08 /* PCA0CPMn */
528 #define CAPN 0x10 /* PCA0CPMn */
529 #define CAPP 0x20 /* PCA0CPMn */
530 #define ECOM 0x40 /* PCA0CPMn */
531 #define PWM16 0x80 /* PCA0CPMn */
532 #define PORSF 0x02 /* RSTSRC */
533 #define SWRSF 0x10 /* RSTSRC */
534
535
536 /* SFR PAGE DEFINITIONS */
537
538 #define CONFIG_PAGE 0x0F /* SYSTEM AND PORT CONFIGURATION PAGE */
539 #define LEGACY_PAGE 0x00 /* LEGACY SFR PAGE */
540 #define TIMER01_PAGE 0x00 /* TIMER 0 AND TIMER 1 */
541 #define CPT0_PAGE 0x01 /* COMPARATOR 0 */
542 #define CPT1_PAGE 0x02 /* COMPARATOR 1 */
543 #define CPT2_PAGE 0x03 /* COMPARATOR 2 */
544 #define UART0_PAGE 0x00 /* UART 0 */
545 #define UART1_PAGE 0x01 /* UART 1 */
546 #define SPI0_PAGE 0x00 /* SPI 0 */
547 #define EMI0_PAGE 0x00 /* EXTERNAL MEMORY INTERFACE */
548 #define ADC0_PAGE 0x00 /* ADC 0 */
549 #define ADC1_PAGE 0x01 /* ADC 1 */
550 #define ADC2_PAGE 0x02 /* ADC 2 */
551 #define SMB0_PAGE 0x00 /* SMBUS 0 */
552 #define TMR2_PAGE 0x00 /* TIMER 2 */
553 #define TMR3_PAGE 0x01 /* TIMER 3 */
554 #define TMR4_PAGE 0x02 /* TIMER 4 */
555 #define DAC0_PAGE 0x00 /* DAC 0 */
556 #define DAC1_PAGE 0x01 /* DAC 1 */
557 #define PCA0_PAGE 0x00 /* PCA 0 */
558 #define DMA0_PAGE 0x03 /* DMA 0 */
559 #define CAN0_PAGE 0x01 /* CAN 0 */
560
561 #endif
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