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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / C8051F300.h
blobce15e887b62f7948efa227d8a280488b2eed613e
1 /*-------------------------------------------------------------------------
2 C8051F300.h - Register Declarations for the Cygnal/SiLabs C8051F30x
3 Processor Range
4
5 Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30
31 #ifndef C8051F300_H
32 #define C8051F300_H
33
34
35 /* BYTE Registers */
36
37 __sfr __at (0x80) P0 ; /* PORT 0 */
38 __sfr __at (0x81) SP ; /* STACK POINTER */
39 __sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
40 __sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
41 __sfr __at (0x87) PCON ; /* POWER CONTROL */
42 __sfr __at (0x88) TCON ; /* TIMER CONTROL */
43 __sfr __at (0x89) TMOD ; /* TIMER MODE */
44 __sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
45 __sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
46 __sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
47 __sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
48 __sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
49 __sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
50 __sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
51 __sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
52 __sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
53 __sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
54 __sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
55 __sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
56 __sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
57 __sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
58 __sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
59 __sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
60 __sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
61 __sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
62 __sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
63 __sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
64 __sfr __at (0xBB) AMX0SL ; /* ADC 0 MUX CHANNEL SELECTION */
65 __sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
66 __sfr __at (0xBE) ADC0 ; /* ADC 0 DATA */
67 __sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
68 __sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
69 __sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
70 __sfr __at (0xC4) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER */
71 __sfr __at (0xC6) ADC0LT ; /* ADC 0 LESS-THAN REGISTER */
72 __sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
73 __sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
74 __sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
75 __sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
76 __sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
77 __sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
78 __sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
79 __sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
80 __sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
81 __sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
82 __sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
83 __sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
84 __sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
85 __sfr __at (0xD9) PCA0MD ; /* PCA MODE */
86 __sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
87 __sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
88 __sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
89 __sfr __at (0xE0) ACC ; /* ACCUMULATOR */
90 __sfr __at (0xE1) PRT0MX ; /* PORT MUX CONFIGURATION REGISTER 0 */
91 __sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
92 __sfr __at (0xE2) PRT1MX ; /* PORT MUX CONFIGURATION REGISTER 1 */
93 __sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
94 __sfr __at (0xE3) PRT2MX ; /* PORT MUX CONFIGURATION REGISTER 2 */
95 __sfr __at (0xE3) XBR2 ; /* PORT MUX CONFIGURATION REGISTER 2 */
96 __sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
97 __sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
98 __sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
99 __sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
100 __sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
101 __sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
102 __sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
103 __sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
104 __sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
105 __sfr __at (0xF0) B ; /* B REGISTER */
106 __sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
107 __sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
108 __sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
109 __sfr __at (0xF8) CPT0CN ; /* COMPARATOR 0 CONTROL */
110 __sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
111 __sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
112 __sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
113 __sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
114
115
116 /* WORD/DWORD Registers */
117
118 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
119 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
120 __sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
121 __sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
122 __sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
123 __sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
124 __sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
125 __sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
126 __sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
127
128
129 /* BIT Registers */
130
131 /* P0 0x80 */
132 __sbit __at (0x80) P0_0 ;
133 __sbit __at (0x81) P0_1 ;
134 __sbit __at (0x82) P0_2 ;
135 __sbit __at (0x83) P0_3 ;
136 __sbit __at (0x84) P0_4 ;
137 __sbit __at (0x85) P0_5 ;
138 __sbit __at (0x86) P0_6 ;
139 __sbit __at (0x87) P0_7 ;
140
141 /* TCON 0x88 */
142 __sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
143 __sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
144 __sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
145 __sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
146 __sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
147 __sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
148 __sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
149 __sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
150
151 /* SCON 0x98 */
152 __sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
153 __sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
154 __sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
155 __sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
156 __sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
157 __sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
158 __sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
159 __sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
160 __sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
161 __sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
162 __sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
163 __sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
164 __sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
165 __sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
166
167 /* IE 0xA8 */
168 __sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
169 __sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
170 __sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
171 __sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
172 __sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
173 __sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
174 __sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
175 __sbit __at (0xAE) IEGF0 ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
176 __sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
177
178 /* IP 0xB8 */
179 __sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
180 __sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
181 __sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
182 __sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
183 __sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
184 __sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
185 __sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
186
187 /* SMB0CN 0xC0 */
188 __sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
189 __sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
190 __sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
191 __sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
192 __sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
193 __sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
194 __sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
195 __sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
196
197 /* TMR2CN 0xC8 */
198 __sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
199 __sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
200 __sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
201 __sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
202 __sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
203 __sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
204 __sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
205
206 /* PSW 0xD0 */
207 __sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
208 __sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
209 __sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
210 __sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
211 __sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
212 __sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
213 __sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
214 __sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
215
216 /* PCA0CN 0xD8 */
217 __sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
218 __sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
219 __sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
220 __sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
221 __sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
222
223 /* ADC0CN 0xE8 */
224 __sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
225 __sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
226 __sbit __at (0xEA) AD0CM2 ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
227 __sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
228 __sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
229 __sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
230 __sbit __at (0xEE) AD0TM ; /* ADC0CN.6 - ADC 0 TRACK MODE */
231 __sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
232
233 /* CPT0CN 0xF8 */
234 __sbit __at (0xF8) CP0HYN0 ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
235 __sbit __at (0xF9) CP0HYN1 ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
236 __sbit __at (0xFA) CP0HYP0 ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
237 __sbit __at (0xFB) CP0HYP1 ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
238 __sbit __at (0xFC) CP0FIF ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
239 __sbit __at (0xFD) CP0RIF ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
240 __sbit __at (0xFE) CP0OUT ; /* CPT0CN.6 - Comparator0 Output State Flag */
241 __sbit __at (0xFF) CP0EN ; /* CPT0CN.7 - Comparator0 Enable Bit */
242
243
244 /* Predefined SFR Bit Masks */
245
246 #define PCON_IDLE 0x01 /* PCON */
247 #define PCON_STOP 0x02 /* PCON */
248 #define T1M 0x10 /* CKCON */
249 #define PSWE 0x01 /* PSCTL */
250 #define PSEE 0x02 /* PSCTL */
251 #define ECP0F 0x10 /* EIE1 */
252 #define ECP0R 0x20 /* EIE1 */
253 #define PORSF 0x02 /* RSTSRC */
254 #define SWRSF 0x10 /* RSTSRC */
255 #define ECCF 0x01 /* PCA0CPMn */
256 #define PWM 0x02 /* PCA0CPMn */
257 #define TOG 0x04 /* PCA0CPMn */
258 #define MAT 0x08 /* PCA0CPMn */
259 #define CAPN 0x10 /* PCA0CPMn */
260 #define CAPP 0x20 /* PCA0CPMn */
261 #define ECOM 0x40 /* PCA0CPMn */
262 #define PWM16 0x80 /* PCA0CPMn */
263 #define CP0E 0x10 /* XBR1 */
264 #define CP0OEN 0x10 /* XBR1 */
265 #define CP0AE 0x20 /* XBR1 */
266 #define CP0AOEN 0x20 /* XBR1 */
267
268 #endif
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