sdcc/device/include/mcs51/C8051F326.h

   1 /*-------------------------------------------------------------------------
   2    C8051F326.h - Register Declarations for the Cygnal/SiLabs C8051F326/7
   3    Processor Range
   4
   5    Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef C8051F326_H
  31 #define C8051F326_H
  32
  33
  34 /*  BYTE Registers  */
  35 __sfr __at (0x80) P0           ;  /* PORT 0                                        */
  36 __sfr __at (0x81) SP           ;  /* STACK POINTER                                 */
  37 __sfr __at (0x82) DPL          ;  /* DATA POINTER - LOW BYTE                       */
  38 __sfr __at (0x83) DPH          ;  /* DATA POINTER - HIGH BYTE                      */
  39 __sfr __at (0x87) PCON         ;  /* POWER CONTROL                                 */
  40 __sfr __at (0x88) TCON         ;  /* TIMER CONTROL                                 */
  41 __sfr __at (0x89) TMOD         ;  /* TIMER MODE                                    */
  42 __sfr __at (0x8A) TL0          ;  /* TIMER 0 - LOW BYTE                            */
  43 __sfr __at (0x8B) TL1          ;  /* TIMER 1 - LOW BYTE                            */
  44 __sfr __at (0x8C) TH0          ;  /* TIMER 0 - HIGH BYTE                           */
  45 __sfr __at (0x8D) TH1          ;  /* TIMER 1 - HIGH BYTE                           */
  46 __sfr __at (0x8E) CKCON        ;  /* CLOCK CONTROL                                 */
  47 __sfr __at (0x8F) PSCTL        ;  /* PROGRAM STORE R/W CONTROL                     */
  48 __sfr __at (0x91) SBCON0       ;  /* BAUDRATE GENERATOR 0 CONTROL                  */
  49 __sfr __at (0x93) SBRLL0       ;  /* BAUDRATE GENERATOR 0 RELOAD VALUE - LOW BYTE  */
  50 __sfr __at (0x94) SBRLH0       ;  /* BAUDRATE GENERATOR 0 RELOAD VALUE - HIGH BYTE */
  51 __sfr __at (0x96) USB0ADR      ;  /* USB0 INDIRECT ADDRESS REGISTER                */
  52 __sfr __at (0x97) USB0DAT      ;  /* USB0 DATA REGISTER                            */
  53 __sfr __at (0x98) SCON         ;  /* UART0 CONTROL                                 */
  54 __sfr __at (0x98) SCON0        ;  /* UART0 CONTROL                                 */
  55 __sfr __at (0x99) SBUF         ;  /* UART0 BUFFER                                  */
  56 __sfr __at (0x99) SBUF0        ;  /* UART0 BUFFER                                  */
  57 __sfr __at (0x9A) SMOD0        ;  /* UART0 MODE                                    */
  58 __sfr __at (0xA0) P2           ;  /* PORT 2                                        */
  59 __sfr __at (0xA4) P0MDOUT      ;  /* PORT 0 OUTPUT MODE CONFIGURATION              */
  60 __sfr __at (0xA6) P2MDOUT      ;  /* PORT 2 OUTPUT MODE CONFIGURATION              */
  61 __sfr __at (0xA7) P3MDOUT      ;  /* PORT 3 OUTPUT MODE CONFIGURATION              */
  62 __sfr __at (0xA8) IE           ;  /* INTERRUPT ENABLE                              */
  63 __sfr __at (0xA9) CLKSEL       ;  /* SYSTEM CLOCK SELECT                           */
  64 __sfr __at (0xAA) EMI0CN       ;  /* EXTERNAL MEMORY INTERFACE CONTROL             */
  65 __sfr __at (0xAA) _XPAGE       ;  /* XDATA/PDATA PAGE                              */
  66 __sfr __at (0xB0) P3           ;  /* PORT 3                                        */
  67 __sfr __at (0xB2) OSCICN       ;  /* INTERNAL OSCILLATOR CONTROL                   */
  68 __sfr __at (0xB3) OSCICL       ;  /* INTERNAL OSCILLATOR CALIBRATION               */
  69 __sfr __at (0xB6) FLSCL        ;  /* FLASH MEMORY TIMING PRESCALER                 */
  70 __sfr __at (0xB7) FLKEY        ;  /* FLASH ACESS LIMIT                             */
  71 __sfr __at (0xB8) IP           ;  /* INTERRUPT PRIORITY                            */
  72 __sfr __at (0xB9) CLKMUL       ;  /* CLOCK MULTIPLIER CONTROL REGISTER             */
  73 __sfr __at (0xC9) REG0CN       ;  /* VOLTAGE REGULATOR CONTROL                     */
  74 __sfr __at (0xD0) PSW          ;  /* PROGRAM STATUS WORD                           */
  75 __sfr __at (0xD7) USB0XCN      ;  /* USB0 TRANSCEIVER CONTROL                      */
  76 __sfr __at (0xE0) ACC          ;  /* ACCUMULATOR                                   */
  77 __sfr __at (0xE2) GPIOCN       ;  /* GLOBAL PORT I/O CONTROL                       */
  78 __sfr __at (0xE3) OSCLCN       ;  /* LOW-FREQUENCY OSCILLATOR CONTROL              */
  79 __sfr __at (0xE6) EIE1         ;  /* EXTERNAL INTERRUPT ENABLE 1                   */
  80 __sfr __at (0xE7) EIE2         ;  /* EXTERNAL INTERRUPT ENABLE 2                   */
  81 __sfr __at (0xEF) RSTSRC       ;  /* RESET SOURCE                                  */
  82 __sfr __at (0xF0) B            ;  /* B REGISTER                                    */
  83 __sfr __at (0xF6) EIP1         ;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 1        */
  84 __sfr __at (0xF7) EIP2         ;  /* EXTERNAL INTERRUPT PRIORITY REGISTER 2        */
  85 __sfr __at (0xFF) VDM0CN       ;  /* VDD MONITOR CONTROL                           */
  86
  87
  88 /*  WORD/DWORD Registers  */
  89
  90 __sfr16 __at (0x8C8A) TMR0     ;  /* TIMER 0 COUNTER                               */
  91 __sfr16 __at (0x8D8B) TMR1     ;  /* TIMER 1 COUNTER                               */
  92 __sfr16 __at (0x9493) SBRL0    ;  /* BAUDRATE GENERATOR 0 RELOAD VALUE WORD        */
  93
  94
  95 /*  BIT Registers  */
  96
  97 /*  P0  0x80 */
  98 __sbit __at (0x80) P0_0        ;
  99 __sbit __at (0x81) P0_1        ;
 100 __sbit __at (0x82) P0_2        ;
 101 __sbit __at (0x83) P0_3        ;
 102 __sbit __at (0x84) P0_4        ;
 103 __sbit __at (0x85) P0_5        ;
 104 __sbit __at (0x86) P0_6        ;
 105 __sbit __at (0x87) P0_7        ;
 106
 107 /*  TCON  0x88 */
 108 __sbit __at (0x88) IT0         ;  /* TCON.0 - EXT. INTERRUPT 0 TYPE                */
 109 __sbit __at (0x89) IE0         ;  /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG           */
 110 __sbit __at (0x8A) IT1         ;  /* TCON.2 - EXT. INTERRUPT 1 TYPE                */
 111 __sbit __at (0x8B) IE1         ;  /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG           */
 112 __sbit __at (0x8C) TR0         ;  /* TCON.4 - TIMER 0 ON/OFF CONTROL               */
 113 __sbit __at (0x8D) TF0         ;  /* TCON.5 - TIMER 0 OVERFLOW FLAG                */
 114 __sbit __at (0x8E) TR1         ;  /* TCON.6 - TIMER 1 ON/OFF CONTROL               */
 115 __sbit __at (0x8F) TF1         ;  /* TCON.7 - TIMER 1 OVERFLOW FLAG                */
 116
 117 /*  SCON  0x98 */
 118 __sbit __at (0x98) RI          ;  /* SCON.0 - RECEIVE INTERRUPT FLAG               */
 119 __sbit __at (0x98) RI0         ;  /* SCON.0 - RECEIVE INTERRUPT FLAG               */
 120 __sbit __at (0x99) TI          ;  /* SCON.1 - TRANSMIT INTERRUPT FLAG              */
 121 __sbit __at (0x99) TI0         ;  /* SCON.1 - TRANSMIT INTERRUPT FLAG              */
 122 __sbit __at (0x9A) RB8         ;  /* SCON.2 - RECEIVE BIT 8                        */
 123 __sbit __at (0x9A) RBX0        ;  /* SCON.2 - EXTRA RECEIVE BIT                    */
 124 __sbit __at (0x9B) TB8         ;  /* SCON.3 - TRANSMIT BIT 8                       */
 125 __sbit __at (0x9B) TBX0        ;  /* SCON.3 - EXTRA TRANSMIT BIT                   */
 126 __sbit __at (0x9C) REN         ;  /* SCON.4 - RECEIVE ENABLE                       */
 127 __sbit __at (0x9C) REN0        ;  /* SCON.4 - RECEIVE ENABLE                       */
 128 __sbit __at (0x9E) PERR0       ;  /* SCON.6 - PARITY ERROR FLAG                    */
 129 __sbit __at (0x9F) OVR0        ;  /* SCON.7 - RECEIVE FIFO OVERRUN FLAG            */
 130
 131 /*  P2  0xA0 */
 132 __sbit __at (0xA0) P2_0        ;
 133 __sbit __at (0xA1) P2_1        ;
 134 __sbit __at (0xA2) P2_2        ;
 135 __sbit __at (0xA3) P2_3        ;
 136 __sbit __at (0xA4) P2_4        ;
 137 __sbit __at (0xA5) P2_5        ;
 138
 139 /*  IE  0xA8 */
 140 __sbit __at (0xA8) EX0         ;  /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE            */
 141 __sbit __at (0xA9) ET0         ;  /* IE.1 - TIMER 0 INTERRUPT ENABLE               */
 142 __sbit __at (0xAA) EX1         ;  /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE            */
 143 __sbit __at (0xAB) ET1         ;  /* IE.3 - TIMER 1 INTERRUPT ENABLE               */
 144 __sbit __at (0xAC) ES          ;  /* IE.4 - SERIAL PORT INTERRUPT ENABLE           */
 145 __sbit __at (0xAC) ES0         ;  /* IE.4 - SERIAL PORT INTERRUPT ENABLE           */
 146 __sbit __at (0xAF) EA          ;  /* IE.7 - GLOBAL INTERRUPT ENABLE                */
 147
 148 /*  P3  0xB0 */
 149 __sbit __at (0xB0) P3_0        ;
 150
 151 /*  IP  0xB8 */
 152 __sbit __at (0xB8) PX0         ;  /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY          */
 153 __sbit __at (0xB9) PT0         ;  /* IP.1 - TIMER 0 PRIORITY                       */
 154 __sbit __at (0xBA) PX1         ;  /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY          */
 155 __sbit __at (0xBB) PT1         ;  /* IP.3 - TIMER 1 PRIORITY                       */
 156 __sbit __at (0xBC) PS          ;  /* IP.4 - SERIAL PORT PRIORITY                   */
 157 __sbit __at (0xBC) PS0         ;  /* IP.4 - SERIAL PORT PRIORITY                   */
 158
 159 /*  PSW  0xD0 */
 160 __sbit __at (0xD0) PARITY      ;  /* PSW.0 - ACCUMULATOR PARITY FLAG               */
 161 __sbit __at (0xD1) F1          ;  /* PSW.1 - FLAG 1                                */
 162 __sbit __at (0xD2) OV          ;  /* PSW.2 - OVERFLOW FLAG                         */
 163 __sbit __at (0xD3) RS0         ;  /* PSW.3 - REGISTER BANK SELECT 0                */
 164 __sbit __at (0xD4) RS1         ;  /* PSW.4 - REGISTER BANK SELECT 1                */
 165 __sbit __at (0xD5) F0          ;  /* PSW.5 - FLAG 0                                */
 166 __sbit __at (0xD6) AC          ;  /* PSW.6 - AUXILIARY CARRY FLAG                  */
 167 __sbit __at (0xD7) CY          ;  /* PSW.7 - CARRY FLAG                            */
 168
 169
 170 /* Predefined SFR Bit Masks */
 171
 172 #define PCON_IDLE         0x01    /* PCON                                */
 173 #define PCON_STOP         0x02    /* PCON                                */
 174 #define T0M               0x04    /* CKCON                               */
 175 #define T1M               0x08    /* CKCON                               */
 176 #define PSWE              0x01    /* PSCTL                               */
 177 #define PSEE              0x02    /* PSCTL                               */
 178 #define EUSB0             0x02    /* EIE1                                */
 179 #define EVBUS             0x01    /* EIE2                                */
 180 #define PORSF             0x02    /* RSTSRC                              */
 181 #define SWRSF             0x10    /* RSTSRC                              */
 182
 183 #endif