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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / C8051F336.h
blobbcb78c942443111b2fe980abf31821459eea1a02
1 /*-------------------------------------------------------------------------
2 C8051F336.h - Register Declarations for the SiLabs C8051F336/7/8/9
3 Processor Range
4
5 Copyright (C) 2008, Steven Borley, steven.borley@partnerelectronics.com
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 #ifndef C8051F336_H
31 #define C8051F336_H
32
33 #include <compiler.h>
34
35 /* BYTE Registers */
36
37 SFR( P0, 0x80 ) ; /* PORT 0 */
38 SFR( SP, 0x81 ) ; /* STACK POINTER */
39 SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
40 SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
41 SFR( PCON, 0x87 ) ; /* POWER CONTROL */
42 SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
43 SFR( TMOD, 0x89 ) ; /* TIMER MODE */
44 SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
45 SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
46 SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
47 SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
48 SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
49 SFR( PSCTL, 0x8F ) ; /* PROGRAM STORE R/W CONTROL */
50 SFR( P1, 0x90 ) ; /* PORT 1 */
51 SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */
52 SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
53 SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
54 SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */
55 SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */
56 SFR( IDA0L, 0x96 ) ; /* CURRENT MODE DAC 0 - LOW BYTE */
57 SFR( IDA0H, 0x97 ) ; /* CURRENT MODE DAC 0 - HIGH BYTE */
58 SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */
59 SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */
60 SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */
61 SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */
62 SFR( CPT0CN, 0x9B ) ; /* COMPARATOR 0 CONTROL */
63 SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */
64 SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */
65 SFR( P2, 0xA0 ) ; /* PORT 2 */
66 SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */
67 SFR( SPI0CKR, 0xA2 ) ; /* SPI0 CLOCK RATE CONTROL */
68 SFR( SPI0DAT, 0xA3 ) ; /* SPI0 DATA */
69 SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
70 SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */
71 SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */
72 SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
73 SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */
74 SFR( EMI0CN, 0xAA ) ; /* EXTERNAL MEMORY INTERFACE CONTROL */
75 SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA PAGE */
76 SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
77 SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
78 SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
79 SFR( FLSCL, 0xB6 ) ; /* FLASH MEMORY TIMING PRESCALER */
80 SFR( FLKEY, 0xB7 ) ; /* FLASH ACESS LIMIT */
81 SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
82 SFR( IDA0CN, 0xB9 ) ; /* CURRENT MODE DAC 0 - CONTROL */
83 SFR( AMX0N, 0xBA ) ; /* ADC 0 MUX NEGATIVE CHANNEL SELECTION */
84 SFR( AMX0P, 0xBB ) ; /* ADC 0 MUX POSITIVE CHANNEL SELECTION */
85 SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
86 SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA WORD LSB */
87 SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA WORD MSB */
88 SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
89 SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
90 SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
91 SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN LOW BYTE */
92 SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN HIGH BYTE */
93 SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN LOW BYTE */
94 SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN HIGH BYTE */
95 SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */
96 SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */
97 SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
98 SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
99 SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
100 SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
101 SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */
102 SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */
103 SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
104 SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
105 SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
106 SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
107 SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */
108 SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */
109 SFR( P2SKIP, 0xD6 ) ; /* PORT 2 SKIP */
110 SFR( SMB0ADR, 0xD7 ) ; /* SMBUS SLAVE ADDRESS */
111 SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
112 SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
113 SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */
114 SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */
115 SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */
116 SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
117 SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
118 SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
119 SFR( OSCLCN, 0xE3 ) ; /* LOW-FREQUENCY OSCILLATOR CONTROL */
120 SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
121 SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
122 SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
123 SFR( SMB0ADM, 0xE7 ) ; /* SMBUS SLAVE ADDRESS MASK */
124 SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
125 SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
126 SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
127 SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
128 SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
129 SFR( P1MAT, 0xED ) ; /* PORT 1 MATCH REGISTER */
130 SFR( P1MASK, 0xEE ) ; /* PORT 1 MASK REGISTER */
131 SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
132 SFR( B, 0xF0 ) ; /* B REGISTER */
133 SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
134 SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
135 SFR( P1MODE, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
136 SFR( P1MDIN, 0xF2 ) ; /* PORT 1 INPUT MODE CONFIGURATION */
137 SFR( P2MDIN, 0xF3 ) ; /* PORT 2 INPUT MODE */
138 SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
139 SFR( PCA0PWM, 0xF7 ) ; /* PCA PWM CONFIGURATION */
140 SFR( SPI0CN, 0xF8 ) ; /* SPI0 CONTROL */
141 SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
142 SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
143 SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
144 SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
145 SFR( P0MAT, 0xFD ) ; /* PORT 0 MATCH REGISTER */
146 SFR( P0MASK, 0xFE ) ; /* PORT 0 MASK REGISTER */
147 SFR( VDM0CN, 0xFF ) ; /* VDD MONITOR CONTROL */
148
149
150 /* WORD/DWORD Registers */
151
152 SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
153 SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
154 SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */
155 SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
156 SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
157 SFR16E( TMR3, 0x9594 ) ; /* TIMER 3 COUNTER */
158 SFR16E( TMR3RL, 0x9392 ) ; /* TIMER 3 CAPTURE REGISTER WORD */
159 SFR16E( IDA0, 0x9796 ) ; /* CURRENT MODE DAC 0 DATA WORD */
160 SFR16E( ADC0, 0xBEBD ) ; /* ADC 0 DATA WORD */
161 SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
162 SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
163 SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */
164 SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */
165 SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */
166 SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */
167
168
169 /* BIT Registers */
170
171 /* P0 0x80 */
172 SBIT( P0_0, 0x80, 0 ) ;
173 SBIT( P0_1, 0x80, 1 ) ;
174 SBIT( P0_2, 0x80, 2 ) ;
175 SBIT( P0_3, 0x80, 3 ) ;
176 SBIT( P0_4, 0x80, 4 ) ;
177 SBIT( P0_5, 0x80, 5 ) ;
178 SBIT( P0_6, 0x80, 6 ) ;
179 SBIT( P0_7, 0x80, 7 ) ;
180
181 /* TCON 0x88 */
182 SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
183 SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
184 SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
185 SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
186 SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
187 SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
188 SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
189 SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
190
191 /* P1 0x90 */
192 SBIT( P1_0, 0x90, 0 ) ;
193 SBIT( P1_1, 0x90, 1 ) ;
194 SBIT( P1_2, 0x90, 2 ) ;
195 SBIT( P1_3, 0x90, 3 ) ;
196 SBIT( P1_4, 0x90, 4 ) ;
197 SBIT( P1_5, 0x90, 5 ) ;
198 SBIT( P1_6, 0x90, 6 ) ;
199 SBIT( P1_7, 0x90, 7 ) ;
200
201 /* SCON 0x98 */
202 SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
203 SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
204 SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
205 SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
206 SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
207 SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
208 SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
209 SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
210 SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
211 SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
212 SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
213 SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
214 SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
215 SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
216
217 /* P2 0xA0 */
218 SBIT( P2_0, 0xA0, 0 ) ;
219 SBIT( P2_1, 0xA0, 1 ) ;
220 SBIT( P2_2, 0xA0, 2 ) ;
221 SBIT( P2_3, 0xA0, 3 ) ;
222 SBIT( P2_4, 0xA0, 4 ) ;
223 SBIT( P2_5, 0xA0, 5 ) ;
224 SBIT( P2_6, 0xA0, 6 ) ;
225 SBIT( P2_7, 0xA0, 7 ) ;
226
227 /* IE 0xA8 */
228 SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
229 SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
230 SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
231 SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
232 SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
233 SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
234 SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
235 SBIT( ESPI0, 0xA8, 6 ) ; /* IE.6 - SPI0 INTERRUPT ENABLE */
236 SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
237
238 /* IP 0xB8 */
239 SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
240 SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
241 SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
242 SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
243 SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
244 SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
245 SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
246 SBIT( PSPI0, 0xB8, 6 ) ; /* IP.6 - SPI0 PRIORITY */
247
248 /* SMB0CN 0xC0 */
249 SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
250 SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
251 SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
252 SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
253 SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
254 SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
255 SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
256 SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
257
258 /* TMR2CN 0xC8 */
259 SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
260 SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
261 SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
262 SBIT( TF2CEN, 0xC8, 4 ) ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
263 SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
264 SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
265 SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
266 SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
267
268 /* PSW 0xD0 */
269 SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
270 SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
271 SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
272 SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
273 SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
274 SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
275 SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
276 SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
277
278 /* PCA0CN 0xD8 */
279 SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
280 SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
281 SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
282 SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
283 SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
284
285 /* ADC0CN 0xE8 */
286 SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
287 SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
288 SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
289 SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
290 SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
291 SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
292 SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
293 SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
294
295 /* SPI0CN 0xF8 */
296 SBIT( SPIEN, 0xF8, 0 ) ; /* SPI0CN.0 - SPI0 ENABLE */
297 SBIT( TXBMT, 0xF8, 1 ) ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
298 SBIT( NSSMD0, 0xF8, 2 ) ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
299 SBIT( NSSMD1, 0xF8, 3 ) ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
300 SBIT( RXOVRN, 0xF8, 4 ) ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
301 SBIT( MODF, 0xF8, 5 ) ; /* SPI0CN.5 - MODE FAULT FLAG */
302 SBIT( WCOL, 0xF8, 6 ) ; /* SPI0CN.6 - WRITE COLLISION FLAG */
303 SBIT( SPIF, 0xF8, 7 ) ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
304
305
306 /* Predefined SFR Bit Masks */
307
308 #define PCON_IDLE 0x01 /* PCON */
309 #define PCON_STOP 0x02 /* PCON */
310 #define T1M 0x08 /* CKCON */
311 #define PSWE 0x01 /* PSCTL */
312 #define PSEE 0x02 /* PSCTL */
313 #define ECP0 0x20 /* EIE1 */
314 #define PORSF 0x02 /* RSTSRC */
315 #define SWRSF 0x10 /* RSTSRC */
316 #define ECCF 0x01 /* PCA0CPMn */
317 #define PWM 0x02 /* PCA0CPMn */
318 #define TOG 0x04 /* PCA0CPMn */
319 #define MAT 0x08 /* PCA0CPMn */
320 #define CAPN 0x10 /* PCA0CPMn */
321 #define CAPP 0x20 /* PCA0CPMn */
322 #define ECOM 0x40 /* PCA0CPMn */
323 #define PWM16 0x80 /* PCA0CPMn */
324 #define CP0E 0x10 /* XBR0 */
325 #define CP0OEN 0x10 /* XBR0 */
326 #define CP0AE 0x20 /* XBR0 */
327 #define CP0AOEN 0x20 /* XBR0 */
328
329 /* Interrupts */
330
331 #define INT_EXT0 0 /* External Interrupt 0 */
332 #define INT_TIMER0 1 /* Timer0 Overflow */
333 #define INT_EXT1 2 /* External Interrupt 1 */
334 #define INT_TIMER1 3 /* Timer1 Overflow */
335 #define INT_UART0 4 /* Serial Port 0 */
336 #define INT_TIMER2 5 /* Timer2 Overflow */
337 #define INT_SPI0 6 /* Serial Peripheral Interface 0 */
338 #define INT_SMBUS0 7 /* SMBus0 Interface */
339 #define INT_PMAT 8 /* Port match */
340 #define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */
341 #define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */
342 #define INT_PCA0 11 /* PCA0 Peripheral */
343 #define INT_COMPARATOR0 12 /* Comparator0 */
344 /* 13 Reserved */
345 #define INT_TIMER3 14 /* Timer3 Overflow */
346
347 #endif
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