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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / C8051F350.h
blob00c980937a3fa4e71fddd68cff3e053caae7571a
1 /*-------------------------------------------------------------------------
2 C8051F350.h - Register Declarations for the SiLabs C8051F35x
3 Processor Range
4
5 Copyright (C) 2004, Maarten Brock, sourceforge.brock@dse.nl
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 #ifndef C8051F350_H
31 #define C8051F350_H
32
33
34 /* BYTE Registers */
35
36 __sfr __at (0x80) P0 ; /* PORT 0 */
37 __sfr __at (0x81) SP ; /* STACK POINTER */
38 __sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
39 __sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
40 __sfr __at (0x87) PCON ; /* POWER CONTROL */
41 __sfr __at (0x88) TCON ; /* TIMER CONTROL */
42 __sfr __at (0x89) TMOD ; /* TIMER MODE */
43 __sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
44 __sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
45 __sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
46 __sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
47 __sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
48 __sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
49 __sfr __at (0x90) P1 ; /* PORT 1 */
50 __sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
51 __sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
52 __sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
53 __sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
54 __sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
55 __sfr __at (0x96) IDA0 ; /* CURRENT MODE DAC 0 */
56 __sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
57 __sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
58 __sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
59 __sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
60 __sfr __at (0x9A) ADC0DECL ; /* ADC DECIMATION LOW */
61 __sfr __at (0x9B) ADC0DECH ; /* ADC DECIMATION HIGH */
62 __sfr __at (0x9C) CPT0CN ; /* COMPARATOR 0 CONTROL */
63 __sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
64 __sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
65 __sfr __at (0xA0) P2 ; /* PORT 2 */
66 __sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
67 __sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
68 __sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
69 __sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
70 __sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
71 __sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
72 __sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
73 __sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
74 __sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
75 __sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
76 __sfr __at (0xAB) ADC0CGL ; /* ADC 0 GAIN CALIBRATION LOW */
77 __sfr __at (0xAC) ADC0CGM ; /* ADC 0 GAIN CALIBRATION MIDDLE */
78 __sfr __at (0xAD) ADC0CGH ; /* ADC 0 GAIN CALIBRATION HIGH */
79 __sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
80 __sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
81 __sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
82 __sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
83 __sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
84 __sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
85 __sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
86 __sfr __at (0xBA) ADC0COL ; /* ADC 0 OFFSET CALIBRATION LOW */
87 __sfr __at (0xBB) ADC0COM ; /* ADC 0 OFFSET CALIBRATION MIDDLE */
88 __sfr __at (0xBC) ADC0COH ; /* ADC 0 OFFSET CALIBRATION HIGH */
89 __sfr __at (0xBD) ADC0BUF ; /* ADC 0 BUFFER CONTROL */
90 __sfr __at (0xBE) CLKMUL ; /* CLOCK MULTIPLIER */
91 __sfr __at (0xBF) ADC0DAC ; /* ADC 0 OFFSET DAC */
92 __sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
93 __sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
94 __sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
95 __sfr __at (0xC3) ADC0L ; /* ADC 0 OUTPUT LOW BYTE */
96 __sfr __at (0xC4) ADC0M ; /* ADC 0 OUTPUT MIDDLE BYTE */
97 __sfr __at (0xC5) ADC0H ; /* ADC 0 OUTPUT HIGH BYTE */
98 __sfr __at (0xC6) ADC0MUX ; /* ADC 0 MULTIPLEXER */
99 __sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
100 __sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
101 __sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
102 __sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
103 __sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
104 __sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
105 __sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
106 __sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
107 __sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
108 __sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
109 __sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
110 __sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
111 __sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
112 __sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
113 __sfr __at (0xD7) IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */
114 __sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
115 __sfr __at (0xD9) PCA0MD ; /* PCA MODE */
116 __sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
117 __sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
118 __sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
119 __sfr __at (0xDD) IDA1 ; /* CURRENT MODE DAC 1 */
120 __sfr __at (0xE0) ACC ; /* ACCUMULATOR */
121 __sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
122 __sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
123 __sfr __at (0xE3) PFE0CN ; /* PREFETCH ENGINE CONTROL */
124 __sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
125 __sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
126 __sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
127 __sfr __at (0xE8) ADC0STA ; /* ADC 0 STATUS */
128 __sfr __at (0xE9) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
129 __sfr __at (0xEA) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
130 __sfr __at (0xEB) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
131 __sfr __at (0xEC) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
132 __sfr __at (0xED) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
133 __sfr __at (0xEE) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
134 __sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
135 __sfr __at (0xF0) B ; /* B REGISTER */
136 __sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
137 __sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
138 __sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
139 __sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
140 __sfr __at (0xF3) ADC0MD ; /* ADC 0 MODE */
141 __sfr __at (0xF4) ADC0CN ; /* ADC 0 CONTROL */
142 __sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
143 __sfr __at (0xF7) ADC0CLK ; /* ADC 0 CLOCK */
144 __sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
145 __sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
146 __sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
147 __sfr __at (0xFB) ADC0CF ; /* ADC 0 CONFIGURATION */
148 __sfr __at (0xFC) ADC0FL ; /* ADC 0 FAST FILTER OUTPUT LOW */
149 __sfr __at (0xFD) ADC0FM ; /* ADC 0 FAST FILTER OUTPUT MIDDLE */
150 __sfr __at (0xFE) ADC0FH ; /* ADC 0 FAST FILTER OUTPUT HIGH */
151 __sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
152
153
154 /* WORD/DWORD Registers */
155
156 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
157 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
158 __sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
159 __sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
160 __sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
161 __sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
162 __sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
163
164 __sfr16 __at (0x9B9A) ADC0DEC ; /* ADC 0 DECIMATION RATIO REGISTER WORD */
165 /* Unfortunately the C8051F350 does not have an sfr that always reads 0x00 and */
166 /* ignores what is written to it. That could have enabled sfr32 definitions for */
167 /* the 24 bit ADC0 sfr combinations. */
168 __sfr16 __at (0xC5C4) ADC0 ; /* 16 bit ADC 0 SINC3 FILTER OUTPUT WORD */
169 __sfr16 __at (0xFEFD) ADC0F ; /* 16 bit ADC 0 FAST FILTER OUTPUT WORD */
170
171 __sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
172 __sfr16 __at (0xEAE9) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
173 __sfr16 __at (0xECEB) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
174 __sfr16 __at (0xEEED) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
175
176
177 /* BIT Registers */
178
179 /* P0 0x80 */
180 __sbit __at (0x80) P0_0 ;
181 __sbit __at (0x81) P0_1 ;
182 __sbit __at (0x82) P0_2 ;
183 __sbit __at (0x83) P0_3 ;
184 __sbit __at (0x84) P0_4 ;
185 __sbit __at (0x85) P0_5 ;
186 __sbit __at (0x86) P0_6 ;
187 __sbit __at (0x87) P0_7 ;
188
189 /* TCON 0x88 */
190 __sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
191 __sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
192 __sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
193 __sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
194 __sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
195 __sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
196 __sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
197 __sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
198
199 /* P1 0x90 */
200 __sbit __at (0x90) P1_0 ;
201 __sbit __at (0x91) P1_1 ;
202 __sbit __at (0x92) P1_2 ;
203 __sbit __at (0x93) P1_3 ;
204 __sbit __at (0x94) P1_4 ;
205 __sbit __at (0x95) P1_5 ;
206 __sbit __at (0x96) P1_6 ;
207 __sbit __at (0x97) P1_7 ;
208
209 /* SCON 0x98 */
210 __sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
211 __sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
212 __sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
213 __sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
214 __sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
215 __sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
216 __sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
217 __sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
218 __sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
219 __sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
220 __sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
221 __sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
222 __sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
223 __sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
224
225 /* P2 0xA0 */
226 __sbit __at (0xA0) P2_0 ;
227 __sbit __at (0xA1) P2_1 ;
228 __sbit __at (0xA2) P2_2 ;
229 __sbit __at (0xA3) P2_3 ;
230 __sbit __at (0xA4) P2_4 ;
231 __sbit __at (0xA5) P2_5 ;
232 __sbit __at (0xA6) P2_6 ;
233 __sbit __at (0xA7) P2_7 ;
234
235 /* IE 0xA8 */
236 __sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
237 __sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
238 __sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
239 __sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
240 __sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
241 __sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
242 __sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
243 __sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
244 __sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
245
246 /* IP 0xB8 */
247 __sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
248 __sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
249 __sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
250 __sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
251 __sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
252 __sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
253 __sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
254 __sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
255
256 /* SMB0CN 0xC0 */
257 __sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
258 __sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
259 __sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
260 __sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
261 __sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
262 __sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
263 __sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
264 __sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
265
266 /* TMR2CN 0xC8 */
267 __sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
268 __sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
269 __sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
270 __sbit __at (0xCC) TF2CEN ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
271 __sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
272 __sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
273 __sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
274 __sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
275
276 /* PSW 0xD0 */
277 __sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
278 __sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
279 __sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
280 __sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
281 __sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
282 __sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
283 __sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
284 __sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
285
286 /* PCA0CN 0xD8 */
287 __sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
288 __sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
289 __sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
290 __sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
291 __sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
292
293 /* ADC0STA 0xE8 */
294 __sbit __at (0xE8) AD0OVR ; /* ADC0CN.0 - ADC 0 OVERRUN FLAG */
295 __sbit __at (0xE9) AD0ERR ; /* ADC0CN.1 - ADC 0 ERROR FLAG */
296 __sbit __at (0xEA) AD0CALC ; /* ADC0CN.2 - ADC 0 CALIBRATION COMPLETE FLAG */
297 __sbit __at (0xEB) AD0FFC ; /* ADC0CN.3 - ADC 0 FAST FILTER CLIP FLAG */
298 __sbit __at (0xEC) AD0S3C ; /* ADC0CN.4 - ADC 0 SINC3 FILTER CLIP FLAG */
299 __sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
300 __sbit __at (0xEE) AD0CBSY ; /* ADC0CN.6 - ADC 0 CALIBRATION IN PROGRESS FLAG */
301 __sbit __at (0xEF) AD0BUSY ; /* ADC0CN.7 - ADC 0 CONVERSION IN PROGRESS FLAG */
302
303 /* SPI0CN 0xF8 */
304 __sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
305 __sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
306 __sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
307 __sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
308 __sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
309 __sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
310 __sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
311 __sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
312
313
314 /* Predefined SFR Bit Masks */
315
316 #define PCON_IDLE 0x01 /* PCON */
317 #define PCON_STOP 0x02 /* PCON */
318 #define T1M 0x08 /* CKCON */
319 #define PSWE 0x01 /* PSCTL */
320 #define PSEE 0x02 /* PSCTL */
321 #define ECP0 0x20 /* EIE1 */
322 #define PORSF 0x02 /* RSTSRC */
323 #define SWRSF 0x10 /* RSTSRC */
324 #define ECCF 0x01 /* PCA0CPMn */
325 #define PWM 0x02 /* PCA0CPMn */
326 #define TOG 0x04 /* PCA0CPMn */
327 #define MAT 0x08 /* PCA0CPMn */
328 #define CAPN 0x10 /* PCA0CPMn */
329 #define CAPP 0x20 /* PCA0CPMn */
330 #define ECOM 0x40 /* PCA0CPMn */
331 #define PWM16 0x80 /* PCA0CPMn */
332 #define CP0E 0x10 /* XBR0 */
333 #define CP0OEN 0x10 /* XBR0 */
334 #define CP0AE 0x20 /* XBR0 */
335 #define CP0AOEN 0x20 /* XBR0 */
336
337 #endif
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