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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / C8051F410.h
blob44e9d4727636d7912e7573d77cc5241d8acf0a20
1 /*-------------------------------------------------------------------------
2 C8051F410.h - Register Declarations for the SiLabs C8051F41x
3 Processor Range
4
5 Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 #ifndef C8051F410_H
31 #define C8051F410_H
32
33
34 /* BYTE Registers */
35
36 __sfr __at (0x80) P0 ; /* PORT 0 */
37 __sfr __at (0x81) SP ; /* STACK POINTER */
38 __sfr __at (0x82) DPL ; /* DATA POINTER - LOW BYTE */
39 __sfr __at (0x83) DPH ; /* DATA POINTER - HIGH BYTE */
40 __sfr __at (0x84) CRC0CN ; /* CRC 0 CONTROL */
41 __sfr __at (0x85) CRC0IN ; /* CRC 0 DATA INPUT */
42 __sfr __at (0x86) CRC0DAT ; /* CRC 0 DATA OUTPUT */
43 __sfr __at (0x87) PCON ; /* POWER CONTROL */
44 __sfr __at (0x88) TCON ; /* TIMER CONTROL */
45 __sfr __at (0x89) TMOD ; /* TIMER MODE */
46 __sfr __at (0x8A) TL0 ; /* TIMER 0 - LOW BYTE */
47 __sfr __at (0x8B) TL1 ; /* TIMER 1 - LOW BYTE */
48 __sfr __at (0x8C) TH0 ; /* TIMER 0 - HIGH BYTE */
49 __sfr __at (0x8D) TH1 ; /* TIMER 1 - HIGH BYTE */
50 __sfr __at (0x8E) CKCON ; /* CLOCK CONTROL */
51 __sfr __at (0x8F) PSCTL ; /* PROGRAM STORE R/W CONTROL */
52 __sfr __at (0x90) P1 ; /* PORT 1 */
53 __sfr __at (0x91) TMR3CN ; /* TIMER 3 CONTROL */
54 __sfr __at (0x92) TMR3RLL ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
55 __sfr __at (0x93) TMR3RLH ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
56 __sfr __at (0x94) TMR3L ; /* TIMER 3 - LOW BYTE */
57 __sfr __at (0x95) TMR3H ; /* TIMER 3 - HIGH BYTE */
58 __sfr __at (0x96) IDA0L ; /* CURRENT MODE DAC 0 - LOW BYTE */
59 __sfr __at (0x97) IDA0H ; /* CURRENT MODE DAC 0 - HIGH BYTE */
60 __sfr __at (0x98) SCON ; /* SERIAL PORT CONTROL */
61 __sfr __at (0x98) SCON0 ; /* SERIAL PORT CONTROL */
62 __sfr __at (0x99) SBUF ; /* SERIAL PORT BUFFER */
63 __sfr __at (0x99) SBUF0 ; /* SERIAL PORT BUFFER */
64 __sfr __at (0x9A) CPT1CN ; /* COMPARATOR 1 CONTROL */
65 __sfr __at (0x9B) CPT0CN ; /* COMPARATOR 0 CONTROL */
66 __sfr __at (0x9C) CPT1MD ; /* COMPARATOR 1 MODE SELECTION */
67 __sfr __at (0x9D) CPT0MD ; /* COMPARATOR 0 MODE SELECTION */
68 __sfr __at (0x9E) CPT1MX ; /* COMPARATOR 1 MUX SELECTION */
69 __sfr __at (0x9F) CPT0MX ; /* COMPARATOR 0 MUX SELECTION */
70 __sfr __at (0xA0) P2 ; /* PORT 2 */
71 __sfr __at (0xA1) SPI0CFG ; /* SPI0 CONFIGURATION */
72 __sfr __at (0xA2) SPI0CKR ; /* SPI0 CLOCK RATE CONTROL */
73 __sfr __at (0xA3) SPI0DAT ; /* SPI0 DATA */
74 __sfr __at (0xA4) P0MDOUT ; /* PORT 0 OUTPUT MODE CONFIGURATION */
75 __sfr __at (0xA5) P1MDOUT ; /* PORT 1 OUTPUT MODE CONFIGURATION */
76 __sfr __at (0xA6) P2MDOUT ; /* PORT 2 OUTPUT MODE CONFIGURATION */
77 __sfr __at (0xA8) IE ; /* INTERRUPT ENABLE */
78 __sfr __at (0xA9) CLKSEL ; /* SYSTEM CLOCK SELECT */
79 __sfr __at (0xAA) EMI0CN ; /* EXTERNAL MEMORY INTERFACE CONTROL */
80 __sfr __at (0xAA) _XPAGE ; /* XDATA/PDATA PAGE */
81 __sfr __at (0xAB) CLKMUL ; /* CLOCK MULTIPLIER */
82 __sfr __at (0xAC) RTC0ADR ; /* SMARTCLOCK ADDRESS */
83 __sfr __at (0xAD) RTC0DAT ; /* SMARTCLOCK DATA */
84 __sfr __at (0xAE) RTC0KEY ; /* SMARTCLOCK LOCK AND KEY */
85 __sfr __at (0xAF) ONESHOT ; /* FLASH ONESHOT PERIOD */
86 __sfr __at (0xB0) P0ODEN ; /* PORT 0 OVERDRIVE */
87 __sfr __at (0xB1) OSCXCN ; /* EXTERNAL OSCILLATOR CONTROL */
88 __sfr __at (0xB2) OSCICN ; /* INTERNAL OSCILLATOR CONTROL */
89 __sfr __at (0xB3) OSCICL ; /* INTERNAL OSCILLATOR CALIBRATION */
90 __sfr __at (0xB5) IDA1CN ; /* CURRENT MODE DAC 1 - CONTROL */
91 __sfr __at (0xB6) FLSCL ; /* FLASH MEMORY TIMING PRESCALER */
92 __sfr __at (0xB7) FLKEY ; /* FLASH ACESS LIMIT */
93 __sfr __at (0xB8) IP ; /* INTERRUPT PRIORITY */
94 __sfr __at (0xB9) IDA0CN ; /* CURRENT MODE DAC 0 - CONTROL */
95 __sfr __at (0xBA) ADC0TK ; /* ADC 0 TRACKING MODE SELECT */
96 __sfr __at (0xBB) ADC0MX ; /* ADC 0 CHANNEL SELECT */
97 __sfr __at (0xBC) ADC0CF ; /* ADC 0 CONFIGURATION */
98 __sfr __at (0xBD) ADC0L ; /* ADC 0 DATA WORD LSB */
99 __sfr __at (0xBE) ADC0H ; /* ADC 0 DATA WORD MSB */
100 __sfr __at (0xBF) P1MASK ; /* PORT 1 MASK */
101 __sfr __at (0xC0) SMB0CN ; /* SMBUS CONTROL */
102 __sfr __at (0xC1) SMB0CF ; /* SMBUS CONFIGURATION */
103 __sfr __at (0xC2) SMB0DAT ; /* SMBUS DATA */
104 __sfr __at (0xC3) ADC0GTL ; /* ADC 0 GREATER-THAN LOW BYTE */
105 __sfr __at (0xC4) ADC0GTH ; /* ADC 0 GREATER-THAN HIGH BYTE */
106 __sfr __at (0xC5) ADC0LTL ; /* ADC 0 LESS-THAN LOW BYTE */
107 __sfr __at (0xC6) ADC0LTH ; /* ADC 0 LESS-THAN HIGH BYTE */
108 __sfr __at (0xC7) P0MASK ; /* PORT 0 MASK */
109 __sfr __at (0xC8) T2CON ; /* TIMER 2 CONTROL */
110 __sfr __at (0xC8) TMR2CN ; /* TIMER 2 CONTROL */
111 __sfr __at (0xC9) REG0CN ; /* VOLTAGE REGULATOR CONTROL */
112 __sfr __at (0xCA) RCAP2L ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
113 __sfr __at (0xCA) TMR2RLL ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
114 __sfr __at (0xCB) RCAP2H ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
115 __sfr __at (0xCB) TMR2RLH ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
116 __sfr __at (0xCC) TL2 ; /* TIMER 2 - LOW BYTE */
117 __sfr __at (0xCC) TMR2L ; /* TIMER 2 - LOW BYTE */
118 __sfr __at (0xCD) TH2 ; /* TIMER 2 - HIGH BYTE */
119 __sfr __at (0xCD) TMR2H ; /* TIMER 2 - HIGH BYTE */
120 __sfr __at (0xCE) PCA0CPM5 ; /* PCA MODULE 5 MODE REGISTER */
121 __sfr __at (0xCF) P1MAT ; /* PORT 1 MATCH */
122 __sfr __at (0xD0) PSW ; /* PROGRAM STATUS WORD */
123 __sfr __at (0xD1) REF0CN ; /* VOLTAGE REFERENCE 0 CONTROL */
124 __sfr __at (0xD2) PCA0CPL5 ; /* PCA CAPTURE 5 LOW */
125 __sfr __at (0xD3) PCA0CPH5 ; /* PCA CAPTURE 5 HIGH */
126 __sfr __at (0xD4) P0SKIP ; /* PORT 0 SKIP */
127 __sfr __at (0xD5) P1SKIP ; /* PORT 1 SKIP */
128 __sfr __at (0xD6) P2SKIP ; /* PORT 2 SKIP */
129 __sfr __at (0xD7) P0MAT ; /* PORT 0 MATCH */
130 __sfr __at (0xD8) PCA0CN ; /* PCA CONTROL */
131 __sfr __at (0xD9) PCA0MD ; /* PCA MODE */
132 __sfr __at (0xDA) PCA0CPM0 ; /* PCA MODULE 0 MODE REGISTER */
133 __sfr __at (0xDB) PCA0CPM1 ; /* PCA MODULE 1 MODE REGISTER */
134 __sfr __at (0xDC) PCA0CPM2 ; /* PCA MODULE 2 MODE REGISTER */
135 __sfr __at (0xDD) PCA0CPM3 ; /* PCA MODULE 3 MODE REGISTER */
136 __sfr __at (0xDE) PCA0CPM4 ; /* PCA MODULE 4 MODE REGISTER */
137 __sfr __at (0xDF) CRC0FLIP ; /* CRC 0 BIT FLIP */
138 __sfr __at (0xE0) ACC ; /* ACCUMULATOR */
139 __sfr __at (0xE1) XBR0 ; /* PORT MUX CONFIGURATION REGISTER 0 */
140 __sfr __at (0xE2) XBR1 ; /* PORT MUX CONFIGURATION REGISTER 1 */
141 __sfr __at (0xE3) PFE0CN ; /* PREFETCH ENGINE CONTROL */
142 __sfr __at (0xE4) IT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
143 __sfr __at (0xE4) INT01CF ; /* INT0/INT1 CONFIGURATION REGISTER */
144 __sfr __at (0xE6) EIE1 ; /* EXTERNAL INTERRUPT ENABLE 1 */
145 __sfr __at (0xE7) EIE2 ; /* EXTERNAL INTERRUPT ENABLE 2 */
146 __sfr __at (0xE8) ADC0CN ; /* ADC 0 CONTROL */
147 __sfr __at (0xE9) PCA0CPL1 ; /* PCA CAPTURE 1 LOW */
148 __sfr __at (0xEA) PCA0CPH1 ; /* PCA CAPTURE 1 HIGH */
149 __sfr __at (0xEB) PCA0CPL2 ; /* PCA CAPTURE 2 LOW */
150 __sfr __at (0xEC) PCA0CPH2 ; /* PCA CAPTURE 2 HIGH */
151 __sfr __at (0xED) PCA0CPL3 ; /* PCA CAPTURE 3 LOW */
152 __sfr __at (0xEE) PCA0CPH3 ; /* PCA CAPTURE 3 HIGH */
153 __sfr __at (0xEF) RSTSRC ; /* RESET SOURCE */
154 __sfr __at (0xF0) B ; /* B REGISTER */
155 __sfr __at (0xF1) P0MODE ; /* PORT 0 INPUT MODE CONFIGURATION */
156 __sfr __at (0xF1) P0MDIN ; /* PORT 0 INPUT MODE CONFIGURATION */
157 __sfr __at (0xF2) P1MODE ; /* PORT 1 INPUT MODE CONFIGURATION */
158 __sfr __at (0xF2) P1MDIN ; /* PORT 1 INPUT MODE CONFIGURATION */
159 __sfr __at (0xF3) P2MODE ; /* PORT 2 INPUT MODE CONFIGURATION */
160 __sfr __at (0xF3) P2MDIN ; /* PORT 2 INPUT MODE CONFIGURATION */
161 __sfr __at (0xF4) IDA1L ; /* CURRENT MODE DAC 1 - LOW BYTE */
162 __sfr __at (0xF5) IDA1H ; /* CURRENT MODE DAC 1 - HIGH BYTE */
163 __sfr __at (0xF6) EIP1 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
164 __sfr __at (0xF7) EIP2 ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
165 __sfr __at (0xF8) SPI0CN ; /* SPI0 CONTROL */
166 __sfr __at (0xF9) PCA0L ; /* PCA COUNTER LOW */
167 __sfr __at (0xFA) PCA0H ; /* PCA COUNTER HIGH */
168 __sfr __at (0xFB) PCA0CPL0 ; /* PCA CAPTURE 0 LOW */
169 __sfr __at (0xFC) PCA0CPH0 ; /* PCA CAPTURE 0 HIGH */
170 __sfr __at (0xFD) PCA0CPL4 ; /* PCA CAPTURE 4 LOW */
171 __sfr __at (0xFE) PCA0CPH4 ; /* PCA CAPTURE 4 HIGH */
172 __sfr __at (0xFF) VDM0CN ; /* VDD MONITOR CONTROL */
173
174
175 /* WORD/DWORD Registers */
176
177 __sfr16 __at (0x8C8A) TMR0 ; /* TIMER 0 COUNTER */
178 __sfr16 __at (0x8D8B) TMR1 ; /* TIMER 1 COUNTER */
179 __sfr16 __at (0xCDCC) TMR2 ; /* TIMER 2 COUNTER */
180 __sfr16 __at (0xCBCA) RCAP2 ; /* TIMER 2 CAPTURE REGISTER WORD */
181 __sfr16 __at (0xCBCA) TMR2RL ; /* TIMER 2 CAPTURE REGISTER WORD */
182 __sfr16 __at (0x9594) TMR3 ; /* TIMER 3 COUNTER */
183 __sfr16 __at (0x9392) TMR3RL ; /* TIMER 3 CAPTURE REGISTER WORD */
184 __sfr16 __at (0x9796) IDA0 ; /* CURRENT MODE DAC 0 DATA WORD */
185 __sfr16 __at (0xF5F4) IDA1 ; /* CURRENT MODE DAC 1 DATA WORD */
186 __sfr16 __at (0xBEBD) ADC0 ; /* ADC 0 DATA WORD */
187 __sfr16 __at (0xC4C3) ADC0GT ; /* ADC 0 GREATER-THAN REGISTER WORD */
188 __sfr16 __at (0xC6C5) ADC0LT ; /* ADC 0 LESS-THAN REGISTER WORD */
189 __sfr16 __at (0xFAF9) PCA0 ; /* PCA COUNTER */
190 __sfr16 __at (0xFCFB) PCA0CP0 ; /* PCA CAPTURE 0 WORD */
191 __sfr16 __at (0xEAE9) PCA0CP1 ; /* PCA CAPTURE 1 WORD */
192 __sfr16 __at (0xECEB) PCA0CP2 ; /* PCA CAPTURE 2 WORD */
193 __sfr16 __at (0xEEED) PCA0CP3 ; /* PCA CAPTURE 3 WORD */
194 __sfr16 __at (0xFEFD) PCA0CP4 ; /* PCA CAPTURE 4 WORD */
195 __sfr16 __at (0xD3D2) PCA0CP5 ; /* PCA CAPTURE 5 WORD */
196
197
198 /* BIT Registers */
199
200 /* P0 0x80 */
201 __sbit __at (0x80) P0_0 ;
202 __sbit __at (0x81) P0_1 ;
203 __sbit __at (0x82) P0_2 ;
204 __sbit __at (0x83) P0_3 ;
205 __sbit __at (0x84) P0_4 ;
206 __sbit __at (0x85) P0_5 ;
207 __sbit __at (0x86) P0_6 ;
208 __sbit __at (0x87) P0_7 ;
209
210 /* TCON 0x88 */
211 __sbit __at (0x88) IT0 ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
212 __sbit __at (0x89) IE0 ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
213 __sbit __at (0x8A) IT1 ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
214 __sbit __at (0x8B) IE1 ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
215 __sbit __at (0x8C) TR0 ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
216 __sbit __at (0x8D) TF0 ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
217 __sbit __at (0x8E) TR1 ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
218 __sbit __at (0x8F) TF1 ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
219
220 /* P1 0x90 */
221 __sbit __at (0x90) P1_0 ;
222 __sbit __at (0x91) P1_1 ;
223 __sbit __at (0x92) P1_2 ;
224 __sbit __at (0x93) P1_3 ;
225 __sbit __at (0x94) P1_4 ;
226 __sbit __at (0x95) P1_5 ;
227 __sbit __at (0x96) P1_6 ;
228 __sbit __at (0x97) P1_7 ;
229
230 /* SCON 0x98 */
231 __sbit __at (0x98) RI ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
232 __sbit __at (0x98) RI0 ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
233 __sbit __at (0x99) TI ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
234 __sbit __at (0x99) TI0 ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
235 __sbit __at (0x9A) RB8 ; /* SCON.2 - RECEIVE BIT 8 */
236 __sbit __at (0x9A) RB80 ; /* SCON.2 - RECEIVE BIT 8 */
237 __sbit __at (0x9B) TB8 ; /* SCON.3 - TRANSMIT BIT 8 */
238 __sbit __at (0x9B) TB80 ; /* SCON.3 - TRANSMIT BIT 8 */
239 __sbit __at (0x9C) REN ; /* SCON.4 - RECEIVE ENABLE */
240 __sbit __at (0x9C) REN0 ; /* SCON.4 - RECEIVE ENABLE */
241 __sbit __at (0x9D) SM2 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
242 __sbit __at (0x9D) MCE0 ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
243 __sbit __at (0x9F) SM0 ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
244 __sbit __at (0x9F) S0MODE ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
245
246 /* P2 0xA0 */
247 __sbit __at (0xA0) P2_0 ;
248 __sbit __at (0xA1) P2_1 ;
249 __sbit __at (0xA2) P2_2 ;
250 __sbit __at (0xA3) P2_3 ;
251 __sbit __at (0xA4) P2_4 ;
252 __sbit __at (0xA5) P2_5 ;
253 __sbit __at (0xA6) P2_6 ;
254 __sbit __at (0xA7) P2_7 ;
255
256 /* IE 0xA8 */
257 __sbit __at (0xA8) EX0 ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
258 __sbit __at (0xA9) ET0 ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
259 __sbit __at (0xAA) EX1 ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
260 __sbit __at (0xAB) ET1 ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
261 __sbit __at (0xAC) ES ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
262 __sbit __at (0xAC) ES0 ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
263 __sbit __at (0xAD) ET2 ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
264 __sbit __at (0xAE) ESPI0 ; /* IE.6 - SPI0 INTERRUPT ENABLE */
265 __sbit __at (0xAF) EA ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
266
267 /* P0ODEN 0xB0 */
268 __sbit __at (0xB0) P0OD_0 ; /* P0ODEN.0 - PORT0.0 OVERDRIVE ENABLE */
269 __sbit __at (0xB1) P0OD_1 ; /* P0ODEN.1 - PORT0.1 OVERDRIVE ENABLE */
270 __sbit __at (0xB2) P0OD_2 ; /* P0ODEN.2 - PORT0.2 OVERDRIVE ENABLE */
271 __sbit __at (0xB3) P0OD_3 ; /* P0ODEN.3 - PORT0.3 OVERDRIVE ENABLE */
272 __sbit __at (0xB4) P0OD_4 ; /* P0ODEN.4 - PORT0.4 OVERDRIVE ENABLE */
273 __sbit __at (0xB5) P0OD_5 ; /* P0ODEN.5 - PORT0.5 OVERDRIVE ENABLE */
274 __sbit __at (0xB6) P0OD_6 ; /* P0ODEN.6 - PORT0.6 OVERDRIVE ENABLE */
275 __sbit __at (0xB7) P0OD_7 ; /* P0ODEN.7 - PORT0.7 OVERDRIVE ENABLE */
276
277 /* IP 0xB8 */
278 __sbit __at (0xB8) PX0 ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
279 __sbit __at (0xB9) PT0 ; /* IP.1 - TIMER 0 PRIORITY */
280 __sbit __at (0xBA) PX1 ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
281 __sbit __at (0xBB) PT1 ; /* IP.3 - TIMER 1 PRIORITY */
282 __sbit __at (0xBC) PS ; /* IP.4 - SERIAL PORT PRIORITY */
283 __sbit __at (0xBC) PS0 ; /* IP.4 - SERIAL PORT PRIORITY */
284 __sbit __at (0xBD) PT2 ; /* IP.5 - TIMER 2 PRIORITY */
285 __sbit __at (0xBE) PSPI0 ; /* IP.6 - SPI0 PRIORITY */
286
287 /* SMB0CN 0xC0 */
288 __sbit __at (0xC0) SI ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
289 __sbit __at (0xC1) ACK ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
290 __sbit __at (0xC2) ARBLOST ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
291 __sbit __at (0xC3) ACKRQ ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
292 __sbit __at (0xC4) STO ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
293 __sbit __at (0xC5) STA ; /* SMB0CN.5 - SMBUS 0 START FLAG */
294 __sbit __at (0xC6) TXMODE ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
295 __sbit __at (0xC7) MASTER ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
296
297 /* TMR2CN 0xC8 */
298 __sbit __at (0xC8) T2XCLK ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
299 __sbit __at (0xC9) T2RCLK ; /* TMR2CN.1 - TIMER 2 CAPTURE MODE */
300 __sbit __at (0xCA) TR2 ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
301 __sbit __at (0xCB) T2SPLIT ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
302 __sbit __at (0xCC) TF2CEN ; /* TMR2CN.4 - TIMER 2 LOW-FREQ OSC CAPTURE ENABLE*/
303 __sbit __at (0xCD) TF2LEN ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
304 __sbit __at (0xCE) TF2L ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
305 __sbit __at (0xCF) TF2 ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
306 __sbit __at (0xCF) TF2H ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
307
308 /* PSW 0xD0 */
309 __sbit __at (0xD0) PARITY ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
310 __sbit __at (0xD1) F1 ; /* PSW.1 - FLAG 1 */
311 __sbit __at (0xD2) OV ; /* PSW.2 - OVERFLOW FLAG */
312 __sbit __at (0xD3) RS0 ; /* PSW.3 - REGISTER BANK SELECT 0 */
313 __sbit __at (0xD4) RS1 ; /* PSW.4 - REGISTER BANK SELECT 1 */
314 __sbit __at (0xD5) F0 ; /* PSW.5 - FLAG 0 */
315 __sbit __at (0xD6) AC ; /* PSW.6 - AUXILIARY CARRY FLAG */
316 __sbit __at (0xD7) CY ; /* PSW.7 - CARRY FLAG */
317
318 /* PCA0CN 0xD8 */
319 __sbit __at (0xD8) CCF0 ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
320 __sbit __at (0xD9) CCF1 ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
321 __sbit __at (0xDA) CCF2 ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
322 __sbit __at (0xDB) CCF3 ; /* PCA0CN.3 - PCA MODULE 3 CAPTURE/COMPARE FLAG */
323 __sbit __at (0xDC) CCF4 ; /* PCA0CN.4 - PCA MODULE 4 CAPTURE/COMPARE FLAG */
324 __sbit __at (0xDD) CCF5 ; /* PCA0CN.5 - PCA MODULE 5 CAPTURE/COMPARE FLAG */
325 __sbit __at (0xDE) CR ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
326 __sbit __at (0xDF) CF ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
327
328 /* ADC0CN 0xE8 */
329 __sbit __at (0xE8) AD0CM0 ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
330 __sbit __at (0xE9) AD0CM1 ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
331 __sbit __at (0xEA) AD0LJST ; /* ADC0CN.2 - ADC 0 LEFT JUSTIFY SELECT */
332 __sbit __at (0xEB) AD0WINT ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
333 __sbit __at (0xEC) AD0BUSY ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
334 __sbit __at (0xED) AD0INT ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
335 __sbit __at (0xEE) BURSTEN ; /* ADC0CN.6 - ADC 0 BURST MODE ENABLE */
336 __sbit __at (0xEF) AD0EN ; /* ADC0CN.7 - ADC 0 ENABLE */
337
338 /* SPI0CN 0xF8 */
339 __sbit __at (0xF8) SPIEN ; /* SPI0CN.0 - SPI0 ENABLE */
340 __sbit __at (0xF9) TXBMT ; /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
341 __sbit __at (0xFA) NSSMD0 ; /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
342 __sbit __at (0xFB) NSSMD1 ; /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
343 __sbit __at (0xFC) RXOVRN ; /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
344 __sbit __at (0xFD) MODF ; /* SPI0CN.5 - MODE FAULT FLAG */
345 __sbit __at (0xFE) WCOL ; /* SPI0CN.6 - WRITE COLLISION FLAG */
346 __sbit __at (0xFF) SPIF ; /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
347
348
349 /* Predefined SFR Bit Masks */
350
351 #define PCON_IDLE 0x01 /* PCON */
352 #define PCON_STOP 0x02 /* PCON */
353 #define T1M 0x08 /* CKCON */
354 #define PSWE 0x01 /* PSCTL */
355 #define PSEE 0x02 /* PSCTL */
356 #define ECP0 0x20 /* EIE1 */
357 #define PORSF 0x02 /* RSTSRC */
358 #define SWRSF 0x10 /* RSTSRC */
359 #define ECCF 0x01 /* PCA0CPMn */
360 #define PWM 0x02 /* PCA0CPMn */
361 #define TOG 0x04 /* PCA0CPMn */
362 #define MAT 0x08 /* PCA0CPMn */
363 #define CAPN 0x10 /* PCA0CPMn */
364 #define CAPP 0x20 /* PCA0CPMn */
365 #define ECOM 0x40 /* PCA0CPMn */
366 #define PWM16 0x80 /* PCA0CPMn */
367 #define CP0E 0x10 /* XBR0 */
368 #define CP0OEN 0x10 /* XBR0 */
369 #define CP0AE 0x20 /* XBR0 */
370 #define CP0AOEN 0x20 /* XBR0 */
371
372 /* Interrupts */
373
374 #define INT_EXT0 0 // External Interrupt 0
375 #define INT_TIMER0 1 // Timer0 Overflow
376 #define INT_EXT1 2 // External Interrupt 1
377 #define INT_TIMER1 3 // Timer1 Overflow
378 #define INT_UART0 4 // Serial Port 0
379 #define INT_TIMER2 5 // Timer2 Overflow
380 #define INT_SPI0 6 // Serial Peripheral Interface 0
381 #define INT_SMBUS0 7 // SMBus0 Interface
382 #define INT_RTC0 8 // RTC0 Interface
383 #define INT_ADC0_WINDOW 9 // ADC0 Window Comparison
384 #define INT_ADC0_EOC 10 // ADC0 End Of Conversion
385 #define INT_PCA0 11 // PCA0 Peripheral
386 #define INT_COMPARATOR0 12 // Comparator0
387 #define INT_COMPARATOR1 13 // Comparator1
388 #define INT_TIMER3 14 // Timer3 Overflow
389 #define INT_VREG_DROPOUT 15 // VREG dropout
390 #define INT_PORT_MATCH 16 // Port Match
391
392 #endif
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