sdcc/device/include/mcs51/C8051F520.h

   1 /*-------------------------------------------------------------------------
   2    C8051F520.h - Register Declarations for the SiLabs C8051F52x-F53x
   3    Processor Range
   4
   5    Copyright (C) 2006, Maarten Brock, sourceforge.brock@dse.nl
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef C8051F520_H
  31 #define C8051F520_H
  32
  33 #include <compiler.h>
  34
  35 SFR(P0,         0x80);      // Port 0
  36    SBIT(P0_0,     0x80, 0); // Port 0 bit 0
  37    SBIT(P0_1,     0x80, 1); // Port 0 bit 1
  38    SBIT(P0_2,     0x80, 2); // Port 0 bit 2
  39    SBIT(P0_3,     0x80, 3); // Port 0 bit 3
  40    SBIT(P0_4,     0x80, 4); // Port 0 bit 4
  41    SBIT(P0_5,     0x80, 5); // Port 0 bit 5
  42    SBIT(P0_6,     0x80, 6); // Port 0 bit 6
  43    SBIT(P0_7,     0x80, 7); // Port 0 bit 7
  44 SFR(SP,         0x81);      // Stack Pointer
  45 SFR(DPL,        0x82);      // Data Pointer Low Byte
  46 SFR(DPH,        0x83);      // Data Pointer High Byte
  47 SFR(PCON,       0x87);      // Power Mode Control
  48 SFR(TCON,       0x88);      // Timer Control
  49    SBIT(IT0,      0x88, 0); // Ext. Interrupt 0 Type Select
  50    SBIT(IE0,      0x88, 1); // Ext. Interrupt 0 Flag
  51    SBIT(IT1,      0x88, 2); // Ext. Interrupt 1 Type Select
  52    SBIT(IE1,      0x88, 3); // Ext. Interrupt 1 Flag
  53    SBIT(TR0,      0x88, 4); // Timer 0 Run Control
  54    SBIT(TF0,      0x88, 5); // Timer 0 Overflow Flag
  55    SBIT(TR1,      0x88, 6); // Timer 1 Run Control
  56    SBIT(TF1,      0x88, 7); // Timer 1 Overflow Flag
  57 SFR(TMOD,       0x89);      // Timer Mode
  58 SFR16E(TMR0,    0x8C8A);    // Timer/Counter 0 Word
  59    SFR(TL0,       0x8A);    // Timer/Counter 0 Low Byte
  60    SFR(TH0,       0x8C);    // Timer/Counter 0 High Byte
  61 SFR16E(TMR1,    0x8D8B);    // Timer/Counter 1 Word
  62    SFR(TL1,       0x8B);    // Timer/Counter 1 Low Byte
  63    SFR(TH1,       0x8D);    // Timer/Counter 1 High Byte
  64 SFR(CKCON,      0x8E);      // Clock Control
  65 SFR(PSCTL,      0x8F);      // Program Store R/W Control
  66 SFR(P1,         0x90);      // Port 1
  67    SBIT(P1_0,     0x90, 0); // Port 1 bit 0
  68    SBIT(P1_1,     0x90, 1); // Port 1 bit 1
  69    SBIT(P1_2,     0x90, 2); // Port 1 bit 2
  70    SBIT(P1_3,     0x90, 3); // Port 1 bit 3
  71    SBIT(P1_4,     0x90, 4); // Port 1 bit 4
  72    SBIT(P1_5,     0x90, 5); // Port 1 bit 5
  73    SBIT(P1_6,     0x90, 6); // Port 1 bit 6
  74    SBIT(P1_7,     0x90, 7); // Port 1 bit 7
  75 SFR(LINADDR,    0x92);      // LIN Indirect Address Pointer
  76 SFR(LINDATA,    0x93);      // LIN Indirect Data Buffer
  77 SFR(LINCF,      0x95);      // LIN Control Mode
  78 SFR(SCON0,      0x98);      // Serial Port 0 Control
  79    SBIT(RI0,      0x98, 0); // Receive Interrupt Flag
  80    SBIT(TI0,      0x98, 1); // Transmit Interrupt Flag
  81    SBIT(RB80,     0x98, 2); // Ninth Receive Bit
  82    SBIT(TB80,     0x98, 3); // Ninth Transmission Bit
  83    SBIT(REN0,     0x98, 4); // Receive Enable
  84    SBIT(MCE0,     0x98, 5); // Multiprocessor Communication Enable
  85    SBIT(S0MODE,   0x98, 7); // Serial Port 0 Operation Mode
  86 SFR(SBUF0,      0x99);      // Serial Port 0 Data Buffer
  87 SFR(CPT0CN,     0x9B);      // Comparator 0 Control
  88 SFR(CPT0MD,     0x9D);      // Comparator 0 Mode Selection
  89 SFR(CPT0MX,     0x9F);      // Comparator 0 MUX Selection
  90 SFR(SPI0CFG,    0xA1);      // SPI Configuration
  91 SFR(SPI0CKR,    0xA2);      // SPI Clock Rate Control
  92 SFR(SPI0DAT,    0xA3);      // SPI Data
  93 SFR(P0MDOUT,    0xA4);      // Port 0 Output Mode Configuration
  94 SFR(P1MDOUT,    0xA5);      // Port 1 Output Mode Configuration
  95 SFR(IE,         0xA8);      // Interrupt Enable
  96    SBIT(EX0,      0xA8, 0); // Enable External Interrupt 0
  97    SBIT(ET0,      0xA8, 1); // Enable Timer 0 Interrupt
  98    SBIT(EX1,      0xA8, 2); // Enable External Interrupt 1
  99    SBIT(ET1,      0xA8, 3); // Enable Timer 1 Interrupt
 100    SBIT(ES0,      0xA8, 4); // Enable Serial Port Interrupt
 101    SBIT(ET2,      0xA8, 5); // Enable Timer 2 Interrupt
 102    SBIT(ESPI0,    0xA8, 6); // Enable SPI0 Interrupt
 103    SBIT(EA,       0xA8, 7); // Global Interrupt Enable
 104 SFR(CLKSEL,     0xA9);      // Clock Select
 105 SFR(OSCIFIN,    0xB0);      // Internal Oscillator Fine Calibration
 106 SFR(OSCXCN,     0xB1);      // External Oscillator Control
 107 SFR(OSCICN,     0xB2);      // Internal Oscillator Control
 108 SFR(OSCICL,     0xB3);      // Internal Oscillator Calibration
 109 SFR(FLKEY,      0xB7);      // Flash Lock and Key
 110 SFR(IP,         0xB8);      // Interrupt Priority
 111    SBIT(PX0,      0xB8, 0); // External Interrupt 0 Priority
 112    SBIT(PT0,      0xB8, 1); // Timer 0 Interrupt Priority
 113    SBIT(PX1,      0xB8, 2); // External Interrupt 1 Priority
 114    SBIT(PT1,      0xB8, 3); // Timer 1 Interrupt Priority
 115    SBIT(PS0,      0xB8, 4); // Serial Port Interrupt Priority
 116    SBIT(PT2,      0xB8, 5); // Timer 2 Interrupt Priority
 117    SBIT(PSPI0,    0xB8, 6); // SPI0 Interrupt Priority
 118 SFR(ADC0TK,     0xBA);      // ADC0 Tracking Mode Select
 119 SFR(ADC0MX,     0xBB);      // ADC0 Channel Select
 120 SFR(ADC0CF,     0xBC);      // ADC0 Configuration
 121 SFR16(ADC0,     0xBD);      // ADC0 Word
 122    SFR(ADC0L,     0xBD);    // ADC0 Low Byte
 123    SFR(ADC0H,     0xBE);    // ADC0 High Byte
 124 SFR(P1MASK,     0xBF);      // Port 1 Mask
 125 SFR16(ADC0GT,   0xC3);      // ADC0 Greater-Than Data Word
 126    SFR(ADC0GTL,   0xC3);    // ADC0 Greater-Than Data Low Byte
 127    SFR(ADC0GTH,   0xC4);    // ADC0 Greater-Than Data High Byte
 128 SFR16(ADC0LT,   0xC5);      // ADC0 Less-Than Data Word
 129    SFR(ADC0LTL,   0xC5);    // ADC0 Less-Than Data Low Byte
 130    SFR(ADC0LTH,   0xC6);    // ADC0 Less-Than Data High Byte
 131 SFR(P0MASK,     0xC7);      // Port 0 Mask
 132 SFR(TMR2CN,     0xC8);      // Timer/Counter 2 Control
 133 SFR(REG0CN,     0xC9);      // Voltage Regulator Control
 134 SFR16(TMR2RL,   0xCA);      // Timer/Counter 2 Reload Word
 135    SFR(TMR2RLL,   0xCA);    // Timer/Counter 2 Reload Low Byte
 136    SFR(TMR2RLH,   0xCB);    // Timer/Counter 2 Reload High Byte
 137 SFR16(TMR2,     0xCC);      // Timer/Counter 2 Word
 138    SFR(TMR2L,     0xCC);    // Timer/Counter 2 Low Byte
 139    SFR(TMR2H,     0xCD);    // Timer/Counter 2 High Byte
 140 SFR(P1MAT,      0xCF);      // Port 1 Match
 141 SFR(PSW,        0xD0);      // Program Status Word
 142    SBIT(P,        0xD0, 0); // Parity Flag
 143    SBIT(F1,       0xD0, 1); // User-Defined Flag
 144    SBIT(OV,       0xD0, 2); // Overflow Flag
 145    SBIT(RS0,      0xD0, 3); // Register Bank Select 0
 146    SBIT(RS1,      0xD0, 4); // Register Bank Select 1
 147    SBIT(F0,       0xD0, 5); // User-Defined Flag
 148    SBIT(AC,       0xD0, 6); // Auxiliary Carry Flag
 149    SBIT(CY,       0xD0, 7); // Carry Flag
 150 SFR(REF0CN,     0xD1);      // Voltage Reference Control
 151 SFR(P0SKIP,     0xD4);      // Port 0 Skip
 152 SFR(P1SKIP,     0xD5);      // Port 1 Skip
 153 SFR(P0MAT,      0xD7);      // Port 0 Match
 154 SFR(PCA0CN,     0xD8);      // PCA Control
 155    SBIT(CCF0,     0xD8, 0); // PCA Module 0 Capture/Compare Flag
 156    SBIT(CCF1,     0xD8, 1); // PCA Module 1 Capture/Compare Flag
 157    SBIT(CCF2,     0xD8, 2); // PCA Module 2 Capture/Compare Flag
 158    SBIT(CR,       0xD8, 6); // PCA Counter/Timer Run Control
 159    SBIT(CF,       0xD8, 7); // PCA Counter/Timer Overflow Flag
 160 SFR(PCA0MD,     0xD9);      // PCA Mode
 161 SFR(PCA0CPM0,   0xDA);      // PCA Module 0 Mode
 162 SFR(PCA0CPM1,   0xDB);      // PCA Module 1 Mode
 163 SFR(PCA0CPM2,   0xDC);      // PCA Module 2 Mode
 164 SFR(ACC,        0xE0);      // Accumulator
 165 SFR(XBR0,       0xE1);      // Port I/O Crossbar Control 0
 166 SFR(XBR1,       0xE2);      // Port I/O Crossbar Control 1
 167 SFR(IT01CF,     0xE4);      // INT0/INT1 Configuration
 168 SFR(EIE1,       0xE6);      // Extended Interrupt Enable 1
 169 SFR(ADC0CN,     0xE8);      // ADC0 Control
 170    SBIT(AD0CM0,   0xE8, 0); // ADC0 Conversion Start Mode Select Bit 0
 171    SBIT(AD0CM1,   0xE8, 1); // ADC0 Conversion Start Mode Select Bit 1
 172    SBIT(AD0LJST,  0xE8, 2); // ADC0 Left Justify Select
 173    SBIT(AD0WINT,  0xE8, 3); // ADC0 Window Compare Interrupt Flag
 174    SBIT(AD0BUSY,  0xE8, 4); // ADC0 Busy Bit
 175    SBIT(AD0INT,   0xE8, 5); // ADC0 Conversion Complete Interrupt Flag
 176    SBIT(BURSTEN,  0xE8, 6); // ADC0 Burst Mode Enable Bit
 177    SBIT(AD0EN,    0xE8, 7); // ADC0 Enable Bit
 178 SFR16(PCA0CP1,  0xE9);      // PCA Capture 1 Word
 179    SFR(PCA0CPL1,  0xE9);    // PCA Capture 1 Low Byte
 180    SFR(PCA0CPH1,  0xEA);    // PCA Capture 1 High Byte
 181 SFR16(PCA0CP2,  0xEB);      // PCA Capture 2 Word
 182    SFR(PCA0CPL2,  0xEB);    // PCA Capture 2 Low Byte
 183    SFR(PCA0CPH2,  0xEC);    // PCA Capture 2 High Byte
 184 SFR(RSTSRC,     0xEF);      // Reset Source Configuration/Status
 185 SFR(B,          0xF0);      // B Register
 186 SFR(P0MDIN,     0xF1);      // Port 0 Input Mode Configuration
 187 SFR(P1MDIN,     0xF2);      // Port 1 Input Mode Configuration
 188 SFR(EIP1,       0xF6);      // Extended Interrupt Priority 1
 189 SFR(SPI0CN,     0xF8);      // SPI0 Control
 190    SBIT(SPIEN,    0xF8, 0); // SPI0 Enable
 191    SBIT(TXBMT,    0xF8, 1); // SPI0 Transmit Buffer Empty
 192    SBIT(NSSMD0,   0xF8, 2); // SPI0 Slave Select Mode Bit 0
 193    SBIT(NSSMD1,   0xF8, 3); // SPI0 Slave Select Mode Bit 1
 194    SBIT(RXOVRN,   0xF8, 4); // SPI0 Receive Overrun Flag
 195    SBIT(MODF,     0xF8, 5); // SPI0 Mode Fault Flag
 196    SBIT(WCOL,     0xF8, 6); // SPI0 Write Collision Flag
 197    SBIT(SPIF,     0xF8, 7); // SPI0 Interrupt Flag
 198 SFR16(PCA0,     0xF9);      // PCA Counter Word
 199    SFR(PCA0L,    0xF9);    // PCA Counter Low Byte
 200    SFR(PCA0H,     0xFA);    // PCA Counter High Byte
 201 SFR16(PCA0CP0,  0xFB);      // PCA Capture 0 Word
 202    SFR(PCA0CPL0,  0xFB);    // PCA Capture 0 Low Byte
 203    SFR(PCA0CPH0,  0xFC);    // PCA Capture 0 High Byte
 204 SFR(VDDMON,     0xFF);      // VDD Control
 205
 206 /* Predefined SFR Bit Masks */
 207
 208 #define PCON_IDLE         0x01    /* PCON                                */
 209 #define PCON_STOP         0x02    /* PCON                                */
 210 #define T1M               0x08    /* CKCON                               */
 211 #define PSWE              0x01    /* PSCTL                               */
 212 #define PSEE              0x02    /* PSCTL                               */
 213 #define PORSF             0x02    /* RSTSRC                              */
 214 #define SWRSF             0x10    /* RSTSRC                              */
 215 #define ECCF              0x01    /* PCA0CPMn                            */
 216 #define PWM               0x02    /* PCA0CPMn                            */
 217 #define TOG               0x04    /* PCA0CPMn                            */
 218 #define MAT               0x08    /* PCA0CPMn                            */
 219 #define CAPN              0x10    /* PCA0CPMn                            */
 220 #define CAPP              0x20    /* PCA0CPMn                            */
 221 #define ECOM              0x40    /* PCA0CPMn                            */
 222 #define PWM16             0x80    /* PCA0CPMn                            */
 223 #define CP0E              0x10    /* XBR0                                */
 224 #define CP0AE             0x20    /* XBR0                                */
 225
 226 /* Interrupts */
 227
 228 #define INT_EXT0          0       // External Interrupt 0
 229 #define INT_TIMER0        1       // Timer0 Overflow
 230 #define INT_EXT1          2       // External Interrupt 1
 231 #define INT_TIMER1        3       // Timer1 Overflow
 232 #define INT_UART0         4       // Serial Port 0
 233 #define INT_TIMER2        5       // Timer2 Overflow
 234 #define INT_SPI0          6       // Serial Peripheral Interface 0
 235 #define INT_ADC0_WINDOW   7       // ADC0 Window Comparison
 236 #define INT_ADC0_EOC      8       // ADC0 End Of Conversion
 237 #define INT_PCA0          9       // PCA0 Peripheral
 238 #define INT_COMP_FALLING  10      // Comparator0 Falling
 239 #define INT_COMP_RISING   11      // Comparator0 Rising
 240 #define INT_LIN           12      // LIN
 241 #define INT_VREG_DROPOUT  13      // VREG dropout
 242 #define INT_PORT_MATCH    14      // Port Match
 243
 244 #endif