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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / C8051F920.h
blob243d4c1dffa248decc927ed5135452e83feb0951
1 /*-------------------------------------------------------------------------
2 C8051F920.h -Register Declarations for the SiLabs C8051F92x-93x
3 Processor Range
4
5 Copyright (C) 2009, Steven Borley, steven.borley@partnerelectronics.com
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 #ifndef C8051F920_H
31 #define C8051F920_H
32
33 #include <compiler.h>
34
35
36 /* BYTE Registers */
37
38 /* Page 0x00 (and all pages) */
39 SFR( P0, 0x80 ) ; /* PORT 0 */
40 SFR( SP, 0x81 ) ; /* STACK POINTER */
41 SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
42 SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
43 SFR( SPI1CFG, 0x84 ) ; /* SPI1 Configuration */
44 SFR( SPI1CKR, 0x85 ) ; /* SPI1 Clock Rate Control */
45 SFR( SPI1DAT, 0x86 ) ; /* SPI1 Data */
46 SFR( PCON, 0x87 ) ; /* POWER CONTROL */
47 SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
48 SFR( TMOD, 0x89 ) ; /* TIMER MODE */
49 SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
50 SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
51 SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
52 SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
53 SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
54 SFR( PSCTL, 0x8F ) ; /* Program Store R/W Control */
55 SFR( P1, 0x90 ) ; /* PORT 1 */
56 SFR( TMR3CN, 0x91 ) ; /* TIMER 3 CONTROL */
57 SFR( TMR3RLL, 0x92 ) ; /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
58 SFR( TMR3RLH, 0x93 ) ; /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
59 SFR( TMR3L, 0x94 ) ; /* TIMER 3 - LOW BYTE */
60 SFR( TMR3H, 0x95 ) ; /* TIMER 3 - HIGH BYTE */
61 SFR( DC0CF, 0x96 ) ; /* DC0 (DC-DC Converter) Configuration */
62 SFR( DC0CN, 0x97 ) ; /* DC0 (DC-DC Converter) Control */
63 SFR( SCON0, 0x98 ) ; /* Serial Port Control */
64 SFR( SBUF0, 0x99 ) ; /* Serial Port Buffer */
65 SFR( CPT1CN, 0x9A ) ; /* Comparator 1 Control */
66 SFR( CPT0CN, 0x9B ) ; /* Comparator 0 Control */
67 SFR( CPT1MD, 0x9C ) ; /* Comparator 1 Mode Selection */
68 SFR( CPT0MD, 0x9D ) ; /* Comparator 0 Mode Selection */
69 SFR( CPT1MX, 0x9E ) ; /* Comparator 1 mux selection */
70 SFR( CPT0MX, 0x9F ) ; /* Comparator 0 mux selection */
71 SFR( P2, 0xA0 ) ; /* PORT 2 */
72 SFR( SPI0CFG, 0xA1 ) ; /* SPI0 CONFIGURATION */
73 SFR( SPI0CKR, 0xA2 ) ; /* SPI0 Clock Rate Control */
74 SFR( SPI0DAT, 0xA3 ) ; /* SPI0 Data */
75 SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
76 SFR( P1MDOUT, 0xA5 ) ; /* PORT 1 OUTPUT MODE CONFIGURATION */
77 SFR( P2MDOUT, 0xA6 ) ; /* PORT 2 OUTPUT MODE CONFIGURATION */
78 SFR( SFRPAGE, 0xA7 ) ; /* SFR Page */
79 SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
80 SFR( CLKSEL, 0xA9 ) ; /* SYSTEM CLOCK SELECT */
81 SFR( EMI0CN, 0xAA ) ; /* EMIF Control */
82 SFR( _XPAGE, 0xAA ) ; /* XDATA/PDATA page alias for SDCC */
83 SFR( EMI0CF, 0xAB ) ; /* EMIF Configuration */
84 SFR( RTC0ADR, 0xAC ) ; /* RTC0 Address */
85 SFR( RTC0DAT, 0xAD ) ; /* RTC0 Data */
86 SFR( RTC0KEY, 0xAE ) ; /* RTC0 Key */
87 SFR( EMI0TC, 0xAF ) ; /* EMIF Timing Control */
88 SFR( SPI1CN, 0xB0 ) ; /* SPI1 Control */
89 SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
90 SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
91 SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
92 SFR( PMU0CF, 0xB5 ) ; /* PMU0 Configuration */
93 SFR( FLSCL, 0xB6 ) ; /* IFlash Scale */
94 SFR( FLKEY, 0xB7 ) ; /* Flash Lock And Key */
95 SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
96 SFR( IREF0CN, 0xB9 ) ; /* Current Reference IREF Control */
97 SFR( ADC0AC, 0xBA ) ; /* ADC0 Accumulator Configuration */
98 SFR( ADC0MX, 0xBB ) ; /* AMUX0 Channel Select */
99 SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
100 SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA - LOW BYTE */
101 SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA - HIGH BYTE */
102 SFR( P1MASK, 0xBF ) ; /* Port 1 Mask */
103 SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
104 SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
105 SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
106 SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
107 SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
108 SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
109 SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
110 SFR( P0MASK, 0xC7 ) ; /* Port 0 Mask */
111 SFR( TMR2CN, 0xC8 ) ; /* Timer 2 control */
112 SFR( REG0CN, 0xC9 ) ; /* Voltage Regulator (VREG0) Control */
113 SFR( TMR2RLL, 0xCA ) ; /* Timer 2 capture register - low byte */
114 SFR( TMR2RLH, 0xCB ) ; /* Timer 2 capture register - high byte */
115 SFR( TMR2L, 0xCC ) ; /* Timer 2 - low byte*/
116 SFR( TMR2H, 0xCD ) ; /* Timer 2 - high byte */
117 SFR( PCA0CPM5, 0xCE ) ; /* PCA0 Module 5 Mode Register */
118 SFR( P1MAT, 0xCF ) ; /* Port 1 Match */
119 SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
120 SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
121 SFR( PCA0CPL5, 0xD2 ) ; /* PCA0 Capture 5 Low */
122 SFR( PCA0CPH5, 0xD3 ) ; /* PCA0 Capture 5 High */
123 SFR( P0SKIP, 0xD4 ) ; /* PORT 0 SKIP */
124 SFR( P1SKIP, 0xD5 ) ; /* PORT 1 SKIP */
125 SFR( P2SKIP, 0xD6 ) ; /* PORT 2 SKIP */
126 SFR( P0MAT, 0xD7 ) ; /* Port 0 Match */
127 SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
128 SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
129 SFR( PCA0CPM0, 0xDA ) ; /* PCA0 Module 0 Mode Register */
130 SFR( PCA0CPM1, 0xDB ) ; /* PCA0 Module 1 Mode Register */
131 SFR( PCA0CPM2, 0xDC ) ; /* PCA0 Module 2 Mode Register */
132 SFR( PCA0CPM3, 0xDD ) ; /* PCA0 Module 3 Mode Register */
133 SFR( PCA0CPM4, 0xDE ) ; /* PCA0 Module 4 Mode Register */
134 SFR( PCA0PWM, 0xDF ) ; /* PCA0 PWM Configuration */
135 SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
136 SFR( XBR0, 0xE1 ) ; /* Port Mux Configuration Register 0 */
137 SFR( XBR1, 0xE2 ) ; /* Port Mux Configuration Register 1 */
138 SFR( XBR2, 0xE3 ) ; /* Port Mux Configuration Register 2 */
139 SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 Configuration Register */
140 SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
141 SFR( EIE2, 0xE7 ) ; /* EXTERNAL INTERRUPT ENABLE 2 */
142 SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
143 SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
144 SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
145 SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
146 SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
147 SFR( PCA0CPL3, 0xED ) ; /* PCA0 Capture 3 Low */
148 SFR( PCA0CPH3, 0xEE ) ; /* PCA0 Capture 3 High */
149 SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
150 SFR( B, 0xF0 ) ; /* B REGISTER */
151 SFR( P0MDIN, 0xF1 ) ; /* Port 0 Input Mode Configuration */
152 SFR( P1MDIN, 0xF2 ) ; /* Port 1 Input Mode Configuration */
153 SFR( P2MDIN, 0xF3 ) ; /* Port 2 Input Mode Configuration */
154 SFR( SMB0ADR, 0xF4 ) ; /* SMBus Slave Address */
155 SFR( SMB0ADM, 0xF5 ) ; /* SMBus Slave Address Mask */
156 SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
157 SFR( EIP2, 0xF7 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
158 SFR( SPI0CN, 0xF8 ) ; /* SPI0 Control */
159 SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
160 SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
161 SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
162 SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
163 SFR( PCA0CPL4, 0xFD ) ; /* PCA0 Capture 4 Low */
164 SFR( PCA0CPH4, 0xFE ) ; /* PCA0 Capture 4 High */
165 SFR( VDM0CN, 0xFF ) ; /* VDD Monitor Control */
166
167 /* Page 0x0F only */
168 SFR( TOFFL, 0x85 ) ; /* Temperature Offset Low */
169 SFR( TOFFH, 0x86 ) ; /* Temperature Offset High */
170 SFR( CRC0DAT, 0x91 ) ; /* CRC0 Data */
171 SFR( CRC0CN, 0x92 ) ; /* CRC0 Control */
172 SFR( CRC0IN, 0x93 ) ; /* CRC0 Input */
173 SFR( CRC0FLIP, 0x95 ) ; /* CRC0 Flip */
174 SFR( CRC0AUTO, 0x96 ) ; /* CRC0 Automatic Control */
175 SFR( CRC0CNT, 0x97 ) ; /* CRC0 Automatic Flash Sector Count */
176 SFR( P0DRV, 0xA4 ) ; /* Port 0 Drive Strength */
177 SFR( P1DRV, 0xA5 ) ; /* Port 1 Drive Strength */
178 SFR( P2DRV, 0xA6 ) ; /* Port 2 Drive Strength */
179 SFR( ADC0PWR, 0xBA) ; /* ADC0 Burst Mode Power-Up Time */
180 SFR( ADC0TK, 0xBD) ; /* ADC0 Tracking Control */
181
182
183 /* WORD/DWORD Registers */
184
185 /* page 0x00 */
186 SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
187 SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
188 SFR16E( TMR3RL, 0x9392 ) ; /* Timer 3 reload word */
189 SFR16E( TMR3, 0x9594 ) ; /* Timer 3 counter word */
190 SFR16E( ADC0, 0xBEBD ) ; /* ADC0 word */
191 SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
192 SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
193 SFR16E( TMR2RL, 0xCBCA ) ; /* Timer 2 reload word */
194 SFR16E( TMR2, 0xCDCC ) ; /* Timer 2 counter word */
195 SFR16E( TMR2RL, 0xCBCA ) ; /* Timer 2 Reload word */
196 SFR16E( PCA0, 0xFAF9 ) ; /* PCA0 counter word */
197 SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA0 Capture 0 word */
198 SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA0 Capture 1 word */
199 SFR16E( PCA0CP2, 0xECEB ) ; /* PCA0 Capture 2 word */
200 SFR16E( PCA0CP3, 0xEEED ) ; /* PCA0 Capture 3 word */
201 SFR16E( PCA0CP4, 0xFEFD ) ; /* PCA0 Capture 4 word */
202 SFR16E( PCA0CP5, 0xD3D4 ) ; /* PCA0 Capture 5 word */
203
204 /* Page 0x0F */
205 SFR16E( TOFF, 0x8685 ) ; /* TEMPERATURE SENSOR OFFSET WORD */
206
207 /* BIT Registers */
208
209 /* P0 0x80 */
210 SBIT( P0_0, 0x80, 0 ) ;
211 SBIT( P0_1, 0x80, 1 ) ;
212 SBIT( P0_2, 0x80, 2 ) ;
213 SBIT( P0_3, 0x80, 3 ) ;
214 SBIT( P0_4, 0x80, 4 ) ;
215 SBIT( P0_5, 0x80, 5 ) ;
216 SBIT( P0_6, 0x80, 6 ) ;
217 SBIT( P0_7, 0x80, 7 ) ;
218
219 /* TCON 0x88 */
220 SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
221 SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
222 SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
223 SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
224 SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
225 SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
226 SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
227 SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
228
229 /* P1 0x90 */
230 SBIT( P1_0, 0x90, 0 ) ;
231 SBIT( P1_1, 0x90, 1 ) ;
232 SBIT( P1_2, 0x90, 2 ) ;
233 SBIT( P1_3, 0x90, 3 ) ;
234 SBIT( P1_4, 0x90, 4 ) ;
235 SBIT( P1_5, 0x90, 5 ) ;
236 SBIT( P1_6, 0x90, 6 ) ;
237 SBIT( P1_7, 0x90, 7 ) ;
238
239 /* SCON0 0x98 */
240 SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
241 SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
242 SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
243 SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
244 SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
245 SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
246 SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
247 SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
248 SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
249 SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
250 SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
251 SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
252 SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
253 SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
254
255 /* P2 0xA0 */
256 SBIT( P2_0, 0xA0, 0 ) ;
257 SBIT( P2_1, 0xA0, 1 ) ;
258 SBIT( P2_2, 0xA0, 2 ) ;
259 SBIT( P2_3, 0xA0, 3 ) ;
260 SBIT( P2_4, 0xA0, 4 ) ;
261 SBIT( P2_5, 0xA0, 5 ) ;
262 SBIT( P2_6, 0xA0, 6 ) ;
263 SBIT( P2_7, 0xA0, 7 ) ;
264
265 /* IE 0xA8 */
266 SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
267 SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
268 SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
269 SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
270 SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
271 SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
272 SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
273 SBIT( IEGF0, 0xA8, 6 ) ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
274 SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
275
276 /* SPI1CN 0xB0 */
277 SBIT( SPI1EN, 0xB0, 0 ) ; /* SPI1 Enable */
278 SBIT( TXBMT1, 0xB0, 1 ) ; /* SPI1 Transmit Buffer Empty */
279 SBIT( NSS1MD0, 0xB0, 2 ) ; /* SPI1 Slave Select Mode bit-0 */
280 SBIT( NSS1MD1, 0xB0, 3 ) ; /* SPI1 Slave Select Mode bit-1 */
281 SBIT( RXOVRN1, 0xB0, 4 ) ; /* SPI1 Receive Overrun Flag */
282 SBIT( MODF1, 0xB0, 5 ) ; /* SPI1 Mode Fault Flag */
283 SBIT( WCOL1, 0xB0, 6 ) ; /* SPI1 Write Collision Flag */
284 SBIT( SPIF1, 0xB0, 7 ) ; /* SPI1 Interrupt Flag */
285
286 /* IP 0xB8 */
287 SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
288 SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
289 SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
290 SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
291 SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
292 SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
293 SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
294
295 /* SMB0CN 0xC0 */
296 SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
297 SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
298 SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
299 SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
300 SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
301 SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
302 SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
303 SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
304
305 /* TMR2CN 0xC8 */
306 SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
307 SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
308 SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
309 SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
310 SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
311 SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
312 SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
313
314 /* PSW 0xD0 */
315 SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
316 SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
317 SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
318 SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
319 SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
320 SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
321 SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
322 SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
323
324 /* PCA0CN 0xD8 */
325 SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
326 SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
327 SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
328 SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
329 SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
330
331 /* ADC0CN 0xE8 */
332 SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
333 SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
334 SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
335 SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
336 SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
337 SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
338 SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
339 SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
340
341 /* SPI0CN 0xF8 */
342 SBIT( SPI0EN, 0xF8, 0 ) ; /* SPI0 Enable */
343 SBIT( TXBMT0, 0xF8, 1 ) ; /* SPI0 Transmit Buffer Empty */
344 SBIT( NSS0MD0, 0xF8, 2 ) ; /* SPI0 Slave Select Mode bit-0 */
345 SBIT( NSS0MD1, 0xF8, 3 ) ; /* SPI0 Slave Select Mode bit-1 */
346 SBIT( RXOVRN0, 0xF8, 4 ) ; /* SPI0 Receive Overrun Flag */
347 SBIT( MODF0, 0xF8, 5 ) ; /* SPI0 Mode Fault Flag */
348 SBIT( WCOL0, 0xF8, 6 ) ; /* SPI0 Write Collision Flag */
349 SBIT( SPIF0, 0xF8, 7 ) ; /* SPI0 Interrupt Flag */
350
351
352 /* Indirectly accessed registers */
353
354 /* smaRTClock Internal Registers */
355 #define CAPTURE0 0x00 /* smaRTClock Capture register 0 */
356 #define CAPTURE1 0x01 /* smaRTClock Capture register 1 */
357 #define CAPTURE2 0x02 /* smaRTClock Capture register 2 */
358 #define CAPTURE3 0x03 /* smaRTClock Capture register 3 */
359 #define RTC0CN 0x04 /* smaRTClock Control */
360 #define RTC0XCN 0x05 /* smaRTClock Oscillator Control */
361 #define RTC0XCF 0x06 /* smaRTClock Oscillator Configuration */
362 #define RTC0PIN 0x07 /* smaRTClock Pin Configuration */
363 #define ALARM0 0x08 /* smaRTClock Alarm Register 0 */
364 #define ALARM1 0x09 /* smaRTClock Alarm Register 1 */
365 #define ALARM2 0x0A /* smaRTClock Alarm Register 2 */
366 #define ALARM3 0x0B /* smaRTClock Alarm Register 3 */
367
368
369 /* Predefined SFR Bit Masks */
370
371 /* PCON 0x87 */
372 #define PCON_IDLE (1<<0) /* PCON */
373 #define PCON_STOP (1<<1) /* PCON */
374
375 /* CKON 0x8E */
376 #define T0M (1<<2) /* CKCON Timer 0 Clock Select */
377 #define T1M (1<<3) /* CKCON Timer 1 Clock Select */
378
379 /* PSCTL 0x8F */
380 #define PSWE (1<<0) /* Program Store Write Enable */
381 #define PSEE (1<<1) /* Program Store Erase Enable */
382 #define SFLE (1<<2) /* Scratchpad Flash Access Enable */
383
384 /* EIE1 0xE6 */
385 #define ESMB0 (1<<0) /* Enable SMBus (SMB0) Interrupt */
386 #define ERTC0A (1<<1) /* Enable smaRTClock Alarm Interrupts */
387 #define EWADC0 (1<<2) /* Enable Window Comparison ADC0 Int. */
388 #define EADC0 (1<<3) /* Enable ADC0 Convert Complete Int. */
389 #define EPCA0 (1<<4) /* Enable PCA0 Interrupt */
390 #define ECP0 (1<<5) /* Enable Comparator0 (CP0) Interrupt */
391 #define ECP1 (1<<6) /* Enable Comparator1 (CP1) Interrupt */
392 #define ET3 (1<<7) /* Enable Timer 3 Interrupt */
393
394 /* RSTSRC */
395 #define PINRSF (1<<0) /* HW Pin Reset Flag */
396 #define PORSF (1<<1) /* Power-on/fail Reset Rlag */
397 #define MCDRSF (1<<2) /* Missing Clock Detector Reset Rlag */
398 #define WDTRSF (1<<3) /* Watchdog Timer Reset Rlag */
399 #define SWRSF (1<<4) /* Software Force/Reset Rlag */
400 #define C0RSEF (1<<5) /* Comparator0 Reset Rlag */
401 #define FERROR (1<<6) /* Flash Error Reset Rlag */
402 #define RTC0RE (1<<7) /* smaRTClock Reset Rlag */
403
404 /* PCA0CPMn */
405 #define ECCF (1<<0) /* Capture/Compare Flag Interrupt En. */
406 #define PWM (1<<1) /* Pulse Width Modulation Mode Enable */
407 #define TOG (1<<2) /* Toggle Function Enable */
408 #define MAT (1<<3) /* Match Function Enable */
409 #define CAPN (1<<4) /* Capture Negative Function Enable */
410 #define CAPP (1<<5) /* Capture Positive Function Enable. */
411 #define ECOM (1<<6) /* Comparator Function Enable. */
412 #define PWM16 (1<<7) /* 16-bit Pulse Width Modulation Enable*/
413
414 /* XBR0 0xE1 */
415 #define URT0E (1<<0) /* UART0 I/O enable */
416 #define SPI0E (1<<1) /* SPI0 I/O Enable */
417 #define SMB0E (1<<2) /* SMBus I/O Enable */
418 #define SYSCKE (1<<3) /* SYSCLK Output Enable. */
419 #define CP0E (1<<4) /* Comparator0 Output Enable */
420 #define CP0AE (1<<5) /* Comparator0 Asynchronous Output En. */
421 #define CP1E (1<<6) /* Comparator1 Output Enable */
422 #define CP1AE (1<<7) /* Comparator1 Asynchronous Output En. */
423
424 /* XBR1 0xE2 */
425 #define PCA0ME0 (1<<0) /* PCA0 Module I/O Enable bit-0 */
426 #define PCA0ME1 (1<<1) /* PCA0 Module I/O Enable bit-1 */
427 #define PCA0ME2 (1<<2) /* PCA0 Module I/O Enable bit-2 */
428 #define ECIE (1<<3) /* PCA0 Ext. Counter Input Enable */
429 #define T0E (1<<4) /* Timer0 Input Enable */
430 #define T1E (1<<5) /* Timer1 Input Enable */
431 #define SPI1E (1<<6) /* SPI1 I/O Enable */
432
433 /* XBR2 0xE3 */
434 #define XBARE (1<<6) /* Crossbar Enable */
435 #define WEAKPUD (1<<7) /* Port I/O Weak Pullup Disable */
436
437 /* Interrupts */
438
439 #define INT_EXT0 0 /* External Interrupt 0*/
440 #define INT_TIMER0 1 /* Timer0 Overflow */
441 #define INT_EXT1 2 /* External Interrupt 1 */
442 #define INT_TIMER1 3 /* Timer1 Overflow */
443 #define INT_UART0 4 /* Serial Port 0 */
444 #define INT_TIMER2 5 /* Timer2 Overflow */
445 #define INT_SPI0 6 /* SPI0 */
446 #define INT_SMBUS0 7 /* SMBus0 Interface */
447 #define INT_ALARM 8 /* smaRTClock Alarm */
448 #define INT_ADC0_WINDOW 9 /* ADC0 Window Comparison */
449 #define INT_ADC0_EOC 10 /* ADC0 End Of Conversion */
450 #define INT_PCA0 11 /* PCA0 Peripheral */
451 #define INT_CP0 12 /* Comparator 0 */
452 #define INT_CP1 13 /* Comparator 1 */
453 #define INT_TIMER3 14 /* Timer3 Overflow */
454 #define INT_VWARN 15 /* VDD/DC+ Supply Monitor early warning */
455 #define INT_MATCH 16 /* Port Match */
456 #define INT_OSCFAIL 17 /* smaRTClock Oscillator Fail */
457 #define INT_SPI1 18 /* SPI1 */
458
459 /* aliases - these map alternative names to names use in the datasheet */
460 #define SCON SCON0 /* Serial Port Control */
461 #define SBUF SBUF0 /* Serial Port Buffer */
462 #define T2CON TMR2CN /* Timer 2 control */
463 #define RCAP2 TMR2RL /* Timer 2 capture register word */
464 #define RCAP2L TMR2RLL /* Timer 2 capture register - low byte */
465 #define RCAP2H TMR2RLH /* Timer 2 capture register - high byte */
466 #define T2 TMR2 /* Timer 2 - word */
467 #define TL2 TMR2L /* Timer 2 - low byte */
468 #define TH2 TMR2H /* Timer 2 - high byte */
469 #define PRT0MX XBR0 /* Port Mux Configuration Register 0 */
470 #define PRT1MX XBR1 /* Port Mux Configuration Register 1 */
471 #define PRT2MX XBR2 /* Port Mux Configuration Register 2 */
472 #define IT01CF INT01CF /* INT0/INT1 Configuration Register */
473 #define P0MODE P0MDIN /* Port 0 Input Mode Configuration */
474 #define P1MODE P1MDIN /* Port 1 Input Mode Configuration */
475 #define P2MODE P2MDIN /* Port 2 Input Mode Configuration */
476 #define CP0OEN CP0E /* Comparator 0 Output Enable bit */
477 #define CP0AOEN CP0AE /* Comparator 0 Asynchronous Output En. bit */
478
479
480 #endif /* C8051F920_H */
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