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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / C8051T600.h
blob2ae31c3246d9f85ffebed7f3e27a6318a8317209
1 /*-------------------------------------------------------------------------
2 C8051T600.h - Register Declarations for the SiLabs C8051T60x Processor
3 Range
4
5 Copyright (C) 2008, Steven Borley, steven.borley@partnerelectronics.com
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 #ifndef C8051T600_H
31 #define C8051T600_H
32
33 #include <compiler.h>
34
35
36 /* BYTE Registers */
37
38 SFR( P0, 0x80 ) ; /* PORT 0 */
39 SFR( SP, 0x81 ) ; /* STACK POINTER */
40 SFR( DPL, 0x82 ) ; /* DATA POINTER - LOW BYTE */
41 SFR( DPH, 0x83 ) ; /* DATA POINTER - HIGH BYTE */
42 SFR( PCON, 0x87 ) ; /* POWER CONTROL */
43 SFR( TCON, 0x88 ) ; /* TIMER CONTROL */
44 SFR( TMOD, 0x89 ) ; /* TIMER MODE */
45 SFR( TL0, 0x8A ) ; /* TIMER 0 - LOW BYTE */
46 SFR( TL1, 0x8B ) ; /* TIMER 1 - LOW BYTE */
47 SFR( TH0, 0x8C ) ; /* TIMER 0 - HIGH BYTE */
48 SFR( TH1, 0x8D ) ; /* TIMER 1 - HIGH BYTE */
49 SFR( CKCON, 0x8E ) ; /* CLOCK CONTROL */
50 SFR( SCON, 0x98 ) ; /* SERIAL PORT CONTROL */
51 SFR( SCON0, 0x98 ) ; /* SERIAL PORT CONTROL */
52 SFR( SBUF, 0x99 ) ; /* SERIAL PORT BUFFER */
53 SFR( SBUF0, 0x99 ) ; /* SERIAL PORT BUFFER */
54 SFR( CPT0MD, 0x9D ) ; /* COMPARATOR 0 MODE SELECTION */
55 SFR( CPT0MX, 0x9F ) ; /* COMPARATOR 0 MUX SELECTION */
56 SFR( TOFFL, 0xA2 ) ; /* TEMPERATURE SENSOR OFFSET - LOW BYTE */
57 SFR( TOFFH, 0xA3 ) ; /* TEMPERATURE SENSOR OFFSET - HIGH BYTE */
58 SFR( P0MDOUT, 0xA4 ) ; /* PORT 0 OUTPUT MODE CONFIGURATION */
59 SFR( IE, 0xA8 ) ; /* INTERRUPT ENABLE */
60 SFR( OSCXCN, 0xB1 ) ; /* EXTERNAL OSCILLATOR CONTROL */
61 SFR( OSCICN, 0xB2 ) ; /* INTERNAL OSCILLATOR CONTROL */
62 SFR( OSCICL, 0xB3 ) ; /* INTERNAL OSCILLATOR CALIBRATION */
63 SFR( IP, 0xB8 ) ; /* INTERRUPT PRIORITY */
64 SFR( AMX0SL, 0xBB ) ; /* ADC 0 MUX CHANNEL SELECTION */
65 SFR( ADC0CF, 0xBC ) ; /* ADC 0 CONFIGURATION */
66 SFR( ADC0L, 0xBD ) ; /* ADC 0 DATA - LOW BYTE */
67 SFR( ADC0H, 0xBE ) ; /* ADC 0 DATA - HIGH BYTE */
68 SFR( SMB0CN, 0xC0 ) ; /* SMBUS CONTROL */
69 SFR( SMB0CF, 0xC1 ) ; /* SMBUS CONFIGURATION */
70 SFR( SMB0DAT, 0xC2 ) ; /* SMBUS DATA */
71 SFR( ADC0GTL, 0xC3 ) ; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
72 SFR( ADC0GTH, 0xC4 ) ; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
73 SFR( ADC0LTL, 0xC5 ) ; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
74 SFR( ADC0LTH, 0xC6 ) ; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
75 SFR( REG0CN, 0xC7 ) ; /* Voltage Regulator Control */
76 SFR( T2CON, 0xC8 ) ; /* TIMER 2 CONTROL */
77 SFR( TMR2CN, 0xC8 ) ; /* TIMER 2 CONTROL */
78 SFR( RCAP2L, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
79 SFR( TMR2RLL, 0xCA ) ; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
80 SFR( RCAP2H, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
81 SFR( TMR2RLH, 0xCB ) ; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
82 SFR( TL2, 0xCC ) ; /* TIMER 2 - LOW BYTE */
83 SFR( TMR2L, 0xCC ) ; /* TIMER 2 - LOW BYTE */
84 SFR( TH2, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
85 SFR( TMR2H, 0xCD ) ; /* TIMER 2 - HIGH BYTE */
86 SFR( PSW, 0xD0 ) ; /* PROGRAM STATUS WORD */
87 SFR( REF0CN, 0xD1 ) ; /* VOLTAGE REFERENCE 0 CONTROL */
88 SFR( PCA0CN, 0xD8 ) ; /* PCA CONTROL */
89 SFR( PCA0MD, 0xD9 ) ; /* PCA MODE */
90 SFR( PCA0CPM0, 0xDA ) ; /* PCA MODULE 0 MODE REGISTER */
91 SFR( PCA0CPM1, 0xDB ) ; /* PCA MODULE 1 MODE REGISTER */
92 SFR( PCA0CPM2, 0xDC ) ; /* PCA MODULE 2 MODE REGISTER */
93 SFR( ACC, 0xE0 ) ; /* ACCUMULATOR */
94 SFR( PRT0MX, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
95 SFR( XBR0, 0xE1 ) ; /* PORT MUX CONFIGURATION REGISTER 0 */
96 SFR( PRT1MX, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
97 SFR( XBR1, 0xE2 ) ; /* PORT MUX CONFIGURATION REGISTER 1 */
98 SFR( PRT2MX, 0xE3 ) ; /* PORT MUX CONFIGURATION REGISTER 2 */
99 SFR( XBR2, 0xE3 ) ; /* PORT MUX CONFIGURATION REGISTER 2 */
100 SFR( IT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
101 SFR( INT01CF, 0xE4 ) ; /* INT0/INT1 CONFIGURATION REGISTER */
102 SFR( EIE1, 0xE6 ) ; /* EXTERNAL INTERRUPT ENABLE 1 */
103 SFR( ADC0CN, 0xE8 ) ; /* ADC 0 CONTROL */
104 SFR( PCA0CPL1, 0xE9 ) ; /* PCA CAPTURE 1 LOW */
105 SFR( PCA0CPH1, 0xEA ) ; /* PCA CAPTURE 1 HIGH */
106 SFR( PCA0CPL2, 0xEB ) ; /* PCA CAPTURE 2 LOW */
107 SFR( PCA0CPH2, 0xEC ) ; /* PCA CAPTURE 2 HIGH */
108 SFR( RSTSRC, 0xEF ) ; /* RESET SOURCE */
109 SFR( B, 0xF0 ) ; /* B REGISTER */
110 SFR( P0MODE, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
111 SFR( P0MDIN, 0xF1 ) ; /* PORT 0 INPUT MODE CONFIGURATION */
112 SFR( EIP1, 0xF6 ) ; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
113 SFR( CPT0CN, 0xF8 ) ; /* COMPARATOR 0 CONTROL */
114 SFR( PCA0L, 0xF9 ) ; /* PCA COUNTER LOW */
115 SFR( PCA0H, 0xFA ) ; /* PCA COUNTER HIGH */
116 SFR( PCA0CPL0, 0xFB ) ; /* PCA CAPTURE 0 LOW */
117 SFR( PCA0CPH0, 0xFC ) ; /* PCA CAPTURE 0 HIGH */
118
119
120 /* WORD/DWORD Registers */
121
122 SFR16E( TMR0, 0x8C8A ) ; /* TIMER 0 COUNTER */
123 SFR16E( TMR1, 0x8D8B ) ; /* TIMER 1 COUNTER */
124 SFR16E( TOFF, 0xA3A2 ) ; /* TEMPERATURE SENSOR OFFSET WORD */
125 SFR16E( ADC0, 0xAEAD ) ; /* ADC0 DATA WORD */
126 SFR16E( ADC0GT, 0xC4C3 ) ; /* ADC 0 GREATER-THAN REGISTER WORD */
127 SFR16E( ADC0LT, 0xC6C5 ) ; /* ADC 0 LESS-THAN REGISTER WORD */
128 SFR16E( TMR2, 0xCDCC ) ; /* TIMER 2 COUNTER */
129 SFR16E( RCAP2, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
130 SFR16E( TMR2RL, 0xCBCA ) ; /* TIMER 2 CAPTURE REGISTER WORD */
131 SFR16E( PCA0, 0xFAF9 ) ; /* PCA COUNTER */
132 SFR16E( PCA0CP0, 0xFCFB ) ; /* PCA CAPTURE 0 WORD */
133 SFR16E( PCA0CP1, 0xEAE9 ) ; /* PCA CAPTURE 1 WORD */
134 SFR16E( PCA0CP2, 0xECEB ) ; /* PCA CAPTURE 2 WORD */
135
136
137 /* BIT Registers */
138
139 /* P0 0x80 */
140 SBIT( P0_0, 0x80, 0 ) ;
141 SBIT( P0_1, 0x80, 1 ) ;
142 SBIT( P0_2, 0x80, 2 ) ;
143 SBIT( P0_3, 0x80, 3 ) ;
144 SBIT( P0_4, 0x80, 4 ) ;
145 SBIT( P0_5, 0x80, 5 ) ;
146 SBIT( P0_6, 0x80, 6 ) ;
147 SBIT( P0_7, 0x80, 7 ) ;
148
149 /* TCON 0x88 */
150 SBIT( IT0, 0x88, 0 ) ; /* TCON.0 - EXT. INTERRUPT 0 TYPE */
151 SBIT( IE0, 0x88, 1 ) ; /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
152 SBIT( IT1, 0x88, 2 ) ; /* TCON.2 - EXT. INTERRUPT 1 TYPE */
153 SBIT( IE1, 0x88, 3 ) ; /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
154 SBIT( TR0, 0x88, 4 ) ; /* TCON.4 - TIMER 0 ON/OFF CONTROL */
155 SBIT( TF0, 0x88, 5 ) ; /* TCON.5 - TIMER 0 OVERFLOW FLAG */
156 SBIT( TR1, 0x88, 6 ) ; /* TCON.6 - TIMER 1 ON/OFF CONTROL */
157 SBIT( TF1, 0x88, 7 ) ; /* TCON.7 - TIMER 1 OVERFLOW FLAG */
158
159 /* SCON 0x98 */
160 SBIT( RI, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
161 SBIT( RI0, 0x98, 0 ) ; /* SCON.0 - RECEIVE INTERRUPT FLAG */
162 SBIT( TI, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
163 SBIT( TI0, 0x98, 1 ) ; /* SCON.1 - TRANSMIT INTERRUPT FLAG */
164 SBIT( RB8, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
165 SBIT( RB80, 0x98, 2 ) ; /* SCON.2 - RECEIVE BIT 8 */
166 SBIT( TB8, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
167 SBIT( TB80, 0x98, 3 ) ; /* SCON.3 - TRANSMIT BIT 8 */
168 SBIT( REN, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
169 SBIT( REN0, 0x98, 4 ) ; /* SCON.4 - RECEIVE ENABLE */
170 SBIT( SM2, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
171 SBIT( MCE0, 0x98, 5 ) ; /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
172 SBIT( SM0, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
173 SBIT( S0MODE, 0x98, 7 ) ; /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
174
175 /* IE 0xA8 */
176 SBIT( EX0, 0xA8, 0 ) ; /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
177 SBIT( ET0, 0xA8, 1 ) ; /* IE.1 - TIMER 0 INTERRUPT ENABLE */
178 SBIT( EX1, 0xA8, 2 ) ; /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
179 SBIT( ET1, 0xA8, 3 ) ; /* IE.3 - TIMER 1 INTERRUPT ENABLE */
180 SBIT( ES, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
181 SBIT( ES0, 0xA8, 4 ) ; /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
182 SBIT( ET2, 0xA8, 5 ) ; /* IE.5 - TIMER 2 INTERRUPT ENABLE */
183 SBIT( IEGF0, 0xA8, 6 ) ; /* IE.6 - GENERAL PURPOSE FLAG 0 */
184 SBIT( EA, 0xA8, 7 ) ; /* IE.7 - GLOBAL INTERRUPT ENABLE */
185
186 /* IP 0xB8 */
187 SBIT( PX0, 0xB8, 0 ) ; /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
188 SBIT( PT0, 0xB8, 1 ) ; /* IP.1 - TIMER 0 PRIORITY */
189 SBIT( PX1, 0xB8, 2 ) ; /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
190 SBIT( PT1, 0xB8, 3 ) ; /* IP.3 - TIMER 1 PRIORITY */
191 SBIT( PS, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
192 SBIT( PS0, 0xB8, 4 ) ; /* IP.4 - SERIAL PORT PRIORITY */
193 SBIT( PT2, 0xB8, 5 ) ; /* IP.5 - TIMER 2 PRIORITY */
194
195 /* SMB0CN 0xC0 */
196 SBIT( SI, 0xC0, 0 ) ; /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
197 SBIT( ACK, 0xC0, 1 ) ; /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
198 SBIT( ARBLOST, 0xC0, 2 ) ; /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
199 SBIT( ACKRQ, 0xC0, 3 ) ; /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
200 SBIT( STO, 0xC0, 4 ) ; /* SMB0CN.4 - SMBUS 0 STOP FLAG */
201 SBIT( STA, 0xC0, 5 ) ; /* SMB0CN.5 - SMBUS 0 START FLAG */
202 SBIT( TXMODE, 0xC0, 6 ) ; /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
203 SBIT( MASTER, 0xC0, 7 ) ; /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
204
205 /* TMR2CN 0xC8 */
206 SBIT( T2XCLK, 0xC8, 0 ) ; /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
207 SBIT( TR2, 0xC8, 2 ) ; /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
208 SBIT( T2SPLIT, 0xC8, 3 ) ; /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
209 SBIT( TF2LEN, 0xC8, 5 ) ; /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
210 SBIT( TF2L, 0xC8, 6 ) ; /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
211 SBIT( TF2, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
212 SBIT( TF2H, 0xC8, 7 ) ; /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
213
214 /* PSW 0xD0 */
215 SBIT( PARITY, 0xD0, 0 ) ; /* PSW.0 - ACCUMULATOR PARITY FLAG */
216 SBIT( F1, 0xD0, 1 ) ; /* PSW.1 - FLAG 1 */
217 SBIT( OV, 0xD0, 2 ) ; /* PSW.2 - OVERFLOW FLAG */
218 SBIT( RS0, 0xD0, 3 ) ; /* PSW.3 - REGISTER BANK SELECT 0 */
219 SBIT( RS1, 0xD0, 4 ) ; /* PSW.4 - REGISTER BANK SELECT 1 */
220 SBIT( F0, 0xD0, 5 ) ; /* PSW.5 - FLAG 0 */
221 SBIT( AC, 0xD0, 6 ) ; /* PSW.6 - AUXILIARY CARRY FLAG */
222 SBIT( CY, 0xD0, 7 ) ; /* PSW.7 - CARRY FLAG */
223
224 /* PCA0CN 0xD8 */
225 SBIT( CCF0, 0xD8, 0 ) ; /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
226 SBIT( CCF1, 0xD8, 1 ) ; /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
227 SBIT( CCF2, 0xD8, 2 ) ; /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
228 SBIT( CR, 0xD8, 6 ) ; /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
229 SBIT( CF, 0xD8, 7 ) ; /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
230
231 /* ADC0CN 0xE8 */
232 SBIT( AD0CM0, 0xE8, 0 ) ; /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
233 SBIT( AD0CM1, 0xE8, 1 ) ; /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
234 SBIT( AD0CM2, 0xE8, 2 ) ; /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
235 SBIT( AD0WINT, 0xE8, 3 ) ; /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
236 SBIT( AD0BUSY, 0xE8, 4 ) ; /* ADC0CN.4 - ADC 0 BUSY FLAG */
237 SBIT( AD0INT, 0xE8, 5 ) ; /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
238 SBIT( AD0TM, 0xE8, 6 ) ; /* ADC0CN.6 - ADC 0 TRACK MODE */
239 SBIT( AD0EN, 0xE8, 7 ) ; /* ADC0CN.7 - ADC 0 ENABLE */
240
241 /* CPT0CN 0xF8 */
242 SBIT( CP0HYN0, 0xF8, 0 ) ; /* CPT0CN.0 - Comp.0 Neg. Hysteresis Control Bit0*/
243 SBIT( CP0HYN1, 0xF8, 1 ) ; /* CPT0CN.1 - Comp.0 Neg. Hysteresis Control Bit1*/
244 SBIT( CP0HYP0, 0xF8, 2 ) ; /* CPT0CN.2 - Comp.0 Pos. Hysteresis Control Bit0*/
245 SBIT( CP0HYP1, 0xF8, 3 ) ; /* CPT0CN.3 - Comp.0 Pos. Hysteresis Control Bit1*/
246 SBIT( CP0FIF, 0xF8, 4 ) ; /* CPT0CN.4 - Comparator0 Falling-Edge Int. Flag */
247 SBIT( CP0RIF, 0xF8, 5 ) ; /* CPT0CN.5 - Comparator0 Rising-Edge Int. Flag */
248 SBIT( CP0OUT, 0xF8, 6 ) ; /* CPT0CN.6 - Comparator0 Output State Flag */
249 SBIT( CP0EN, 0xF8, 7 ) ; /* CPT0CN.7 - Comparator0 Enable Bit */
250
251
252 /* Predefined SFR Bit Masks */
253
254 #define PCON_IDLE 0x01 /* PCON */
255 #define PCON_STOP 0x02 /* PCON */
256 #define T1M 0x10 /* CKCON */
257 #define PSWE 0x01 /* PSCTL */
258 #define PSEE 0x02 /* PSCTL */
259 #define ECP0F 0x10 /* EIE1 */
260 #define ECP0R 0x20 /* EIE1 */
261 #define PORSF 0x02 /* RSTSRC */
262 #define SWRSF 0x10 /* RSTSRC */
263 #define ECCF 0x01 /* PCA0CPMn */
264 #define PWM 0x02 /* PCA0CPMn */
265 #define TOG 0x04 /* PCA0CPMn */
266 #define MAT 0x08 /* PCA0CPMn */
267 #define CAPN 0x10 /* PCA0CPMn */
268 #define CAPP 0x20 /* PCA0CPMn */
269 #define ECOM 0x40 /* PCA0CPMn */
270 #define PWM16 0x80 /* PCA0CPMn */
271 #define CP0E 0x10 /* XBR1 */
272 #define CP0OEN 0x10 /* XBR1 */
273 #define CP0AE 0x20 /* XBR1 */
274 #define CP0AOEN 0x20 /* XBR1 */
275
276 /* Interrupts */
277
278 #define INT_EXT0 0 /* External Interrupt 0 */
279 #define INT_TIMER0 1 /* Timer0 Overflow */
280 #define INT_EXT1 2 /* External Interrupt 1 */
281 #define INT_TIMER1 3 /* Timer1 Overflow */
282 #define INT_UART0 4 /* Serial Port 0 */
283 #define INT_TIMER2 5 /* Timer2 Overflow */
284 #define INT_SMBUS0 6 /* SMBus0 Interface */
285 #define INT_ADC0_WINDOW 7 /* ADC0 Window Comparison */
286 #define INT_ADC0_EOC 8 /* ADC0 End Of Conversion */
287 #define INT_PCA0 9 /* PCA0 Peripheral */
288 #define INT_CP0F 10 /* Comparator0 falling edge */
289 #define INT_CP0R 11 /* Comparator1 rising edge */
290
291 #endif
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