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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / EFM8BB1.h
blobc8e9a04c3004d28c790b84ac9f5033ded14c5daa
1 /*-------------------------------------------------------------------------
2 * EFM8BB1.h - Register Declarations for the SiLabs EFM8BB1 Processor
3 * Range
4 *
5 * Copyright (C) 2015, Kharitonov Dmitriy, kharpost@altlinux.org
6 *
7 * This library is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2, or (at your option) any
10 * later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this library; see the file COPYING. If not, write to the
19 * Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 *
22 * As a special exception, if you link this library with other files,
23 * some of which are compiled with SDCC, to produce an executable,
24 * this library does not by itself cause the resulting executable to
25 * be covered by the GNU General Public License. This exception does
26 * not however invalidate any other reasons why the executable file
27 * might be covered by the GNU General Public License.
28 * -------------------------------------------------------------------------*/
29 #ifndef EFM8BB1_H
30 #define EFM8BB1_H
31
32 /* Supported Devices:
33 EFM8BB10F2G
34 EFM8BB10F4G
35 EFM8BB10F8G
36 */
37
38 #include <compiler.h>
39
40 /* BYTE Registers */
41
42 SFR( P0, 0x80 ); /* PORT 0 */
43 SFR( SP, 0x81 ); /* STACK POINTER */
44 SFR( DPL, 0x82 ); /* DATA POINTER - LOW BYTE */
45 SFR( DPH, 0x83 ); /* DATA POINTER - HIGH BYTE */
46 SFR( PCON0, 0x87 ); /* POWER CONTROL */
47 SFR( TCON, 0x88 ); /* TIMER CONTROL */
48 SFR( TMOD, 0x89 ); /* TIMER MODE */
49 SFR( TL0, 0x8A ); /* TIMER 0 - LOW BYTE */
50 SFR( TL1, 0x8B ); /* TIMER 1 - LOW BYTE */
51 SFR( TH0, 0x8C ); /* TIMER 0 - HIGH BYTE */
52 SFR( TH1, 0x8D ); /* TIMER 1 - HIGH BYTE */
53 SFR( CKCON0, 0x8E ); /* CLOCK CONTROL */
54 SFR( PSCTL, 0x8F ); /* PROGRAM STORE R/W CONTROL */
55 SFR( P1, 0x90 ); /* PORT 1 */
56 SFR( TMR3CN0, 0x91 ); /* TIMER 3 CONTROL */
57 SFR( TMR3RLL, 0x92 ); /* TIMER 3 CAPTURE REGISTER - LOW BYTE */
58 SFR( TMR3RLH, 0x93 ); /* TIMER 3 CAPTURE REGISTER - HIGH BYTE */
59 SFR( TMR3L, 0x94 ); /* TIMER 3 - LOW BYTE */
60 SFR( TMR3H, 0x95 ); /* TIMER 3 - HIGH BYTE */
61 SFR( PCA0POL, 0x96 ); /* PCA Output Polarity */
62 SFR( WDTCN, 0x97 ); /* Watchdog Timer Control*/
63 SFR( SCON0, 0x98 ); /* SERIAL PORT CONTROL */
64 SFR( SBUF0, 0x99 ); /* SERIAL PORT BUFFER */
65 SFR( CMP0CN0, 0x9B ); /* COMPARATOR 0 CONTROL 0 */
66 SFR( PCA0CLR, 0x9C ); /* PCA Comparator Clear Control */
67 SFR( CMP0MD, 0x9D ); /* Comparator 0 Mode */
68 SFR( PCA0CENT, 0x9E ); /* PCA Center Alignment Enable */
69 SFR( CMP0MX, 0x9F ); /* Comparator 0 Multiplexer Selection */
70 SFR( P2, 0xA0 ); /* PORT 2 */
71 SFR( SPI0CFG, 0xA1 ); /* SPI0 CONFIGURATION */
72 SFR( SPI0CKR, 0xA2 ); /* SPI0 CLOCK RATE CONTROL */
73 SFR( SPI0DAT, 0xA3 ); /* SPI0 DATA */
74 SFR( P0MDOUT, 0xA4 ); /* PORT 0 OUTPUT MODE CONFIGURATION */
75 SFR( P1MDOUT, 0xA5 ); /* PORT 1 OUTPUT MODE CONFIGURATION */
76 SFR( P2MDOUT, 0xA6 ); /* PORT 2 OUTPUT MODE CONFIGURATION */
77 SFR( IE, 0xA8 ); /* INTERRUPT ENABLE */
78 SFR( CLKSEL, 0xA9 ); /* SYSTEM CLOCK SELECT */
79 SFR( CMP1MX, 0xAA ); /* Comparator 1 Multiplexer Selection */
80 SFR( CMP1MD, 0xAB ); /* Comparator 1 Mode */
81 SFR( SMB0TC, 0xAC ); /* SMBus 0 Timing and Pin Control */
82 SFR( DERIVID, 0xAD ); /* Derivative Identification */
83 SFR( LFO0CN, 0xB1 ); /* Low Frequency Oscillator Control */
84 SFR( ADC0CN1, 0xB2 ); /* ADC0 Control 1 */
85 SFR( ADC0AC, 0xB3 ); /* ADC0 Accumulator Configuration */
86 SFR( C2FPDAT, 0xB4 ); /* C2 Flash Programming Data */
87 SFR( DEVICEID, 0xB5 ); /* Device Identification */
88 SFR( REVID, 0xB6 ); /* Revision Identifcation */
89 SFR( FLKEY, 0xB7 ); /* Flash Lock and Key */
90 SFR( IP, 0xB8 ); /* INTERRUPT PRIORITY */
91 SFR( ADC0TK, 0xB9 ); /* ADC0 Burst Mode Track Time */
92 SFR( ADC0MX, 0xBB ); /* ADC0 Multiplexer Selection */
93 SFR( ADC0CF, 0xBC ); /* ADC 0 CONFIGURATION */
94 SFR( ADC0L, 0xBD ); /* ADC 0 DATA WORD LSB */
95 SFR( ADC0H, 0xBE ); /* ADC 0 DATA WORD MSB */
96 SFR( CMP1CN0, 0xBF ); /* Comparator 1 Control 0 */
97 SFR( SMB0CN0, 0xC0 ); /* SMBUS CONTROL */
98 SFR( SMB0CF, 0xC1 ); /* SMBUS CONFIGURATION */
99 SFR( SMB0DAT, 0xC2 ); /* SMBUS DATA */
100 SFR( ADC0GTL, 0xC3 ); /* ADC 0 GREATER-THAN LOW BYTE */
101 SFR( ADC0GTH, 0xC4 ); /* ADC 0 GREATER-THAN HIGH BYTE */
102 SFR( ADC0LTL, 0xC5 ); /* ADC 0 LESS-THAN LOW BYTE */
103 SFR( ADC0LTH, 0xC6 ); /* ADC 0 LESS-THAN HIGH BYTE */
104 SFR( HFO0CAL, 0xC7 ); /* High Frequency Oscillator 0 Calibration */
105 SFR( TMR2CN0, 0xC8 ); /* TIMER 2 CONTROL */
106 SFR( REG0CN, 0xC9 ); /* TIMER 2 CONTROL */
107 SFR( TMR2RLL, 0xCA ); /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
108 SFR( TMR2RLH, 0xCB ); /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
109 SFR( TMR2L, 0xCC ); /* TIMER 2 - LOW BYTE */
110 SFR( TMR2H, 0xCD ); /* TIMER 2 - HIGH BYTE */
111 SFR( CRC0CN0, 0xCE ); /* CRC0 Control 0 */
112 SFR( CRC0FLIP, 0xCF ); /* CRC0 Bit Flip */
113 SFR( PSW, 0xD0 ); /* PROGRAM STATUS WORD */
114 SFR( REF0CN, 0xD1 ); /* VOLTAGE REFERENCE 0 CONTROL */
115 SFR( CRC0AUTO, 0xD2 ); /* CRC0 Automatic Control */
116 SFR( CRC0CNT, 0xD3 ); /* CRC0 Automatic Flash Sector Count */
117 SFR( P0SKIP, 0xD4 ); /* PORT 0 SKIP */
118 SFR( P1SKIP, 0xD5 ); /* PORT 1 SKIP */
119 SFR( SMB0ADM, 0xD6 ); /* SMBus 0 Slave Address Mask */
120 SFR( SMB0ADR, 0xD7 ); /* SMBus 0 Slave Address */
121 SFR( PCA0CN0, 0xD8 ); /* PCA CONTROL */
122 SFR( PCA0MD, 0xD9 ); /* PCA MODE */
123 SFR( PCA0CPM0, 0xDA ); /* PCA MODULE 0 MODE REGISTER */
124 SFR( PCA0CPM1, 0xDB ); /* PCA MODULE 1 MODE REGISTER */
125 SFR( PCA0CPM2, 0xDC ); /* PCA MODULE 2 MODE REGISTER */
126 SFR( CRC0IN, 0xDD ); /* CRC0 Data Input */
127 SFR( CRC0DAT, 0xDE ); /* CRC0 Data Output */
128 SFR( ADC0PWR, 0xDF ); /* ADC0 Power Control */
129 SFR( ACC, 0xE0 ); /* ACCUMULATOR */
130 SFR( XBR0, 0xE1 ); /* PORT MUX CONFIGURATION REGISTER 0 */
131 SFR( XBR1, 0xE2 ); /* PORT MUX CONFIGURATION REGISTER 1 */
132 SFR( XBR2, 0xE3 ); /* PORT MUX CONFIGURATION REGISTER 2 */
133 SFR( IT01CF, 0xE4 ); /* INT0/INT1 CONFIGURATION REGISTER */
134 SFR( EIE1, 0xE6 ); /* EXTERNAL INTERRUPT ENABLE 1 */
135 SFR( ADC0CN0, 0xE8 ); /* ADC 0 CONTROL */
136 SFR( PCA0CPL1, 0xE9 ); /* PCA CAPTURE 1 LOW */
137 SFR( PCA0CPH1, 0xEA ); /* PCA CAPTURE 1 HIGH */
138 SFR( PCA0CPL2, 0xEB ); /* PCA CAPTURE 2 LOW */
139 SFR( PCA0CPH2, 0xEC ); /* PCA CAPTURE 2 HIGH */
140 SFR( P1MAT, 0xED ); /* Port 1 Match */
141 SFR( P1MASK, 0xEE ); /* Port 1 Mask */
142 SFR( RSTSRC, 0xEF ); /* RESET SOURCE */
143 SFR( B, 0xF0 ); /* B REGISTER */
144 SFR( P0MDIN, 0xF1 ); /* PORT 0 INPUT MODE CONFIGURATION */
145 SFR( P1MDIN, 0xF2 ); /* PORT 1 INPUT MODE CONFIGURATION */
146 SFR( EIP1, 0xF3 ); /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
147 SFR( PRTDRV, 0xF6 ); /* Port Drive Strength */
148 SFR( PCA0PWM, 0xF7 ); /* PCA PWM Configuration */
149 SFR( SPI0CN0, 0xF8 ); /* SPI0 CONTROL */
150 SFR( PCA0L, 0xF9 ); /* PCA COUNTER LOW */
151 SFR( PCA0H, 0xFA ); /* PCA COUNTER HIGH */
152 SFR( PCA0CPL0, 0xFB ); /* PCA CAPTURE 0 LOW */
153 SFR( PCA0CPH0, 0xFC ); /* PCA CAPTURE 0 HIGH */
154 SFR( P0MAT, 0xFD ); /* Port 0 Match */
155 SFR( P0MASK, 0xFE ); /* Port 0 Mask */
156 SFR( VDM0CN, 0xFF ); /* Supply Monitor Control */
157
158
159 /* WORD/DWORD Registers */
160
161 SFR16E( TMR0, 0x8C8A ); /* TIMER 0 COUNTER */
162 SFR16E( TMR1, 0x8D8B ); /* TIMER 1 COUNTER */
163 SFR16( TMR2, 0xCC ); /* TIMER 2 COUNTER */
164 SFR16( TMR2RL, 0xCA ); /* TIMER 2 CAPTURE REGISTER WORD */
165 SFR16( TMR3, 0x94 ); /* TIMER 3 COUNTER */
166 SFR16( TMR3RL, 0x92 ); /* TIMER 3 CAPTURE REGISTER WORD */
167 SFR16( ADC0, 0xBD ); /* ADC 0 DATA WORD */
168 SFR16( ADC0GT, 0xC3 ); /* ADC 0 GREATER-THAN REGISTER WORD */
169 SFR16( ADC0LT, 0xC5 ); /* ADC 0 LESS-THAN REGISTER WORD */
170 SFR16( PCA0, 0xF9 ); /* PCA COUNTER */
171 SFR16( PCA0CP0, 0xFB ); /* PCA CAPTURE 0 WORD */
172 SFR16( PCA0CP1, 0xE9 ); /* PCA CAPTURE 1 WORD */
173 SFR16( PCA0CP2, 0xEB ); /* PCA CAPTURE 2 WORD */
174
175 /* BIT Registers */
176
177 /* P0 0x80 */
178 SBIT( P0_0, 0x80, 0 ); /* Port 0 bit 0 */
179 SBIT( P0_1, 0x80, 1 ); /* Port 0 bit 1 */
180 SBIT( P0_2, 0x80, 2 ); /* Port 0 bit 2 */
181 SBIT( P0_3, 0x80, 3 ); /* Port 0 bit 3 */
182 SBIT( P0_4, 0x80, 4 ); /* Port 0 bit 4 */
183 SBIT( P0_5, 0x80, 5 ); /* Port 0 bit 5 */
184 SBIT( P0_6, 0x80, 6 ); /* Port 0 bit 6 */
185 SBIT( P0_7, 0x80, 7 ); /* Port 0 bit 7 */
186
187 /* TCON 0x88 */
188 SBIT( IT0, 0x88, 0 ); /* TCON.0 - EXT. INTERRUPT 0 TYPE */
189 SBIT( IE0, 0x88, 1 ); /* TCON.1 - EXT. INTERRUPT 0 EDGE FLAG */
190 SBIT( IT1, 0x88, 2 ); /* TCON.2 - EXT. INTERRUPT 1 TYPE */
191 SBIT( IE1, 0x88, 3 ); /* TCON.3 - EXT. INTERRUPT 1 EDGE FLAG */
192 SBIT( TR0, 0x88, 4 ); /* TCON.4 - TIMER 0 ON/OFF CONTROL */
193 SBIT( TF0, 0x88, 5 ); /* TCON.5 - TIMER 0 OVERFLOW FLAG */
194 SBIT( TR1, 0x88, 6 ); /* TCON.6 - TIMER 1 ON/OFF CONTROL */
195 SBIT( TF1, 0x88, 7 ); /* TCON.7 - TIMER 1 OVERFLOW FLAG */
196
197 /* P1 0x90 */
198 SBIT( P1_0, 0x90, 0 ); /* Port 1 bit 0 */
199 SBIT( P1_1, 0x90, 1 ); /* Port 1 bit 1 */
200 SBIT( P1_2, 0x90, 2 ); /* Port 1 bit 2 */
201 SBIT( P1_3, 0x90, 3 ); /* Port 1 bit 3 */
202 SBIT( P1_4, 0x90, 4 ); /* Port 1 bit 4 */
203 SBIT( P1_5, 0x90, 5 ); /* Port 1 bit 5 */
204 SBIT( P1_6, 0x90, 6 ); /* Port 1 bit 6 */
205 SBIT( P1_7, 0x90, 7 ); /* Port 1 bit 7 */
206
207 /* SCON 0x98 */
208 SBIT( RI, 0x98, 0 ); /* SCON.0 - RECEIVE INTERRUPT FLAG */
209 SBIT( RI0, 0x98, 0 ); /* SCON.0 - RECEIVE INTERRUPT FLAG */
210 SBIT( TI, 0x98, 1 ); /* SCON.1 - TRANSMIT INTERRUPT FLAG */
211 SBIT( TI0, 0x98, 1 ); /* SCON.1 - TRANSMIT INTERRUPT FLAG */
212 SBIT( RB8, 0x98, 2 ); /* SCON.2 - RECEIVE BIT 8 */
213 SBIT( RB80, 0x98, 2 ); /* SCON.2 - RECEIVE BIT 8 */
214 SBIT( TB8, 0x98, 3 ); /* SCON.3 - TRANSMIT BIT 8 */
215 SBIT( TB80, 0x98, 3 ); /* SCON.3 - TRANSMIT BIT 8 */
216 SBIT( REN, 0x98, 4 ); /* SCON.4 - RECEIVE ENABLE */
217 SBIT( REN0, 0x98, 4 ); /* SCON.4 - RECEIVE ENABLE */
218 SBIT( SM2, 0x98, 5 ); /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
219 SBIT( MCE0, 0x98, 5 ); /* SCON.5 - MULTIPROCESSOR COMMUNICATION ENABLE */
220 SBIT( SM0, 0x98, 7 ); /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
221 SBIT( S0MODE, 0x98, 7 ); /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
222 SBIT( SMODE, 0x98, 7 ); /* SCON.7 - SERIAL MODE CONTROL BIT 0 */
223
224 /* P2 0xA0 */
225 SBIT( P2_0, 0xA0, 0 ); /* Port 2 bit 0 */
226 SBIT( P2_1, 0xA0, 1 ); /* Port 2 bit 1 */
227 SBIT( P2_2, 0xA0, 2 ); /* Port 2 bit 2 */
228 SBIT( P2_3, 0xA0, 3 ); /* Port 2 bit 3 */
229 SBIT( P2_4, 0xA0, 4 ); /* Port 2 bit 4 */
230 SBIT( P2_5, 0xA0, 5 ); /* Port 2 bit 5 */
231 SBIT( P2_6, 0xA0, 6 ); /* Port 2 bit 6 */
232 SBIT( P2_7, 0xA0, 7 ); /* Port 2 bit 7 */
233
234 /* IE 0xA8 */
235 SBIT( EX0, 0xA8, 0 ); /* IE.0 - EXTERNAL INTERRUPT 0 ENABLE */
236 SBIT( ET0, 0xA8, 1 ); /* IE.1 - TIMER 0 INTERRUPT ENABLE */
237 SBIT( EX1, 0xA8, 2 ); /* IE.2 - EXTERNAL INTERRUPT 1 ENABLE */
238 SBIT( ET1, 0xA8, 3 ); /* IE.3 - TIMER 1 INTERRUPT ENABLE */
239 SBIT( ES, 0xA8, 4 ); /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
240 SBIT( ES0, 0xA8, 4 ); /* IE.4 - SERIAL PORT INTERRUPT ENABLE */
241 SBIT( ET2, 0xA8, 5 ); /* IE.5 - TIMER 2 INTERRUPT ENABLE */
242 SBIT( ESPI0, 0xA8, 6 ); /* IE.6 - SPI0 INTERRUPT ENABLE */
243 SBIT( EA, 0xA8, 7 ); /* IE.7 - GLOBAL INTERRUPT ENABLE */
244
245 /* IP 0xB8 */
246 SBIT( PX0, 0xB8, 0 ); /* IP.0 - EXTERNAL INTERRUPT 0 PRIORITY */
247 SBIT( PT0, 0xB8, 1 ); /* IP.1 - TIMER 0 PRIORITY */
248 SBIT( PX1, 0xB8, 2 ); /* IP.2 - EXTERNAL INTERRUPT 1 PRIORITY */
249 SBIT( PT1, 0xB8, 3 ); /* IP.3 - TIMER 1 PRIORITY */
250 SBIT( PS, 0xB8, 4 ); /* IP.4 - SERIAL PORT PRIORITY */
251 SBIT( PS0, 0xB8, 4 ); /* IP.4 - SERIAL PORT PRIORITY */
252 SBIT( PT2, 0xB8, 5 ); /* IP.5 - TIMER 2 PRIORITY */
253 SBIT( PSPI0, 0xB8, 6 ); /* IP.6 - SPI0 PRIORITY */
254
255 /* SMB0CN 0xC0 */
256 SBIT( SI, 0xC0, 0 ); /* SMB0CN.0 - SMBUS 0 INTERRUPT PENDING FLAG */
257 SBIT( ACK, 0xC0, 1 ); /* SMB0CN.1 - SMBUS 0 ACKNOWLEDGE FLAG */
258 SBIT( ARBLOST, 0xC0, 2 ); /* SMB0CN.2 - SMBUS 0 ARBITRATION LOST INDICATOR */
259 SBIT( ACKRQ, 0xC0, 3 ); /* SMB0CN.3 - SMBUS 0 ACKNOWLEDGE REQUEST */
260 SBIT( STO, 0xC0, 4 ); /* SMB0CN.4 - SMBUS 0 STOP FLAG */
261 SBIT( STA, 0xC0, 5 ); /* SMB0CN.5 - SMBUS 0 START FLAG */
262 SBIT( TXMODE, 0xC0, 6 ); /* SMB0CN.6 - SMBUS 0 TRANSMIT MODE INDICATOR */
263 SBIT( MASTER, 0xC0, 7 ); /* SMB0CN.7 - SMBUS 0 MASTER/SLAVE INDICATOR */
264
265 /* TMR2CN 0xC8 */
266 SBIT( T2XCLK, 0xC8, 0 ); /* TMR2CN.0 - TIMER 2 EXTERNAL CLOCK SELECT */
267 SBIT( TR2, 0xC8, 2 ); /* TMR2CN.2 - TIMER 2 ON/OFF CONTROL */
268 SBIT( T2SPLIT, 0xC8, 3 ); /* TMR2CN.3 - TIMER 2 SPLIT MODE ENABLE */
269 SBIT( TF2CEN, 0xC8, 4 ); /* TMR2CN.5 - TIMER 2 CAPTURE ENABLE */
270 SBIT( TF2LEN, 0xC8, 5 ); /* TMR2CN.5 - TIMER 2 LOW BYTE INTERRUPT ENABLE */
271 SBIT( TF2L, 0xC8, 6 ); /* TMR2CN.6 - TIMER 2 LOW BYTE OVERFLOW FLAG */
272 SBIT( TF2, 0xC8, 7 ); /* TMR2CN.7 - TIMER 2 OVERFLOW FLAG */
273 SBIT( TF2H, 0xC8, 7 ); /* TMR2CN.7 - TIMER 2 HIGH BYTE OVERFLOW FLAG */
274
275 /* PSW 0xD0 */
276 SBIT( PARITY, 0xD0, 0 ); /* PSW.0 - ACCUMULATOR PARITY FLAG */
277 SBIT( F1, 0xD0, 1 ); /* PSW.1 - FLAG 1 */
278 SBIT( OV, 0xD0, 2 ); /* PSW.2 - OVERFLOW FLAG */
279 SBIT( RS0, 0xD0, 3 ); /* PSW.3 - REGISTER BANK SELECT 0 */
280 SBIT( RS1, 0xD0, 4 ); /* PSW.4 - REGISTER BANK SELECT 1 */
281 SBIT( F0, 0xD0, 5 ); /* PSW.5 - FLAG 0 */
282 SBIT( AC, 0xD0, 6 ); /* PSW.6 - AUXILIARY CARRY FLAG */
283 SBIT( CY, 0xD0, 7 ); /* PSW.7 - CARRY FLAG */
284
285 /* PCA0CN 0xD8 */
286 SBIT( CCF0, 0xD8, 0 ); /* PCA0CN.0 - PCA MODULE 0 CAPTURE/COMPARE FLAG */
287 SBIT( CCF1, 0xD8, 1 ); /* PCA0CN.1 - PCA MODULE 1 CAPTURE/COMPARE FLAG */
288 SBIT( CCF2, 0xD8, 2 ); /* PCA0CN.2 - PCA MODULE 2 CAPTURE/COMPARE FLAG */
289 SBIT( CR, 0xD8, 6 ); /* PCA0CN.6 - PCA COUNTER/TIMER RUN CONTROL */
290 SBIT( CF, 0xD8, 7 ); /* PCA0CN.7 - PCA COUNTER/TIMER OVERFLOW FLAG */
291
292 /* ADC0CN 0xE8 */
293 SBIT( ADCM0, 0xE8, 0 ); /* ADC0CN.0 - ADC 0 START OF CONV. MODE BIT 0 */
294 SBIT( ADCM1, 0xE8, 1 ); /* ADC0CN.1 - ADC 0 START OF CONV. MODE BIT 1 */
295 SBIT( ADCM2, 0xE8, 2 ); /* ADC0CN.2 - ADC 0 START OF CONV. MODE BIT 2 */
296 SBIT( ADWINT, 0xE8, 3 ); /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
297 SBIT( AD0WINT, 0xE8, 3 ); /* ADC0CN.3 - ADC 0 WINDOW COMPARE INT. FLAG */
298 SBIT( ADBUSY, 0xE8, 4 ); /* ADC0CN.4 - ADC 0 BUSY FLAG */
299 SBIT( AD0BUSY, 0xE8, 4 ); /* ADC0CN.4 - ADC 0 BUSY FLAG */
300 SBIT( ADINT, 0xE8, 5 ); /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
301 SBIT( AD0INT, 0xE8, 5 ); /* ADC0CN.5 - ADC 0 CONV. COMPLETE INT. FLAG */
302 SBIT( ADBMEN, 0xE8, 6 ); /* ADC0CN.6 - ADC 0 BURST MODE ENABLE */
303 SBIT( ADEN, 0xE8, 7 ); /* ADC0CN.7 - ADC 0 ENABLE */
304 SBIT( AD0EN, 0xE8, 7 ); /* ADC0CN.7 - ADC 0 ENABLE */
305
306 /* SPI0CN 0xF8 */
307 SBIT( SPIEN, 0xF8, 0 ); /* SPI0CN.0 - SPI0 ENABLE */
308 SBIT( TXBMT, 0xF8, 1 ); /* SPI0CN.1 - TRANSMIT BUFFER EMPTY */
309 SBIT( NSSMD0, 0xF8, 2 ); /* SPI0CN.2 - SLAVE SELECT MODE BIT 0 */
310 SBIT( NSSMD1, 0xF8, 3 ); /* SPI0CN.3 - SLAVE SELECT MODE BIT 1 */
311 SBIT( RXOVRN, 0xF8, 4 ); /* SPI0CN.4 - RECEIVE OVERRUN FLAG */
312 SBIT( MODF, 0xF8, 5 ); /* SPI0CN.5 - MODE FAULT FLAG */
313 SBIT( WCOL, 0xF8, 6 ); /* SPI0CN.6 - WRITE COLLISION FLAG */
314 SBIT( SPIF, 0xF8, 7 ); /* SPI0CN.7 - SPI0 INTERRUPT FLAG */
315
316
317 /* Predefined SFR Bit Masks */
318
319 #define PCON_IDLE 0x01 /* PCON */
320 #define PCON_STOP 0x02 /* PCON */
321 #define T1M 0x08 /* CKCON */
322 #define PSWE 0x01 /* PSCTL */
323 #define PSEE 0x02 /* PSCTL */
324 #define ECP0 0x20 /* EIE1 */
325 #define ECP1 0x40 /* EIE1 */
326 #define PORSF 0x02 /* RSTSRC */
327 #define SWRSF 0x10 /* RSTSRC */
328 #define ECCF 0x01 /* PCA0CPMn */
329 #define PWM 0x02 /* PCA0CPMn */
330 #define TOG 0x04 /* PCA0CPMn */
331 #define MAT 0x08 /* PCA0CPMn */
332 #define CAPN 0x10 /* PCA0CPMn */
333 #define CAPP 0x20 /* PCA0CPMn */
334 #define ECOM 0x40 /* PCA0CPMn */
335 #define PWM16 0x80 /* PCA0CPMn */
336 #define CP0E 0x10 /* XBR0 */
337 #define CP0OEN 0x10 /* XBR0 */
338 #define CP0AE 0x20 /* XBR0 */
339 #define CP0AOEN 0x20 /* XBR0 */
340 #define CP1E 0x40 /* XBR0 */
341 #define CP1AE 0x80 /* XBR0 */
342
343 /* Interrupts */
344
345 #define EXT0_VECTOR 0 /* External Interrupt 0 */
346 #define TIMER0_VECTOR 1 /* Timer0 Overflow */
347 #define EXT1_VECTOR 2 /* External Interrupt 1 */
348 #define TIMER1_VECTOR 3 /* Timer1 Overflow */
349 #define UART0_VECTOR 4 /* Serial Port 0 */
350 #define TIMER2_VECTOR 5 /* Timer2 Overflow */
351 #define SPI0_VECTOR 6 /* Serial Peripheral Interface 0 */
352 #define SMBUS0_VECTOR 7 /* SMBus0 Interface */
353 #define PMAT_VECTOR 8 /* Port Match */
354 #define ADC0_WINDOW_VECTOR 9 /* ADC0 Window Comparison */
355 #define ADC0_EOC_VECTOR 10 /* ADC0 End Of Conversion */
356 #define PCA0_VECTOR 11 /* PCA0 Peripheral */
357 #define CMP0_VECTOR 12 /* Comparator0 */
358 #define CMP1_VECTOR 13 /* Comparator1 */
359 #define TIMER3_VECTOR 14 /* Timer3 Overflow */
360
361 /*------------------------------------------------------------------------------ */
362 /* ADC0CN0 Enums (ADC0 Control 0 @ 0xE8) */
363 /*------------------------------------------------------------------------------ */
364 #define ADCM__FMASK 0x07 /* Start of Conversion Mode Select */
365 #define ADCM__SHIFT 0x00 /* Start of Conversion Mode Select */
366 #define ADCM__ADBUSY 0x00 /* ADC0 conversion initiated on write of 1 to ADBUSY. */
367 #define ADCM__TIMER0 0x01 /* ADC0 conversion initiated on overflow of Timer 0. */
368 #define ADCM__TIMER2 0x02 /* ADC0 conversion initiated on overflow of Timer 2. */
369 #define ADCM__TIMER3 0x03 /* ADC0 conversion initiated on overflow of Timer 3. */
370 #define ADCM__CNVSTR 0x04 /* ADC0 conversion initiated on rising edge of CNVSTR. */
371
372 #define ADWINT__BMASK 0x08 /* Window Compare Interrupt Flag */
373 #define ADWINT__SHIFT 0x03 /* Window Compare Interrupt Flag */
374 #define ADWINT__NOT_SET 0x00 /* An ADC window compare event did not occur. */
375 #define ADWINT__SET 0x08 /* An ADC window compare event occurred. */
376
377 #define ADBUSY__BMASK 0x10 /* ADC Busy */
378 #define ADBUSY__SHIFT 0x04 /* ADC Busy */
379 #define ADBUSY__NOT_SET 0x00 /* An ADC0 conversion is not currently in progress. */
380 #define ADBUSY__SET 0x10 /* ADC0 conversion is in progress or start an ADC0 conversion. */
381
382 #define ADINT__BMASK 0x20 /* Conversion Complete Interrupt Flag */
383 #define ADINT__SHIFT 0x05 /* Conversion Complete Interrupt Flag */
384 #define ADINT__NOT_SET 0x00 /* ADC0 has not completed a conversion since the last time ADINT was cleared. */
385 #define ADINT__SET 0x20 /* ADC0 completed a data conversion. */
386
387 #define ADBMEN__BMASK 0x40 /* Burst Mode Enable */
388 #define ADBMEN__SHIFT 0x06 /* Burst Mode Enable */
389 #define ADBMEN__BURST_DISABLED 0x00 /* Disable ADC0 burst mode. */
390 #define ADBMEN__BURST_ENABLED 0x40 /* Enable ADC0 burst mode. */
391
392 #define ADEN__BMASK 0x80 /* ADC Enable */
393 #define ADEN__SHIFT 0x07 /* ADC Enable */
394 #define ADEN__DISABLED 0x00 /* Disable ADC0 (low-power shutdown). */
395 #define ADEN__ENABLED 0x80 /* Enable ADC0 (active and ready for data conversions). */
396
397 /*------------------------------------------------------------------------------ */
398 /* ADC0AC Enums (ADC0 Accumulator Configuration @ 0xB3) */
399 /*------------------------------------------------------------------------------ */
400 #define AD0RPT__FMASK 0x07 /* Repeat Count */
401 #define AD0RPT__SHIFT 0x00 /* Repeat Count */
402 #define AD0RPT__ACC_1 0x00 /* Perform and Accumulate 1 conversion (not used in 12-bit mode). */
403 #define AD0RPT__ACC_4 0x01 /* Perform and Accumulate 4 conversions (1 conversion in 12-bit mode). */
404 #define AD0RPT__ACC_8 0x02 /* Perform and Accumulate 8 conversions (2 conversions in 12-bit mode). */
405 #define AD0RPT__ACC_16 0x03 /* Perform and Accumulate 16 conversions (4 conversions in 12-bit mode). */
406 #define AD0RPT__ACC_32 0x04 /* Perform and Accumulate 32 conversions (8 conversions in 12-bit mode). */
407 #define AD0RPT__ACC_64 0x05 /* Perform and Accumulate 64 conversions (16 conversions in 12-bit mode). */
408
409 #define AD0SJST__FMASK 0x38 /* Accumulator Shift and Justify */
410 #define AD0SJST__SHIFT 0x03 /* Accumulator Shift and Justify */
411 #define AD0SJST__RIGHT_NO_SHIFT 0x00 /* Right justified. No shifting applied. */
412 #define AD0SJST__RIGHT_SHIFT_1 0x08 /* Right justified. Shifted right by 1 bit. */
413 #define AD0SJST__RIGHT_SHIFT_2 0x10 /* Right justified. Shifted right by 2 bits. */
414 #define AD0SJST__RIGHT_SHIFT_3 0x18 /* Right justified. Shifted right by 3 bits. */
415 #define AD0SJST__LEFT_NO_SHIFT 0x20 /* Left justified. No shifting applied. */
416
417 #define AD0AE__BMASK 0x40 /* Accumulate Enable */
418 #define AD0AE__SHIFT 0x06 /* Accumulate Enable */
419 #define AD0AE__ACC_DISABLED 0x00 /* ADC0H:ADC0L contain the result of the latest conversion when Burst Mode is disabled. */
420 #define AD0AE__ACC_ENABLED 0x40 /* ADC0H:ADC0L contain the accumulated conversion results when Burst Mode is disabled. Firmware must write 0x0000 to ADC0H:ADC0L to clear the accumulated result. */
421
422 #define AD12BE__BMASK 0x80 /* 12-Bit Mode Enable */
423 #define AD12BE__SHIFT 0x07 /* 12-Bit Mode Enable */
424 #define AD12BE__12_BIT_DISABLED 0x00 /* Disable 12-bit mode. */
425 #define AD12BE__12_BIT_ENABLED 0x80 /* Enable 12-bit mode. */
426
427 /*------------------------------------------------------------------------------ */
428 /* ADC0CF Enums (ADC0 Configuration @ 0xBC) */
429 /*------------------------------------------------------------------------------ */
430 #define ADGN__BMASK 0x01 /* Gain Control */
431 #define ADGN__SHIFT 0x00 /* Gain Control */
432 #define ADGN__GAIN_0P5 0x00 /* The on-chip PGA gain is 0.5. */
433 #define ADGN__GAIN_1 0x01 /* The on-chip PGA gain is 1. */
434
435 #define ADTM__BMASK 0x02 /* Track Mode */
436 #define ADTM__SHIFT 0x01 /* Track Mode */
437 #define ADTM__TRACK_NORMAL 0x00 /* Normal Track Mode. When ADC0 is enabled, conversion begins immediately following the start-of-conversion signal. */
438 #define ADTM__TRACK_DELAYED 0x02 /* Delayed Track Mode. When ADC0 is enabled, conversion begins 4 SAR clock cycles following the start-of-conversion signal. The ADC is allowed to track during this time. */
439
440 #define AD8BE__BMASK 0x04 /* 8-Bit Mode Enable */
441 #define AD8BE__SHIFT 0x02 /* 8-Bit Mode Enable */
442 #define AD8BE__NORMAL 0x00 /* ADC0 operates in 10-bit or 12-bit mode (normal operation). */
443 #define AD8BE__8_BIT 0x04 /* ADC0 operates in 8-bit mode. */
444
445 #define ADSC__FMASK 0xF8 /* SAR Clock Divider */
446 #define ADSC__SHIFT 0x03 /* SAR Clock Divider */
447
448 /*------------------------------------------------------------------------------ */
449 /* P0MDIN Enums (Port 0 Input Mode @ 0xF1) */
450 /*------------------------------------------------------------------------------ */
451 #define B0__BMASK 0x01 /* Port 0 Bit 0 Input Mode */
452 #define B0__SHIFT 0x00 /* Port 0 Bit 0 Input Mode */
453 #define B0__ANALOG 0x00 /* P0.0 pin is configured for analog mode. */
454 #define B0__DIGITAL 0x01 /* P0.0 pin is configured for digital mode. */
455
456 #define B1__BMASK 0x02 /* Port 0 Bit 1 Input Mode */
457 #define B1__SHIFT 0x01 /* Port 0 Bit 1 Input Mode */
458 #define B1__ANALOG 0x00 /* P0.1 pin is configured for analog mode. */
459 #define B1__DIGITAL 0x02 /* P0.1 pin is configured for digital mode. */
460
461 #define B2__BMASK 0x04 /* Port 0 Bit 2 Input Mode */
462 #define B2__SHIFT 0x02 /* Port 0 Bit 2 Input Mode */
463 #define B2__ANALOG 0x00 /* P0.2 pin is configured for analog mode. */
464 #define B2__DIGITAL 0x04 /* P0.2 pin is configured for digital mode. */
465
466 #define B3__BMASK 0x08 /* Port 0 Bit 3 Input Mode */
467 #define B3__SHIFT 0x03 /* Port 0 Bit 3 Input Mode */
468 #define B3__ANALOG 0x00 /* P0.3 pin is configured for analog mode. */
469 #define B3__DIGITAL 0x08 /* P0.3 pin is configured for digital mode. */
470
471 #define B4__BMASK 0x10 /* Port 0 Bit 4 Input Mode */
472 #define B4__SHIFT 0x04 /* Port 0 Bit 4 Input Mode */
473 #define B4__ANALOG 0x00 /* P0.4 pin is configured for analog mode. */
474 #define B4__DIGITAL 0x10 /* P0.4 pin is configured for digital mode. */
475
476 #define B5__BMASK 0x20 /* Port 0 Bit 5 Input Mode */
477 #define B5__SHIFT 0x05 /* Port 0 Bit 5 Input Mode */
478 #define B5__ANALOG 0x00 /* P0.5 pin is configured for analog mode. */
479 #define B5__DIGITAL 0x20 /* P0.5 pin is configured for digital mode. */
480
481 #define B6__BMASK 0x40 /* Port 0 Bit 6 Input Mode */
482 #define B6__SHIFT 0x06 /* Port 0 Bit 6 Input Mode */
483 #define B6__ANALOG 0x00 /* P0.6 pin is configured for analog mode. */
484 #define B6__DIGITAL 0x40 /* P0.6 pin is configured for digital mode. */
485
486 #define B7__BMASK 0x80 /* Port 0 Bit 7 Input Mode */
487 #define B7__SHIFT 0x07 /* Port 0 Bit 7 Input Mode */
488 #define B7__ANALOG 0x00 /* P0.7 pin is configured for analog mode. */
489 #define B7__DIGITAL 0x80 /* P0.7 pin is configured for digital mode. */
490
491 /*------------------------------------------------------------------------------ */
492 /* P0MDOUT Enums (Port 0 Output Mode @ 0xA4) */
493 /*------------------------------------------------------------------------------ */
494 #define B0__BMASK 0x01 /* Port 0 Bit 0 Output Mode */
495 #define B0__SHIFT 0x00 /* Port 0 Bit 0 Output Mode */
496 #define B0__OPEN_DRAIN 0x00 /* P0.0 output is open-drain. */
497 #define B0__PUSH_PULL 0x01 /* P0.0 output is push-pull. */
498
499 #define B1__BMASK 0x02 /* Port 0 Bit 1 Output Mode */
500 #define B1__SHIFT 0x01 /* Port 0 Bit 1 Output Mode */
501 #define B1__OPEN_DRAIN 0x00 /* P0.1 output is open-drain. */
502 #define B1__PUSH_PULL 0x02 /* P0.1 output is push-pull. */
503
504 #define B2__BMASK 0x04 /* Port 0 Bit 2 Output Mode */
505 #define B2__SHIFT 0x02 /* Port 0 Bit 2 Output Mode */
506 #define B2__OPEN_DRAIN 0x00 /* P0.2 output is open-drain. */
507 #define B2__PUSH_PULL 0x04 /* P0.2 output is push-pull. */
508
509 #define B3__BMASK 0x08 /* Port 0 Bit 3 Output Mode */
510 #define B3__SHIFT 0x03 /* Port 0 Bit 3 Output Mode */
511 #define B3__OPEN_DRAIN 0x00 /* P0.3 output is open-drain. */
512 #define B3__PUSH_PULL 0x08 /* P0.3 output is push-pull. */
513
514 #define B4__BMASK 0x10 /* Port 0 Bit 4 Output Mode */
515 #define B4__SHIFT 0x04 /* Port 0 Bit 4 Output Mode */
516 #define B4__OPEN_DRAIN 0x00 /* P0.4 output is open-drain. */
517 #define B4__PUSH_PULL 0x10 /* P0.4 output is push-pull. */
518
519 #define B5__BMASK 0x20 /* Port 0 Bit 5 Output Mode */
520 #define B5__SHIFT 0x05 /* Port 0 Bit 5 Output Mode */
521 #define B5__OPEN_DRAIN 0x00 /* P0.5 output is open-drain. */
522 #define B5__PUSH_PULL 0x20 /* P0.5 output is push-pull. */
523
524 #define B6__BMASK 0x40 /* Port 0 Bit 6 Output Mode */
525 #define B6__SHIFT 0x06 /* Port 0 Bit 6 Output Mode */
526 #define B6__OPEN_DRAIN 0x00 /* P0.6 output is open-drain. */
527 #define B6__PUSH_PULL 0x40 /* P0.6 output is push-pull. */
528
529 #define B7__BMASK 0x80 /* Port 0 Bit 7 Output Mode */
530 #define B7__SHIFT 0x07 /* Port 0 Bit 7 Output Mode */
531 #define B7__OPEN_DRAIN 0x00 /* P0.7 output is open-drain. */
532 #define B7__PUSH_PULL 0x80 /* P0.7 output is push-pull. */
533
534 /*------------------------------------------------------------------------------ */
535 /* P0SKIP Enums (Port 0 Skip @ 0xD4) */
536 /*------------------------------------------------------------------------------ */
537 #define B0__BMASK 0x01 /* Port 0 Bit 0 Skip */
538 #define B0__SHIFT 0x00 /* Port 0 Bit 0 Skip */
539 #define B0__NOT_SKIPPED 0x00 /* P0.0 pin is not skipped by the crossbar. */
540 #define B0__SKIPPED 0x01 /* P0.0 pin is skipped by the crossbar. */
541
542 #define B1__BMASK 0x02 /* Port 0 Bit 1 Skip */
543 #define B1__SHIFT 0x01 /* Port 0 Bit 1 Skip */
544 #define B1__NOT_SKIPPED 0x00 /* P0.1 pin is not skipped by the crossbar. */
545 #define B1__SKIPPED 0x02 /* P0.1 pin is skipped by the crossbar. */
546
547 #define B2__BMASK 0x04 /* Port 0 Bit 2 Skip */
548 #define B2__SHIFT 0x02 /* Port 0 Bit 2 Skip */
549 #define B2__NOT_SKIPPED 0x00 /* P0.2 pin is not skipped by the crossbar. */
550 #define B2__SKIPPED 0x04 /* P0.2 pin is skipped by the crossbar. */
551
552 #define B3__BMASK 0x08 /* Port 0 Bit 3 Skip */
553 #define B3__SHIFT 0x03 /* Port 0 Bit 3 Skip */
554 #define B3__NOT_SKIPPED 0x00 /* P0.3 pin is not skipped by the crossbar. */
555 #define B3__SKIPPED 0x08 /* P0.3 pin is skipped by the crossbar. */
556
557 #define B4__BMASK 0x10 /* Port 0 Bit 4 Skip */
558 #define B4__SHIFT 0x04 /* Port 0 Bit 4 Skip */
559 #define B4__NOT_SKIPPED 0x00 /* P0.4 pin is not skipped by the crossbar. */
560 #define B4__SKIPPED 0x10 /* P0.4 pin is skipped by the crossbar. */
561
562 #define B5__BMASK 0x20 /* Port 0 Bit 5 Skip */
563 #define B5__SHIFT 0x05 /* Port 0 Bit 5 Skip */
564 #define B5__NOT_SKIPPED 0x00 /* P0.5 pin is not skipped by the crossbar. */
565 #define B5__SKIPPED 0x20 /* P0.5 pin is skipped by the crossbar. */
566
567 #define B6__BMASK 0x40 /* Port 0 Bit 6 Skip */
568 #define B6__SHIFT 0x06 /* Port 0 Bit 6 Skip */
569 #define B6__NOT_SKIPPED 0x00 /* P0.6 pin is not skipped by the crossbar. */
570 #define B6__SKIPPED 0x40 /* P0.6 pin is skipped by the crossbar. */
571
572 #define B7__BMASK 0x80 /* Port 0 Bit 7 Skip */
573 #define B7__SHIFT 0x07 /* Port 0 Bit 7 Skip */
574 #define B7__NOT_SKIPPED 0x00 /* P0.7 pin is not skipped by the crossbar. */
575 #define B7__SKIPPED 0x80 /* P0.7 pin is skipped by the crossbar. */
576
577 /*------------------------------------------------------------------------------ */
578 /* P0 Enums (Port 0 Pin Latch @ 0x80) */
579 /*------------------------------------------------------------------------------ */
580 #define B0__BMASK 0x01 /* Port 0 Bit 0 Latch */
581 #define B0__SHIFT 0x00 /* Port 0 Bit 0 Latch */
582 #define B0__LOW 0x00 /* P0.0 is low. Set P0.0 to drive low. */
583 #define B0__HIGH 0x01 /* P0.0 is high. Set P0.0 to drive or float high. */
584
585 #define B1__BMASK 0x02 /* Port 0 Bit 1 Latch */
586 #define B1__SHIFT 0x01 /* Port 0 Bit 1 Latch */
587 #define B1__LOW 0x00 /* P0.1 is low. Set P0.1 to drive low. */
588 #define B1__HIGH 0x02 /* P0.1 is high. Set P0.1 to drive or float high. */
589
590 #define B2__BMASK 0x04 /* Port 0 Bit 2 Latch */
591 #define B2__SHIFT 0x02 /* Port 0 Bit 2 Latch */
592 #define B2__LOW 0x00 /* P0.2 is low. Set P0.2 to drive low. */
593 #define B2__HIGH 0x04 /* P0.2 is high. Set P0.2 to drive or float high. */
594
595 #define B3__BMASK 0x08 /* Port 0 Bit 3 Latch */
596 #define B3__SHIFT 0x03 /* Port 0 Bit 3 Latch */
597 #define B3__LOW 0x00 /* P0.3 is low. Set P0.3 to drive low. */
598 #define B3__HIGH 0x08 /* P0.3 is high. Set P0.3 to drive or float high. */
599
600 #define B4__BMASK 0x10 /* Port 0 Bit 4 Latch */
601 #define B4__SHIFT 0x04 /* Port 0 Bit 4 Latch */
602 #define B4__LOW 0x00 /* P0.4 is low. Set P0.4 to drive low. */
603 #define B4__HIGH 0x10 /* P0.4 is high. Set P0.4 to drive or float high. */
604
605 #define B5__BMASK 0x20 /* Port 0 Bit 5 Latch */
606 #define B5__SHIFT 0x05 /* Port 0 Bit 5 Latch */
607 #define B5__LOW 0x00 /* P0.5 is low. Set P0.5 to drive low. */
608 #define B5__HIGH 0x20 /* P0.5 is high. Set P0.5 to drive or float high. */
609
610 #define B6__BMASK 0x40 /* Port 0 Bit 6 Latch */
611 #define B6__SHIFT 0x06 /* Port 0 Bit 6 Latch */
612 #define B6__LOW 0x00 /* P0.6 is low. Set P0.6 to drive low. */
613 #define B6__HIGH 0x40 /* P0.6 is high. Set P0.6 to drive or float high. */
614
615 #define B7__BMASK 0x80 /* Port 0 Bit 7 Latch */
616 #define B7__SHIFT 0x07 /* Port 0 Bit 7 Latch */
617 #define B7__LOW 0x00 /* P0.7 is low. Set P0.7 to drive low. */
618 #define B7__HIGH 0x80 /* P0.7 is high. Set P0.7 to drive or float high. */
619
620 /*------------------------------------------------------------------------------ */
621 /* P0MASK Enums (Port 0 Mask @ 0xFE) */
622 /*------------------------------------------------------------------------------ */
623 #define B0__BMASK 0x01 /* Port 0 Bit 0 Mask Value */
624 #define B0__SHIFT 0x00 /* Port 0 Bit 0 Mask Value */
625 #define B0__IGNORED 0x00 /* P0.0 pin logic value is ignored and will not cause a port mismatch event. */
626 #define B0__COMPARED 0x01 /* P0.0 pin logic value is compared to P0MAT.0. */
627
628 #define B1__BMASK 0x02 /* Port 0 Bit 1 Mask Value */
629 #define B1__SHIFT 0x01 /* Port 0 Bit 1 Mask Value */
630 #define B1__IGNORED 0x00 /* P0.1 pin logic value is ignored and will not cause a port mismatch event. */
631 #define B1__COMPARED 0x02 /* P0.1 pin logic value is compared to P0MAT.1. */
632
633 #define B2__BMASK 0x04 /* Port 0 Bit 2 Mask Value */
634 #define B2__SHIFT 0x02 /* Port 0 Bit 2 Mask Value */
635 #define B2__IGNORED 0x00 /* P0.2 pin logic value is ignored and will not cause a port mismatch event. */
636 #define B2__COMPARED 0x04 /* P0.2 pin logic value is compared to P0MAT.2. */
637
638 #define B3__BMASK 0x08 /* Port 0 Bit 3 Mask Value */
639 #define B3__SHIFT 0x03 /* Port 0 Bit 3 Mask Value */
640 #define B3__IGNORED 0x00 /* P0.3 pin logic value is ignored and will not cause a port mismatch event. */
641 #define B3__COMPARED 0x08 /* P0.3 pin logic value is compared to P0MAT.3. */
642
643 #define B4__BMASK 0x10 /* Port 0 Bit 4 Mask Value */
644 #define B4__SHIFT 0x04 /* Port 0 Bit 4 Mask Value */
645 #define B4__IGNORED 0x00 /* P0.4 pin logic value is ignored and will not cause a port mismatch event. */
646 #define B4__COMPARED 0x10 /* P0.4 pin logic value is compared to P0MAT.4. */
647
648 #define B5__BMASK 0x20 /* Port 0 Bit 5 Mask Value */
649 #define B5__SHIFT 0x05 /* Port 0 Bit 5 Mask Value */
650 #define B5__IGNORED 0x00 /* P0.5 pin logic value is ignored and will not cause a port mismatch event. */
651 #define B5__COMPARED 0x20 /* P0.5 pin logic value is compared to P0MAT.5. */
652
653 #define B6__BMASK 0x40 /* Port 0 Bit 6 Mask Value */
654 #define B6__SHIFT 0x06 /* Port 0 Bit 6 Mask Value */
655 #define B6__IGNORED 0x00 /* P0.6 pin logic value is ignored and will not cause a port mismatch event. */
656 #define B6__COMPARED 0x40 /* P0.6 pin logic value is compared to P0MAT.6. */
657
658 #define B7__BMASK 0x80 /* Port 0 Bit 7 Mask Value */
659 #define B7__SHIFT 0x07 /* Port 0 Bit 7 Mask Value */
660 #define B7__IGNORED 0x00 /* P0.7 pin logic value is ignored and will not cause a port mismatch event. */
661 #define B7__COMPARED 0x80 /* P0.7 pin logic value is compared to P0MAT.7. */
662
663 /*------------------------------------------------------------------------------ */
664 /* P0MAT Enums (Port 0 Match @ 0xFD) */
665 /*------------------------------------------------------------------------------ */
666 #define B0__BMASK 0x01 /* Port 0 Bit 0 Match Value */
667 #define B0__SHIFT 0x00 /* Port 0 Bit 0 Match Value */
668 #define B0__LOW 0x00 /* P0.0 pin logic value is compared with logic LOW. */
669 #define B0__HIGH 0x01 /* P0.0 pin logic value is compared with logic HIGH. */
670
671 #define B1__BMASK 0x02 /* Port 0 Bit 1 Match Value */
672 #define B1__SHIFT 0x01 /* Port 0 Bit 1 Match Value */
673 #define B1__LOW 0x00 /* P0.1 pin logic value is compared with logic LOW. */
674 #define B1__HIGH 0x02 /* P0.1 pin logic value is compared with logic HIGH. */
675
676 #define B2__BMASK 0x04 /* Port 0 Bit 2 Match Value */
677 #define B2__SHIFT 0x02 /* Port 0 Bit 2 Match Value */
678 #define B2__LOW 0x00 /* P0.2 pin logic value is compared with logic LOW. */
679 #define B2__HIGH 0x04 /* P0.2 pin logic value is compared with logic HIGH. */
680
681 #define B3__BMASK 0x08 /* Port 0 Bit 3 Match Value */
682 #define B3__SHIFT 0x03 /* Port 0 Bit 3 Match Value */
683 #define B3__LOW 0x00 /* P0.3 pin logic value is compared with logic LOW. */
684 #define B3__HIGH 0x08 /* P0.3 pin logic value is compared with logic HIGH. */
685
686 #define B4__BMASK 0x10 /* Port 0 Bit 4 Match Value */
687 #define B4__SHIFT 0x04 /* Port 0 Bit 4 Match Value */
688 #define B4__LOW 0x00 /* P0.4 pin logic value is compared with logic LOW. */
689 #define B4__HIGH 0x10 /* P0.4 pin logic value is compared with logic HIGH. */
690
691 #define B5__BMASK 0x20 /* Port 0 Bit 5 Match Value */
692 #define B5__SHIFT 0x05 /* Port 0 Bit 5 Match Value */
693 #define B5__LOW 0x00 /* P0.5 pin logic value is compared with logic LOW. */
694 #define B5__HIGH 0x20 /* P0.5 pin logic value is compared with logic HIGH. */
695
696 #define B6__BMASK 0x40 /* Port 0 Bit 6 Match Value */
697 #define B6__SHIFT 0x06 /* Port 0 Bit 6 Match Value */
698 #define B6__LOW 0x00 /* P0.6 pin logic value is compared with logic LOW. */
699 #define B6__HIGH 0x40 /* P0.6 pin logic value is compared with logic HIGH. */
700
701 #define B7__BMASK 0x80 /* Port 0 Bit 7 Match Value */
702 #define B7__SHIFT 0x07 /* Port 0 Bit 7 Match Value */
703 #define B7__LOW 0x00 /* P0.7 pin logic value is compared with logic LOW. */
704 #define B7__HIGH 0x80 /* P0.7 pin logic value is compared with logic HIGH. */
705
706 /*------------------------------------------------------------------------------ */
707 /* P1 Enums (Port 1 Pin Latch @ 0x90) */
708 /*------------------------------------------------------------------------------ */
709 #define B0__BMASK 0x01 /* Port 1 Bit 0 Latch */
710 #define B0__SHIFT 0x00 /* Port 1 Bit 0 Latch */
711 #define B0__LOW 0x00 /* P1.0 is low. Set P1.0 to drive low. */
712 #define B0__HIGH 0x01 /* P1.0 is high. Set P1.0 to drive or float high. */
713
714 #define B1__BMASK 0x02 /* Port 1 Bit 1 Latch */
715 #define B1__SHIFT 0x01 /* Port 1 Bit 1 Latch */
716 #define B1__LOW 0x00 /* P1.1 is low. Set P1.1 to drive low. */
717 #define B1__HIGH 0x02 /* P1.1 is high. Set P1.1 to drive or float high. */
718
719 #define B2__BMASK 0x04 /* Port 1 Bit 2 Latch */
720 #define B2__SHIFT 0x02 /* Port 1 Bit 2 Latch */
721 #define B2__LOW 0x00 /* P1.2 is low. Set P1.2 to drive low. */
722 #define B2__HIGH 0x04 /* P1.2 is high. Set P1.2 to drive or float high. */
723
724 #define B3__BMASK 0x08 /* Port 1 Bit 3 Latch */
725 #define B3__SHIFT 0x03 /* Port 1 Bit 3 Latch */
726 #define B3__LOW 0x00 /* P1.3 is low. Set P1.3 to drive low. */
727 #define B3__HIGH 0x08 /* P1.3 is high. Set P1.3 to drive or float high. */
728
729 #define B4__BMASK 0x10 /* Port 1 Bit 4 Latch */
730 #define B4__SHIFT 0x04 /* Port 1 Bit 4 Latch */
731 #define B4__LOW 0x00 /* P1.4 is low. Set P1.4 to drive low. */
732 #define B4__HIGH 0x10 /* P1.4 is high. Set P1.4 to drive or float high. */
733
734 #define B5__BMASK 0x20 /* Port 1 Bit 5 Latch */
735 #define B5__SHIFT 0x05 /* Port 1 Bit 5 Latch */
736 #define B5__LOW 0x00 /* P1.5 is low. Set P1.5 to drive low. */
737 #define B5__HIGH 0x20 /* P1.5 is high. Set P1.5 to drive or float high. */
738
739 #define B6__BMASK 0x40 /* Port 1 Bit 6 Latch */
740 #define B6__SHIFT 0x06 /* Port 1 Bit 6 Latch */
741 #define B6__LOW 0x00 /* P1.6 is low. Set P1.6 to drive low. */
742 #define B6__HIGH 0x40 /* P1.6 is high. Set P1.6 to drive or float high. */
743
744 #define B7__BMASK 0x80 /* Port 1 Bit 7 Latch */
745 #define B7__SHIFT 0x07 /* Port 1 Bit 7 Latch */
746 #define B7__LOW 0x00 /* P1.7 is low. Set P1.7 to drive low. */
747 #define B7__HIGH 0x80 /* P1.7 is high. Set P1.7 to drive or float high. */
748
749 /*------------------------------------------------------------------------------ */
750 /* P1MASK Enums (Port 1 Mask @ 0xEE) */
751 /*------------------------------------------------------------------------------ */
752 #define B0__BMASK 0x01 /* Port 1 Bit 0 Mask Value */
753 #define B0__SHIFT 0x00 /* Port 1 Bit 0 Mask Value */
754 #define B0__IGNORED 0x00 /* P1.0 pin logic value is ignored and will not cause a port mismatch event. */
755 #define B0__COMPARED 0x01 /* P1.0 pin logic value is compared to P1MAT.0. */
756
757 #define B1__BMASK 0x02 /* Port 1 Bit 1 Mask Value */
758 #define B1__SHIFT 0x01 /* Port 1 Bit 1 Mask Value */
759 #define B1__IGNORED 0x00 /* P1.1 pin logic value is ignored and will not cause a port mismatch event. */
760 #define B1__COMPARED 0x02 /* P1.1 pin logic value is compared to P1MAT.1. */
761
762 #define B2__BMASK 0x04 /* Port 1 Bit 2 Mask Value */
763 #define B2__SHIFT 0x02 /* Port 1 Bit 2 Mask Value */
764 #define B2__IGNORED 0x00 /* P1.2 pin logic value is ignored and will not cause a port mismatch event. */
765 #define B2__COMPARED 0x04 /* P1.2 pin logic value is compared to P1MAT.2. */
766
767 #define B3__BMASK 0x08 /* Port 1 Bit 3 Mask Value */
768 #define B3__SHIFT 0x03 /* Port 1 Bit 3 Mask Value */
769 #define B3__IGNORED 0x00 /* P1.3 pin logic value is ignored and will not cause a port mismatch event. */
770 #define B3__COMPARED 0x08 /* P1.3 pin logic value is compared to P1MAT.3. */
771
772 #define B4__BMASK 0x10 /* Port 1 Bit 4 Mask Value */
773 #define B4__SHIFT 0x04 /* Port 1 Bit 4 Mask Value */
774 #define B4__IGNORED 0x00 /* P1.4 pin logic value is ignored and will not cause a port mismatch event. */
775 #define B4__COMPARED 0x10 /* P1.4 pin logic value is compared to P1MAT.4. */
776
777 #define B5__BMASK 0x20 /* Port 1 Bit 5 Mask Value */
778 #define B5__SHIFT 0x05 /* Port 1 Bit 5 Mask Value */
779 #define B5__IGNORED 0x00 /* P1.5 pin logic value is ignored and will not cause a port mismatch event. */
780 #define B5__COMPARED 0x20 /* P1.5 pin logic value is compared to P1MAT.5. */
781
782 #define B6__BMASK 0x40 /* Port 1 Bit 6 Mask Value */
783 #define B6__SHIFT 0x06 /* Port 1 Bit 6 Mask Value */
784 #define B6__IGNORED 0x00 /* P1.6 pin logic value is ignored and will not cause a port mismatch event. */
785 #define B6__COMPARED 0x40 /* P1.6 pin logic value is compared to P1MAT.6. */
786
787 #define B7__BMASK 0x80 /* Port 1 Bit 7 Mask Value */
788 #define B7__SHIFT 0x07 /* Port 1 Bit 7 Mask Value */
789 #define B7__IGNORED 0x00 /* P1.7 pin logic value is ignored and will not cause a port mismatch event. */
790 #define B7__COMPARED 0x80 /* P1.7 pin logic value is compared to P1MAT.7. */
791
792 /*------------------------------------------------------------------------------ */
793 /* P1MAT Enums (Port 1 Match @ 0xED) */
794 /*------------------------------------------------------------------------------ */
795 #define B0__BMASK 0x01 /* Port 1 Bit 0 Match Value */
796 #define B0__SHIFT 0x00 /* Port 1 Bit 0 Match Value */
797 #define B0__LOW 0x00 /* P1.0 pin logic value is compared with logic LOW. */
798 #define B0__HIGH 0x01 /* P1.0 pin logic value is compared with logic HIGH. */
799
800 #define B1__BMASK 0x02 /* Port 1 Bit 1 Match Value */
801 #define B1__SHIFT 0x01 /* Port 1 Bit 1 Match Value */
802 #define B1__LOW 0x00 /* P1.1 pin logic value is compared with logic LOW. */
803 #define B1__HIGH 0x02 /* P1.1 pin logic value is compared with logic HIGH. */
804
805 #define B2__BMASK 0x04 /* Port 1 Bit 2 Match Value */
806 #define B2__SHIFT 0x02 /* Port 1 Bit 2 Match Value */
807 #define B2__LOW 0x00 /* P1.2 pin logic value is compared with logic LOW. */
808 #define B2__HIGH 0x04 /* P1.2 pin logic value is compared with logic HIGH. */
809
810 #define B3__BMASK 0x08 /* Port 1 Bit 3 Match Value */
811 #define B3__SHIFT 0x03 /* Port 1 Bit 3 Match Value */
812 #define B3__LOW 0x00 /* P1.3 pin logic value is compared with logic LOW. */
813 #define B3__HIGH 0x08 /* P1.3 pin logic value is compared with logic HIGH. */
814
815 #define B4__BMASK 0x10 /* Port 1 Bit 4 Match Value */
816 #define B4__SHIFT 0x04 /* Port 1 Bit 4 Match Value */
817 #define B4__LOW 0x00 /* P1.4 pin logic value is compared with logic LOW. */
818 #define B4__HIGH 0x10 /* P1.4 pin logic value is compared with logic HIGH. */
819
820 #define B5__BMASK 0x20 /* Port 1 Bit 5 Match Value */
821 #define B5__SHIFT 0x05 /* Port 1 Bit 5 Match Value */
822 #define B5__LOW 0x00 /* P1.5 pin logic value is compared with logic LOW. */
823 #define B5__HIGH 0x20 /* P1.5 pin logic value is compared with logic HIGH. */
824
825 #define B6__BMASK 0x40 /* Port 1 Bit 6 Match Value */
826 #define B6__SHIFT 0x06 /* Port 1 Bit 6 Match Value */
827 #define B6__LOW 0x00 /* P1.6 pin logic value is compared with logic LOW. */
828 #define B6__HIGH 0x40 /* P1.6 pin logic value is compared with logic HIGH. */
829
830 #define B7__BMASK 0x80 /* Port 1 Bit 7 Match Value */
831 #define B7__SHIFT 0x07 /* Port 1 Bit 7 Match Value */
832 #define B7__LOW 0x00 /* P1.7 pin logic value is compared with logic LOW. */
833 #define B7__HIGH 0x80 /* P1.7 pin logic value is compared with logic HIGH. */
834
835 /*------------------------------------------------------------------------------ */
836 /* P1MDIN Enums (Port 1 Input Mode @ 0xF2) */
837 /*------------------------------------------------------------------------------ */
838 #define B0__BMASK 0x01 /* Port 1 Bit 0 Input Mode */
839 #define B0__SHIFT 0x00 /* Port 1 Bit 0 Input Mode */
840 #define B0__ANALOG 0x00 /* P1.0 pin is configured for analog mode. */
841 #define B0__DIGITAL 0x01 /* P1.0 pin is configured for digital mode. */
842
843 #define B1__BMASK 0x02 /* Port 1 Bit 1 Input Mode */
844 #define B1__SHIFT 0x01 /* Port 1 Bit 1 Input Mode */
845 #define B1__ANALOG 0x00 /* P1.1 pin is configured for analog mode. */
846 #define B1__DIGITAL 0x02 /* P1.1 pin is configured for digital mode. */
847
848 #define B2__BMASK 0x04 /* Port 1 Bit 2 Input Mode */
849 #define B2__SHIFT 0x02 /* Port 1 Bit 2 Input Mode */
850 #define B2__ANALOG 0x00 /* P1.2 pin is configured for analog mode. */
851 #define B2__DIGITAL 0x04 /* P1.2 pin is configured for digital mode. */
852
853 #define B3__BMASK 0x08 /* Port 1 Bit 3 Input Mode */
854 #define B3__SHIFT 0x03 /* Port 1 Bit 3 Input Mode */
855 #define B3__ANALOG 0x00 /* P1.3 pin is configured for analog mode. */
856 #define B3__DIGITAL 0x08 /* P1.3 pin is configured for digital mode. */
857
858 #define B4__BMASK 0x10 /* Port 1 Bit 4 Input Mode */
859 #define B4__SHIFT 0x04 /* Port 1 Bit 4 Input Mode */
860 #define B4__ANALOG 0x00 /* P1.4 pin is configured for analog mode. */
861 #define B4__DIGITAL 0x10 /* P1.4 pin is configured for digital mode. */
862
863 #define B5__BMASK 0x20 /* Port 1 Bit 5 Input Mode */
864 #define B5__SHIFT 0x05 /* Port 1 Bit 5 Input Mode */
865 #define B5__ANALOG 0x00 /* P1.5 pin is configured for analog mode. */
866 #define B5__DIGITAL 0x20 /* P1.5 pin is configured for digital mode. */
867
868 #define B6__BMASK 0x40 /* Port 1 Bit 6 Input Mode */
869 #define B6__SHIFT 0x06 /* Port 1 Bit 6 Input Mode */
870 #define B6__ANALOG 0x00 /* P1.6 pin is configured for analog mode. */
871 #define B6__DIGITAL 0x40 /* P1.6 pin is configured for digital mode. */
872
873 #define B7__BMASK 0x80 /* Port 1 Bit 7 Input Mode */
874 #define B7__SHIFT 0x07 /* Port 1 Bit 7 Input Mode */
875 #define B7__ANALOG 0x00 /* P1.7 pin is configured for analog mode. */
876 #define B7__DIGITAL 0x80 /* P1.7 pin is configured for digital mode. */
877
878 /*------------------------------------------------------------------------------ */
879 /* P1MDOUT Enums (Port 1 Output Mode @ 0xA5) */
880 /*------------------------------------------------------------------------------ */
881 #define B0__BMASK 0x01 /* Port 1 Bit 0 Output Mode */
882 #define B0__SHIFT 0x00 /* Port 1 Bit 0 Output Mode */
883 #define B0__OPEN_DRAIN 0x00 /* P1.0 output is open-drain. */
884 #define B0__PUSH_PULL 0x01 /* P1.0 output is push-pull. */
885
886 #define B1__BMASK 0x02 /* Port 1 Bit 1 Output Mode */
887 #define B1__SHIFT 0x01 /* Port 1 Bit 1 Output Mode */
888 #define B1__OPEN_DRAIN 0x00 /* P1.1 output is open-drain. */
889 #define B1__PUSH_PULL 0x02 /* P1.1 output is push-pull. */
890
891 #define B2__BMASK 0x04 /* Port 1 Bit 2 Output Mode */
892 #define B2__SHIFT 0x02 /* Port 1 Bit 2 Output Mode */
893 #define B2__OPEN_DRAIN 0x00 /* P1.2 output is open-drain. */
894 #define B2__PUSH_PULL 0x04 /* P1.2 output is push-pull. */
895
896 #define B3__BMASK 0x08 /* Port 1 Bit 3 Output Mode */
897 #define B3__SHIFT 0x03 /* Port 1 Bit 3 Output Mode */
898 #define B3__OPEN_DRAIN 0x00 /* P1.3 output is open-drain. */
899 #define B3__PUSH_PULL 0x08 /* P1.3 output is push-pull. */
900
901 #define B4__BMASK 0x10 /* Port 1 Bit 4 Output Mode */
902 #define B4__SHIFT 0x04 /* Port 1 Bit 4 Output Mode */
903 #define B4__OPEN_DRAIN 0x00 /* P1.4 output is open-drain. */
904 #define B4__PUSH_PULL 0x10 /* P1.4 output is push-pull. */
905
906 #define B5__BMASK 0x20 /* Port 1 Bit 5 Output Mode */
907 #define B5__SHIFT 0x05 /* Port 1 Bit 5 Output Mode */
908 #define B5__OPEN_DRAIN 0x00 /* P1.5 output is open-drain. */
909 #define B5__PUSH_PULL 0x20 /* P1.5 output is push-pull. */
910
911 #define B6__BMASK 0x40 /* Port 1 Bit 6 Output Mode */
912 #define B6__SHIFT 0x06 /* Port 1 Bit 6 Output Mode */
913 #define B6__OPEN_DRAIN 0x00 /* P1.6 output is open-drain. */
914 #define B6__PUSH_PULL 0x40 /* P1.6 output is push-pull. */
915
916 #define B7__BMASK 0x80 /* Port 1 Bit 7 Output Mode */
917 #define B7__SHIFT 0x07 /* Port 1 Bit 7 Output Mode */
918 #define B7__OPEN_DRAIN 0x00 /* P1.7 output is open-drain. */
919 #define B7__PUSH_PULL 0x80 /* P1.7 output is push-pull. */
920
921 /*------------------------------------------------------------------------------ */
922 /* P1SKIP Enums (Port 1 Skip @ 0xD5) */
923 /*------------------------------------------------------------------------------ */
924 #define B0__BMASK 0x01 /* Port 1 Bit 0 Skip */
925 #define B0__SHIFT 0x00 /* Port 1 Bit 0 Skip */
926 #define B0__NOT_SKIPPED 0x00 /* P1.0 pin is not skipped by the crossbar. */
927 #define B0__SKIPPED 0x01 /* P1.0 pin is skipped by the crossbar. */
928
929 #define B1__BMASK 0x02 /* Port 1 Bit 1 Skip */
930 #define B1__SHIFT 0x01 /* Port 1 Bit 1 Skip */
931 #define B1__NOT_SKIPPED 0x00 /* P1.1 pin is not skipped by the crossbar. */
932 #define B1__SKIPPED 0x02 /* P1.1 pin is skipped by the crossbar. */
933
934 #define B2__BMASK 0x04 /* Port 1 Bit 2 Skip */
935 #define B2__SHIFT 0x02 /* Port 1 Bit 2 Skip */
936 #define B2__NOT_SKIPPED 0x00 /* P1.2 pin is not skipped by the crossbar. */
937 #define B2__SKIPPED 0x04 /* P1.2 pin is skipped by the crossbar. */
938
939 #define B3__BMASK 0x08 /* Port 1 Bit 3 Skip */
940 #define B3__SHIFT 0x03 /* Port 1 Bit 3 Skip */
941 #define B3__NOT_SKIPPED 0x00 /* P1.3 pin is not skipped by the crossbar. */
942 #define B3__SKIPPED 0x08 /* P1.3 pin is skipped by the crossbar. */
943
944 #define B4__BMASK 0x10 /* Port 1 Bit 4 Skip */
945 #define B4__SHIFT 0x04 /* Port 1 Bit 4 Skip */
946 #define B4__NOT_SKIPPED 0x00 /* P1.4 pin is not skipped by the crossbar. */
947 #define B4__SKIPPED 0x10 /* P1.4 pin is skipped by the crossbar. */
948
949 #define B5__BMASK 0x20 /* Port 1 Bit 5 Skip */
950 #define B5__SHIFT 0x05 /* Port 1 Bit 5 Skip */
951 #define B5__NOT_SKIPPED 0x00 /* P1.5 pin is not skipped by the crossbar. */
952 #define B5__SKIPPED 0x20 /* P1.5 pin is skipped by the crossbar. */
953
954 #define B6__BMASK 0x40 /* Port 1 Bit 6 Skip */
955 #define B6__SHIFT 0x06 /* Port 1 Bit 6 Skip */
956 #define B6__NOT_SKIPPED 0x00 /* P1.6 pin is not skipped by the crossbar. */
957 #define B6__SKIPPED 0x40 /* P1.6 pin is skipped by the crossbar. */
958
959 #define B7__BMASK 0x80 /* Port 1 Bit 7 Skip */
960 #define B7__SHIFT 0x07 /* Port 1 Bit 7 Skip */
961 #define B7__NOT_SKIPPED 0x00 /* P1.7 pin is not skipped by the crossbar. */
962 #define B7__SKIPPED 0x80 /* P1.7 pin is skipped by the crossbar. */
963
964 /*------------------------------------------------------------------------------ */
965 /* P2 Enums (Port 2 Pin Latch @ 0xA0) */
966 /*------------------------------------------------------------------------------ */
967 #define B0__BMASK 0x01 /* Port 2 Bit 0 Latch */
968 #define B0__SHIFT 0x00 /* Port 2 Bit 0 Latch */
969 #define B0__LOW 0x00 /* P2.0 is low. Set P2.0 to drive low. */
970 #define B0__HIGH 0x01 /* P2.0 is high. Set P2.0 to drive or float high. */
971
972 #define B1__BMASK 0x02 /* Port 2 Bit 1 Latch */
973 #define B1__SHIFT 0x01 /* Port 2 Bit 1 Latch */
974 #define B1__LOW 0x00 /* P2.1 is low. Set P2.1 to drive low. */
975 #define B1__HIGH 0x02 /* P2.1 is high. Set P2.1 to drive or float high. */
976
977 /*------------------------------------------------------------------------------ */
978 /* P2MDOUT Enums (Port 2 Output Mode @ 0xA6) */
979 /*------------------------------------------------------------------------------ */
980 #define B0__BMASK 0x01 /* Port 2 Bit 0 Output Mode */
981 #define B0__SHIFT 0x00 /* Port 2 Bit 0 Output Mode */
982 #define B0__OPEN_DRAIN 0x00 /* P2.0 output is open-drain. */
983 #define B0__PUSH_PULL 0x01 /* P2.0 output is push-pull. */
984
985 #define B1__BMASK 0x02 /* Port 2 Bit 1 Output Mode */
986 #define B1__SHIFT 0x01 /* Port 2 Bit 1 Output Mode */
987 #define B1__OPEN_DRAIN 0x00 /* P2.1 output is open-drain. */
988 #define B1__PUSH_PULL 0x02 /* P2.1 output is push-pull. */
989
990 /*------------------------------------------------------------------------------ */
991 /* XBR0 Enums (Port I/O Crossbar 0 @ 0xE1) */
992 /*------------------------------------------------------------------------------ */
993 #define URT0E__BMASK 0x01 /* UART I/O Output Enable */
994 #define URT0E__SHIFT 0x00 /* UART I/O Output Enable */
995 #define URT0E__DISABLED 0x00 /* UART I/O unavailable at Port pin. */
996 #define URT0E__ENABLED 0x01 /* UART TX, RX routed to Port pins P0.4 and P0.5. */
997
998 #define SPI0E__BMASK 0x02 /* SPI I/O Enable */
999 #define SPI0E__SHIFT 0x01 /* SPI I/O Enable */
1000 #define SPI0E__DISABLED 0x00 /* SPI I/O unavailable at Port pins. */
1001 #define SPI0E__ENABLED 0x02 /* SPI I/O routed to Port pins. The SPI can be assigned either 3 or 4 GPIO pins. */
1002
1003 #define SMB0E__BMASK 0x04 /* SMB0 I/O Enable */
1004 #define SMB0E__SHIFT 0x02 /* SMB0 I/O Enable */
1005 #define SMB0E__DISABLED 0x00 /* SMBus 0 I/O unavailable at Port pins. */
1006 #define SMB0E__ENABLED 0x04 /* SMBus 0 I/O routed to Port pins. */
1007
1008 #define CP0E__BMASK 0x08 /* Comparator0 Output Enable */
1009 #define CP0E__SHIFT 0x03 /* Comparator0 Output Enable */
1010 #define CP0E__DISABLED 0x00 /* CP0 unavailable at Port pin. */
1011 #define CP0E__ENABLED 0x08 /* CP0 routed to Port pin. */
1012
1013 #define CP0AE__BMASK 0x10 /* Comparator0 Asynchronous Output Enable */
1014 #define CP0AE__SHIFT 0x04 /* Comparator0 Asynchronous Output Enable */
1015 #define CP0AE__DISABLED 0x00 /* Asynchronous CP0 unavailable at Port pin. */
1016 #define CP0AE__ENABLED 0x10 /* Asynchronous CP0 routed to Port pin. */
1017
1018 #define CP1E__BMASK 0x20 /* Comparator1 Output Enable */
1019 #define CP1E__SHIFT 0x05 /* Comparator1 Output Enable */
1020 #define CP1E__DISABLED 0x00 /* CP1 unavailable at Port pin. */
1021 #define CP1E__ENABLED 0x20 /* CP1 routed to Port pin. */
1022
1023 #define CP1AE__BMASK 0x40 /* Comparator1 Asynchronous Output Enable */
1024 #define CP1AE__SHIFT 0x06 /* Comparator1 Asynchronous Output Enable */
1025 #define CP1AE__DISABLED 0x00 /* Asynchronous CP1 unavailable at Port pin. */
1026 #define CP1AE__ENABLED 0x40 /* Asynchronous CP1 routed to Port pin. */
1027
1028 #define SYSCKE__BMASK 0x80 /* SYSCLK Output Enable */
1029 #define SYSCKE__SHIFT 0x07 /* SYSCLK Output Enable */
1030 #define SYSCKE__DISABLED 0x00 /* SYSCLK unavailable at Port pin. */
1031 #define SYSCKE__ENABLED 0x80 /* SYSCLK output routed to Port pin. */
1032
1033 /*------------------------------------------------------------------------------ */
1034 /* XBR1 Enums (Port I/O Crossbar 1 @ 0xE2) */
1035 /*------------------------------------------------------------------------------ */
1036 #define PCA0ME__FMASK 0x03 /* PCA Module I/O Enable */
1037 #define PCA0ME__SHIFT 0x00 /* PCA Module I/O Enable */
1038 #define PCA0ME__DISABLED 0x00 /* All PCA I/O unavailable at Port pins. */
1039 #define PCA0ME__CEX0 0x01 /* CEX0 routed to Port pin. */
1040 #define PCA0ME__CEX0_CEX1 0x02 /* CEX0, CEX1 routed to Port pins. */
1041 #define PCA0ME__CEX0_CEX1_CEX2 0x03 /* CEX0, CEX1, CEX2 routed to Port pins. */
1042
1043 #define ECIE__BMASK 0x04 /* PCA0 External Counter Input Enable */
1044 #define ECIE__SHIFT 0x02 /* PCA0 External Counter Input Enable */
1045 #define ECIE__DISABLED 0x00 /* ECI unavailable at Port pin. */
1046 #define ECIE__ENABLED 0x04 /* ECI routed to Port pin. */
1047
1048 #define T0E__BMASK 0x08 /* T0 Enable */
1049 #define T0E__SHIFT 0x03 /* T0 Enable */
1050 #define T0E__DISABLED 0x00 /* T0 unavailable at Port pin. */
1051 #define T0E__ENABLED 0x08 /* T0 routed to Port pin. */
1052
1053 #define T1E__BMASK 0x10 /* T1 Enable */
1054 #define T1E__SHIFT 0x04 /* T1 Enable */
1055 #define T1E__DISABLED 0x00 /* T1 unavailable at Port pin. */
1056 #define T1E__ENABLED 0x10 /* T1 routed to Port pin. */
1057
1058 #define T2E__BMASK 0x20 /* T2 Enable */
1059 #define T2E__SHIFT 0x05 /* T2 Enable */
1060 #define T2E__DISABLED 0x00 /* T2 unavailable at Port pin. */
1061 #define T2E__ENABLED 0x20 /* T2 routed to Port pin. */
1062
1063 /*------------------------------------------------------------------------------ */
1064 /* XBR2 Enums (Port I/O Crossbar 2 @ 0xE3) */
1065 /*------------------------------------------------------------------------------ */
1066 #define XBARE__BMASK 0x40 /* Crossbar Enable */
1067 #define XBARE__SHIFT 0x06 /* Crossbar Enable */
1068 #define XBARE__DISABLED 0x00 /* Crossbar disabled. */
1069 #define XBARE__ENABLED 0x40 /* Crossbar enabled. */
1070
1071 #define WEAKPUD__BMASK 0x80 /* Port I/O Weak Pullup Disable */
1072 #define WEAKPUD__SHIFT 0x07 /* Port I/O Weak Pullup Disable */
1073 #define WEAKPUD__PULL_UPS_ENABLED 0x00 /* Weak Pullups enabled (except for Ports whose I/O are configured for analog mode). */
1074 #define WEAKPUD__PULL_UPS_DISABLED 0x80 /* Weak Pullups disabled. */
1075
1076 /*------------------------------------------------------------------------------ */
1077 /* ADC0CN1 Enums (ADC0 Control 1 @ 0xB2) */
1078 /*------------------------------------------------------------------------------ */
1079 #define ADCMBE__BMASK 0x01 /* Common Mode Buffer Enable */
1080 #define ADCMBE__SHIFT 0x00 /* Common Mode Buffer Enable */
1081 #define ADCMBE__CM_BUFFER_DISABLED 0x00 /* Disable the common mode buffer. This setting should be used only if the tracking time of the signal is greater than 1.5 us. */
1082 #define ADCMBE__CM_BUFFER_ENABLED 0x01 /* Enable the common mode buffer. This setting should be used in most cases, and will give the best dynamic ADC performance. The common mode buffer must be enabled if signal tracking time is less than or equal to 1.5 us. */
1083
1084 /*------------------------------------------------------------------------------ */
1085 /* ADC0GTH Enums (ADC0 Greater-Than High Byte @ 0xC4) */
1086 /*------------------------------------------------------------------------------ */
1087 #define ADC0GTH__FMASK 0xFF /* Greater-Than High Byte */
1088 #define ADC0GTH__SHIFT 0x00 /* Greater-Than High Byte */
1089
1090 /*------------------------------------------------------------------------------ */
1091 /* ADC0GTL Enums (ADC0 Greater-Than Low Byte @ 0xC3) */
1092 /*------------------------------------------------------------------------------ */
1093 #define ADC0GTL__FMASK 0xFF /* Greater-Than Low Byte */
1094 #define ADC0GTL__SHIFT 0x00 /* Greater-Than Low Byte */
1095
1096 /*------------------------------------------------------------------------------ */
1097 /* ADC0H Enums (ADC0 Data Word High Byte @ 0xBE) */
1098 /*------------------------------------------------------------------------------ */
1099 #define ADC0H__FMASK 0xFF /* Data Word High Byte */
1100 #define ADC0H__SHIFT 0x00 /* Data Word High Byte */
1101
1102 /*------------------------------------------------------------------------------ */
1103 /* ADC0L Enums (ADC0 Data Word Low Byte @ 0xBD) */
1104 /*------------------------------------------------------------------------------ */
1105 #define ADC0L__FMASK 0xFF /* Data Word Low Byte */
1106 #define ADC0L__SHIFT 0x00 /* Data Word Low Byte */
1107
1108 /*------------------------------------------------------------------------------ */
1109 /* ADC0LTH Enums (ADC0 Less-Than High Byte @ 0xC6) */
1110 /*------------------------------------------------------------------------------ */
1111 #define ADC0LTH__FMASK 0xFF /* Less-Than High Byte */
1112 #define ADC0LTH__SHIFT 0x00 /* Less-Than High Byte */
1113
1114 /*------------------------------------------------------------------------------ */
1115 /* ADC0LTL Enums (ADC0 Less-Than Low Byte @ 0xC5) */
1116 /*------------------------------------------------------------------------------ */
1117 #define ADC0LTL__FMASK 0xFF /* Less-Than Low Byte */
1118 #define ADC0LTL__SHIFT 0x00 /* Less-Than Low Byte */
1119
1120 /*------------------------------------------------------------------------------ */
1121 /* ADC0MX Enums (ADC0 Multiplexer Selection @ 0xBB) */
1122 /*------------------------------------------------------------------------------ */
1123 #define ADC0MX__FMASK 0x1F /* AMUX0 Positive Input Selection */
1124 #define ADC0MX__SHIFT 0x00 /* AMUX0 Positive Input Selection */
1125 #define ADC0MX__ADC0P0 0x00 /* Select ADC0.0. */
1126 #define ADC0MX__ADC0P1 0x01 /* Select ADC0.1. */
1127 #define ADC0MX__ADC0P2 0x02 /* Select ADC0.2. */
1128 #define ADC0MX__ADC0P3 0x03 /* Select ADC0.3. */
1129 #define ADC0MX__ADC0P4 0x04 /* Select ADC0.4. */
1130 #define ADC0MX__ADC0P5 0x05 /* Select ADC0.5. */
1131 #define ADC0MX__ADC0P6 0x06 /* Select ADC0.6. */
1132 #define ADC0MX__ADC0P7 0x07 /* Select ADC0.7. */
1133 #define ADC0MX__ADC0P8 0x08 /* Select ADC0.8. */
1134 #define ADC0MX__ADC0P9 0x09 /* Select ADC0.9. */
1135 #define ADC0MX__ADC0P10 0x0A /* Select ADC0.10. */
1136 #define ADC0MX__ADC0P11 0x0B /* Select ADC0.11. */
1137 #define ADC0MX__ADC0P12 0x0C /* Select ADC0.12. */
1138 #define ADC0MX__ADC0P13 0x0D /* Select ADC0.13. */
1139 #define ADC0MX__ADC0P14 0x0E /* Select ADC0.14. */
1140 #define ADC0MX__ADC0P15 0x0F /* Select ADC0.15. */
1141 #define ADC0MX__TEMP 0x10 /* Select ADC0.16. */
1142 #define ADC0MX__LDO_OUT 0x11 /* Select ADC0.17. */
1143 #define ADC0MX__VDD 0x12 /* Select ADC0.18. */
1144 #define ADC0MX__GND 0x13 /* Select ADC0.19. */
1145 #define ADC0MX__NONE 0x1F /* No input selected. */
1146
1147 /*------------------------------------------------------------------------------ */
1148 /* ADC0PWR Enums (ADC0 Power Control @ 0xDF) */
1149 /*------------------------------------------------------------------------------ */
1150 #define ADPWR__FMASK 0x0F /* Burst Mode Power Up Time */
1151 #define ADPWR__SHIFT 0x00 /* Burst Mode Power Up Time */
1152
1153 #define ADLPM__BMASK 0x10 /* Low Power Mode Enable */
1154 #define ADLPM__SHIFT 0x04 /* Low Power Mode Enable */
1155 #define ADLPM__LP_BUFFER_DISABLED 0x00 /* Disable low power mode. */
1156 #define ADLPM__LP_BUFFER_ENABLED 0x10 /* Enable low power mode (requires extended tracking time). */
1157
1158 #define ADMXLP__BMASK 0x20 /* Mux and Reference Low Power Mode Enable */
1159 #define ADMXLP__SHIFT 0x05 /* Mux and Reference Low Power Mode Enable */
1160 #define ADMXLP__LP_MUX_VREF_DISABLED 0x00 /* Low power mode disabled. */
1161 #define ADMXLP__LP_MUX_VREF_ENABLED 0x20 /* Low power mode enabled (SAR clock < 4 MHz). */
1162
1163 #define ADBIAS__FMASK 0xC0 /* Bias Power Select */
1164 #define ADBIAS__SHIFT 0x06 /* Bias Power Select */
1165 #define ADBIAS__MODE0 0x00 /* Select bias current mode 0. Recommended to use modes 1, 2, or 3. */
1166 #define ADBIAS__MODE1 0x40 /* Select bias current mode 1 (SARCLK <= 16 MHz). */
1167 #define ADBIAS__MODE2 0x80 /* Select bias current mode 2. */
1168 #define ADBIAS__MODE3 0xC0 /* Select bias current mode 3 (SARCLK <= 4 MHz). */
1169
1170 /*------------------------------------------------------------------------------ */
1171 /* ADC0TK Enums (ADC0 Burst Mode Track Time @ 0xB9) */
1172 /*------------------------------------------------------------------------------ */
1173 #define ADTK__FMASK 0x3F /* Burst Mode Tracking Time */
1174 #define ADTK__SHIFT 0x00 /* Burst Mode Tracking Time */
1175
1176 #define AD12SM__BMASK 0x80 /* 12-Bit Sampling Mode */
1177 #define AD12SM__SHIFT 0x07 /* 12-Bit Sampling Mode */
1178 #define AD12SM__SAMPLE_FOUR 0x00 /* The ADC will re-track and sample the input four times during a 12-bit conversion. */
1179 #define AD12SM__SAMPLE_ONCE 0x80 /* The ADC will sample the input once at the beginning of each 12-bit conversion. The ADTK field can be set to 63 to maximize throughput. */
1180
1181 /*------------------------------------------------------------------------------ */
1182 /* REF0CN Enums (Voltage Reference Control @ 0xD1) */
1183 /*------------------------------------------------------------------------------ */
1184 #define TEMPE__BMASK 0x04 /* Temperature Sensor Enable */
1185 #define TEMPE__SHIFT 0x02 /* Temperature Sensor Enable */
1186 #define TEMPE__TEMP_DISABLED 0x00 /* Disable the Temperature Sensor. */
1187 #define TEMPE__TEMP_ENABLED 0x04 /* Enable the Temperature Sensor. */
1188
1189 #define REFSL__FMASK 0x18 /* Voltage Reference Select */
1190 #define REFSL__SHIFT 0x03 /* Voltage Reference Select */
1191 #define REFSL__VREF_PIN 0x00 /* The ADC0 voltage reference is the P0.0/VREF pin. */
1192 #define REFSL__VDD_PIN 0x08 /* The ADC0 voltage reference is the VDD pin. */
1193 #define REFSL__INTERNAL_LDO 0x10 /* The ADC0 voltage reference is the internal 1.8 V digital supply voltage. */
1194 #define REFSL__INTERNAL_VREF 0x18 /* The ADC0 voltage reference is the internal voltage reference. */
1195
1196 #define GNDSL__BMASK 0x20 /* Analog Ground Reference */
1197 #define GNDSL__SHIFT 0x05 /* Analog Ground Reference */
1198 #define GNDSL__GND_PIN 0x00 /* The ADC0 ground reference is the GND pin. */
1199 #define GNDSL__AGND_PIN 0x20 /* The ADC0 ground reference is the P0.1/AGND pin. */
1200
1201 #define IREFLVL__BMASK 0x80 /* Internal Voltage Reference Level */
1202 #define IREFLVL__SHIFT 0x07 /* Internal Voltage Reference Level */
1203 #define IREFLVL__1P65 0x00 /* The internal reference operates at 1.65 V nominal. */
1204 #define IREFLVL__2P4 0x80 /* The internal reference operates at 2.4 V nominal. */
1205
1206 /*------------------------------------------------------------------------------ */
1207 /* REG0CN Enums (Voltage Regulator 0 Control @ 0xC9) */
1208 /*------------------------------------------------------------------------------ */
1209 #define STOPCF__BMASK 0x08 /* Stop Mode Configuration */
1210 #define STOPCF__SHIFT 0x03 /* Stop Mode Configuration */
1211 #define STOPCF__ACTIVE 0x00 /* Regulator is still active in stop mode. Any enabled reset source will reset the device. */
1212 #define STOPCF__SHUTDOWN 0x08 /* Regulator is shut down in stop mode. Only the RSTb pin or power cycle can reset the device. */
1213
1214 /*------------------------------------------------------------------------------ */
1215 /* CLKSEL Enums (Clock Select @ 0xA9) */
1216 /*------------------------------------------------------------------------------ */
1217 #define CLKSL__FMASK 0x03 /* Clock Source Select */
1218 #define CLKSL__SHIFT 0x00 /* Clock Source Select */
1219 #define CLKSL__HFOSC 0x00 /* Clock derived from the Internal High-Frequency Oscillator. */
1220 #define CLKSL__EXTOSC 0x01 /* Clock derived from the External CMOS clock circuit. */
1221 #define CLKSL__LFOSC 0x02 /* Clock derived from the Internal Low-Frequency Oscillator. */
1222
1223 #define CLKDIV__FMASK 0x70 /* Clock Source Divider */
1224 #define CLKDIV__SHIFT 0x04 /* Clock Source Divider */
1225 #define CLKDIV__SYSCLK_DIV_1 0x00 /* SYSCLK is equal to selected clock source divided by 1. */
1226 #define CLKDIV__SYSCLK_DIV_2 0x10 /* SYSCLK is equal to selected clock source divided by 2. */
1227 #define CLKDIV__SYSCLK_DIV_4 0x20 /* SYSCLK is equal to selected clock source divided by 4. */
1228 #define CLKDIV__SYSCLK_DIV_8 0x30 /* SYSCLK is equal to selected clock source divided by 8. */
1229 #define CLKDIV__SYSCLK_DIV_16 0x40 /* SYSCLK is equal to selected clock source divided by 16. */
1230 #define CLKDIV__SYSCLK_DIV_32 0x50 /* SYSCLK is equal to selected clock source divided by 32. */
1231 #define CLKDIV__SYSCLK_DIV_64 0x60 /* SYSCLK is equal to selected clock source divided by 64. */
1232 #define CLKDIV__SYSCLK_DIV_128 0x70 /* SYSCLK is equal to selected clock source divided by 128. */
1233
1234 /*------------------------------------------------------------------------------ */
1235 /* TMR2CN0 Enums (Timer 2 Control 0 @ 0xC8) */
1236 /*------------------------------------------------------------------------------ */
1237 #define T2XCLK__BMASK 0x01 /* Timer 2 External Clock Select */
1238 #define T2XCLK__SHIFT 0x00 /* Timer 2 External Clock Select */
1239 #define T2XCLK__SYSCLK_DIV_12 0x00 /* Timer 2 clock is the system clock divided by 12. */
1240 #define T2XCLK__EXTOSC_DIV_8 0x01 /* Timer 2 clock is the external oscillator divided by 8 (synchronized with SYSCLK). */
1241
1242 #define TR2__BMASK 0x04 /* Timer 2 Run Control */
1243 #define TR2__SHIFT 0x02 /* Timer 2 Run Control */
1244 #define TR2__STOP 0x00 /* Stop Timer 2. */
1245 #define TR2__RUN 0x04 /* Start Timer 2 running. */
1246
1247 #define T2SPLIT__BMASK 0x08 /* Timer 2 Split Mode Enable */
1248 #define T2SPLIT__SHIFT 0x03 /* Timer 2 Split Mode Enable */
1249 #define T2SPLIT__16_BIT_RELOAD 0x00 /* Timer 2 operates in 16-bit auto-reload mode. */
1250 #define T2SPLIT__8_BIT_RELOAD 0x08 /* Timer 2 operates as two 8-bit auto-reload timers. */
1251
1252 #define TF2CEN__BMASK 0x10 /* Timer 2 Capture Enable */
1253 #define TF2CEN__SHIFT 0x04 /* Timer 2 Capture Enable */
1254 #define TF2CEN__DISABLED 0x00 /* Disable capture mode. */
1255 #define TF2CEN__ENABLED 0x10 /* Enable capture mode. */
1256
1257 #define TF2LEN__BMASK 0x20 /* Timer 2 Low Byte Interrupt Enable */
1258 #define TF2LEN__SHIFT 0x05 /* Timer 2 Low Byte Interrupt Enable */
1259 #define TF2LEN__DISABLED 0x00 /* Disable low byte interrupts. */
1260 #define TF2LEN__ENABLED 0x20 /* Enable low byte interrupts. */
1261
1262 #define TF2L__BMASK 0x40 /* Timer 2 Low Byte Overflow Flag */
1263 #define TF2L__SHIFT 0x06 /* Timer 2 Low Byte Overflow Flag */
1264 #define TF2L__NOT_SET 0x00 /* Timer 2 low byte did not overflow. */
1265 #define TF2L__SET 0x40 /* Timer 2 low byte overflowed. */
1266
1267 #define TF2H__BMASK 0x80 /* Timer 2 High Byte Overflow Flag */
1268 #define TF2H__SHIFT 0x07 /* Timer 2 High Byte Overflow Flag */
1269 #define TF2H__NOT_SET 0x00 /* Timer 2 8-bit high byte or 16-bit value did not overflow. */
1270 #define TF2H__SET 0x80 /* Timer 2 8-bit high byte or 16-bit value overflowed. */
1271
1272 /*------------------------------------------------------------------------------ */
1273 /* TMR3CN0 Enums (Timer 3 Control 0 @ 0x91) */
1274 /*------------------------------------------------------------------------------ */
1275 #define T3XCLK__BMASK 0x01 /* Timer 3 External Clock Select */
1276 #define T3XCLK__SHIFT 0x00 /* Timer 3 External Clock Select */
1277 #define T3XCLK__SYSCLK_DIV_12 0x00 /* Timer 3 clock is the system clock divided by 12. */
1278 #define T3XCLK__EXTOSC_DIV_8 0x01 /* Timer 3 clock is the external oscillator divided by 8 (synchronized with SYSCLK). */
1279
1280 #define TR3__BMASK 0x04 /* Timer 3 Run Control */
1281 #define TR3__SHIFT 0x02 /* Timer 3 Run Control */
1282 #define TR3__STOP 0x00 /* Stop Timer 3. */
1283 #define TR3__RUN 0x04 /* Start Timer 3 running. */
1284
1285 #define T3SPLIT__BMASK 0x08 /* Timer 3 Split Mode Enable */
1286 #define T3SPLIT__SHIFT 0x03 /* Timer 3 Split Mode Enable */
1287 #define T3SPLIT__16_BIT_RELOAD 0x00 /* Timer 3 operates in 16-bit auto-reload mode. */
1288 #define T3SPLIT__8_BIT_RELOAD 0x08 /* Timer 3 operates as two 8-bit auto-reload timers. */
1289
1290 #define TF3CEN__BMASK 0x10 /* Timer 3 Capture Enable */
1291 #define TF3CEN__SHIFT 0x04 /* Timer 3 Capture Enable */
1292 #define TF3CEN__DISABLED 0x00 /* Disable capture mode. */
1293 #define TF3CEN__ENABLED 0x10 /* Enable capture mode. */
1294
1295 #define TF3LEN__BMASK 0x20 /* Timer 3 Low Byte Interrupt Enable */
1296 #define TF3LEN__SHIFT 0x05 /* Timer 3 Low Byte Interrupt Enable */
1297 #define TF3LEN__DISABLED 0x00 /* Disable low byte interrupts. */
1298 #define TF3LEN__ENABLED 0x20 /* Enable low byte interrupts. */
1299
1300 #define TF3L__BMASK 0x40 /* Timer 3 Low Byte Overflow Flag */
1301 #define TF3L__SHIFT 0x06 /* Timer 3 Low Byte Overflow Flag */
1302 #define TF3L__NOT_SET 0x00 /* Timer 3 low byte did not overflow. */
1303 #define TF3L__SET 0x40 /* Timer 3 low byte overflowed. */
1304
1305 #define TF3H__BMASK 0x80 /* Timer 3 High Byte Overflow Flag */
1306 #define TF3H__SHIFT 0x07 /* Timer 3 High Byte Overflow Flag */
1307 #define TF3H__NOT_SET 0x00 /* Timer 3 8-bit high byte or 16-bit value did not overflow. */
1308 #define TF3H__SET 0x80 /* Timer 3 8-bit high byte or 16-bit value overflowed. */
1309
1310 /*------------------------------------------------------------------------------ */
1311 /* PCA0CPM0 Enums (PCA Channel 0 Capture/Compare Mode @ 0xDA) */
1312 /*------------------------------------------------------------------------------ */
1313 #define ECCF__BMASK 0x01 /* Channel 0 Capture/Compare Flag Interrupt Enable */
1314 #define ECCF__SHIFT 0x00 /* Channel 0 Capture/Compare Flag Interrupt Enable */
1315 #define ECCF__DISABLED 0x00 /* Disable CCF0 interrupts. */
1316 #define ECCF__ENABLED 0x01 /* Enable a Capture/Compare Flag interrupt request when CCF0 is set. */
1317
1318 #define PWM__BMASK 0x02 /* Channel 0 Pulse Width Modulation Mode Enable */
1319 #define PWM__SHIFT 0x01 /* Channel 0 Pulse Width Modulation Mode Enable */
1320 #define PWM__DISABLED 0x00 /* Disable PWM function. */
1321 #define PWM__ENABLED 0x02 /* Enable PWM function. */
1322
1323 #define TOG__BMASK 0x04 /* Channel 0 Toggle Function Enable */
1324 #define TOG__SHIFT 0x02 /* Channel 0 Toggle Function Enable */
1325 #define TOG__DISABLED 0x00 /* Disable toggle function. */
1326 #define TOG__ENABLED 0x04 /* Enable toggle function. */
1327
1328 #define MAT__BMASK 0x08 /* Channel 0 Match Function Enable */
1329 #define MAT__SHIFT 0x03 /* Channel 0 Match Function Enable */
1330 #define MAT__DISABLED 0x00 /* Disable match function. */
1331 #define MAT__ENABLED 0x08 /* Enable match function. */
1332
1333 #define CAPN__BMASK 0x10 /* Channel 0 Capture Negative Function Enable */
1334 #define CAPN__SHIFT 0x04 /* Channel 0 Capture Negative Function Enable */
1335 #define CAPN__DISABLED 0x00 /* Disable negative edge capture. */
1336 #define CAPN__ENABLED 0x10 /* Enable negative edge capture. */
1337
1338 #define CAPP__BMASK 0x20 /* Channel 0 Capture Positive Function Enable */
1339 #define CAPP__SHIFT 0x05 /* Channel 0 Capture Positive Function Enable */
1340 #define CAPP__DISABLED 0x00 /* Disable positive edge capture. */
1341 #define CAPP__ENABLED 0x20 /* Enable positive edge capture. */
1342
1343 #define ECOM__BMASK 0x40 /* Channel 0 Comparator Function Enable */
1344 #define ECOM__SHIFT 0x06 /* Channel 0 Comparator Function Enable */
1345 #define ECOM__DISABLED 0x00 /* Disable comparator function. */
1346 #define ECOM__ENABLED 0x40 /* Enable comparator function. */
1347
1348 #define PWM16__BMASK 0x80 /* Channel 0 16-bit Pulse Width Modulation Enable */
1349 #define PWM16__SHIFT 0x07 /* Channel 0 16-bit Pulse Width Modulation Enable */
1350 #define PWM16__8_BIT 0x00 /* 8 to 11-bit PWM selected. */
1351 #define PWM16__16_BIT 0x80 /* 16-bit PWM selected. */
1352
1353 /*------------------------------------------------------------------------------ */
1354 /* PCA0CPM1 Enums (PCA Channel 1 Capture/Compare Mode @ 0xDB) */
1355 /*------------------------------------------------------------------------------ */
1356 #define ECCF__BMASK 0x01 /* Channel 1 Capture/Compare Flag Interrupt Enable */
1357 #define ECCF__SHIFT 0x00 /* Channel 1 Capture/Compare Flag Interrupt Enable */
1358 #define ECCF__DISABLED 0x00 /* Disable CCF1 interrupts. */
1359 #define ECCF__ENABLED 0x01 /* Enable a Capture/Compare Flag interrupt request when CCF1 is set. */
1360
1361 #define PWM__BMASK 0x02 /* Channel 1 Pulse Width Modulation Mode Enable */
1362 #define PWM__SHIFT 0x01 /* Channel 1 Pulse Width Modulation Mode Enable */
1363 #define PWM__DISABLED 0x00 /* Disable PWM function. */
1364 #define PWM__ENABLED 0x02 /* Enable PWM function. */
1365
1366 #define TOG__BMASK 0x04 /* Channel 1 Toggle Function Enable */
1367 #define TOG__SHIFT 0x02 /* Channel 1 Toggle Function Enable */
1368 #define TOG__DISABLED 0x00 /* Disable toggle function. */
1369 #define TOG__ENABLED 0x04 /* Enable toggle function. */
1370
1371 #define MAT__BMASK 0x08 /* Channel 1 Match Function Enable */
1372 #define MAT__SHIFT 0x03 /* Channel 1 Match Function Enable */
1373 #define MAT__DISABLED 0x00 /* Disable match function. */
1374 #define MAT__ENABLED 0x08 /* Enable match function. */
1375
1376 #define CAPN__BMASK 0x10 /* Channel 1 Capture Negative Function Enable */
1377 #define CAPN__SHIFT 0x04 /* Channel 1 Capture Negative Function Enable */
1378 #define CAPN__DISABLED 0x00 /* Disable negative edge capture. */
1379 #define CAPN__ENABLED 0x10 /* Enable negative edge capture. */
1380
1381 #define CAPP__BMASK 0x20 /* Channel 1 Capture Positive Function Enable */
1382 #define CAPP__SHIFT 0x05 /* Channel 1 Capture Positive Function Enable */
1383 #define CAPP__DISABLED 0x00 /* Disable positive edge capture. */
1384 #define CAPP__ENABLED 0x20 /* Enable positive edge capture. */
1385
1386 #define ECOM__BMASK 0x40 /* Channel 1 Comparator Function Enable */
1387 #define ECOM__SHIFT 0x06 /* Channel 1 Comparator Function Enable */
1388 #define ECOM__DISABLED 0x00 /* Disable comparator function. */
1389 #define ECOM__ENABLED 0x40 /* Enable comparator function. */
1390
1391 #define PWM16__BMASK 0x80 /* Channel 1 16-bit Pulse Width Modulation Enable */
1392 #define PWM16__SHIFT 0x07 /* Channel 1 16-bit Pulse Width Modulation Enable */
1393 #define PWM16__8_BIT 0x00 /* 8 to 11-bit PWM selected. */
1394 #define PWM16__16_BIT 0x80 /* 16-bit PWM selected. */
1395
1396 /*------------------------------------------------------------------------------ */
1397 /* PCA0CPM2 Enums (PCA Channel 2 Capture/Compare Mode @ 0xDC) */
1398 /*------------------------------------------------------------------------------ */
1399 #define ECCF__BMASK 0x01 /* Channel 2 Capture/Compare Flag Interrupt Enable */
1400 #define ECCF__SHIFT 0x00 /* Channel 2 Capture/Compare Flag Interrupt Enable */
1401 #define ECCF__DISABLED 0x00 /* Disable CCF2 interrupts. */
1402 #define ECCF__ENABLED 0x01 /* Enable a Capture/Compare Flag interrupt request */
1403 /* when CCF2 is set. */
1404
1405 #define PWM__BMASK 0x02 /* Channel 2 Pulse Width Modulation Mode Enable */
1406 #define PWM__SHIFT 0x01 /* Channel 2 Pulse Width Modulation Mode Enable */
1407 #define PWM__DISABLED 0x00 /* Disable PWM function. */
1408 #define PWM__ENABLED 0x02 /* Enable PWM function. */
1409
1410 #define TOG__BMASK 0x04 /* Channel 2 Toggle Function Enable */
1411 #define TOG__SHIFT 0x02 /* Channel 2 Toggle Function Enable */
1412 #define TOG__DISABLED 0x00 /* Disable toggle function. */
1413 #define TOG__ENABLED 0x04 /* Enable toggle function. */
1414
1415 #define MAT__BMASK 0x08 /* Channel 2 Match Function Enable */
1416 #define MAT__SHIFT 0x03 /* Channel 2 Match Function Enable */
1417 #define MAT__DISABLED 0x00 /* Disable match function. */
1418 #define MAT__ENABLED 0x08 /* Enable match function. */
1419
1420 #define CAPN__BMASK 0x10 /* Channel 2 Capture Negative Function Enable */
1421 #define CAPN__SHIFT 0x04 /* Channel 2 Capture Negative Function Enable */
1422 #define CAPN__DISABLED 0x00 /* Disable negative edge capture. */
1423 #define CAPN__ENABLED 0x10 /* Enable negative edge capture. */
1424
1425 #define CAPP__BMASK 0x20 /* Channel 2 Capture Positive Function Enable */
1426 #define CAPP__SHIFT 0x05 /* Channel 2 Capture Positive Function Enable */
1427 #define CAPP__DISABLED 0x00 /* Disable positive edge capture. */
1428 #define CAPP__ENABLED 0x20 /* Enable positive edge capture. */
1429
1430 #define ECOM__BMASK 0x40 /* Channel 2 Comparator Function Enable */
1431 #define ECOM__SHIFT 0x06 /* Channel 2 Comparator Function Enable */
1432 #define ECOM__DISABLED 0x00 /* Disable comparator function. */
1433 #define ECOM__ENABLED 0x40 /* Enable comparator function. */
1434
1435 #define PWM16__BMASK 0x80 /* Channel 2 16-bit Pulse Width Modulation Enable */
1436 #define PWM16__SHIFT 0x07 /* Channel 2 16-bit Pulse Width Modulation Enable */
1437 #define PWM16__8_BIT 0x00 /* 8 to 11-bit PWM selected. */
1438 #define PWM16__16_BIT 0x80 /* 16-bit PWM selected. */
1439
1440 /*------------------------------------------------------------------------------ */
1441 /* PCA0CENT Enums (PCA Center Alignment Enable @ 0x9E) */
1442 /*------------------------------------------------------------------------------ */
1443 #define CEX0CEN__BMASK 0x01 /* CEX0 Center Alignment Enable */
1444 #define CEX0CEN__SHIFT 0x00 /* CEX0 Center Alignment Enable */
1445 #define CEX0CEN__EDGE 0x00 /* Edge-aligned. */
1446 #define CEX0CEN__CENTER 0x01 /* Center-aligned. */
1447
1448 #define CEX1CEN__BMASK 0x02 /* CEX1 Center Alignment Enable */
1449 #define CEX1CEN__SHIFT 0x01 /* CEX1 Center Alignment Enable */
1450 #define CEX1CEN__EDGE 0x00 /* Edge-aligned. */
1451 #define CEX1CEN__CENTER 0x02 /* Center-aligned. */
1452
1453 #define CEX2CEN__BMASK 0x04 /* CEX2 Center Alignment Enable */
1454 #define CEX2CEN__SHIFT 0x02 /* CEX2 Center Alignment Enable */
1455 #define CEX2CEN__EDGE 0x00 /* Edge-aligned. */
1456 #define CEX2CEN__CENTER 0x04 /* Center-aligned. */
1457
1458 /*------------------------------------------------------------------------------ */
1459 /* PCA0CLR Enums (PCA Comparator Clear Control @ 0x9C) */
1460 /*------------------------------------------------------------------------------ */
1461 #define CPCE0__BMASK 0x01 /* Comparator Clear Enable for CEX0 */
1462 #define CPCE0__SHIFT 0x00 /* Comparator Clear Enable for CEX0 */
1463 #define CPCE0__DISABLED 0x00 /* Disable the comparator clear function on PCA channel 0. */
1464 #define CPCE0__ENABLED 0x01 /* Enable the comparator clear function on PCA channel 0. */
1465
1466 #define CPCE1__BMASK 0x02 /* Comparator Clear Enable for CEX1 */
1467 #define CPCE1__SHIFT 0x01 /* Comparator Clear Enable for CEX1 */
1468 #define CPCE1__DISABLED 0x00 /* Disable the comparator clear function on PCA channel 1. */
1469 #define CPCE1__ENABLED 0x02 /* Enable the comparator clear function on PCA channel 1. */
1470
1471 #define CPCE2__BMASK 0x04 /* Comparator Clear Enable for CEX2 */
1472 #define CPCE2__SHIFT 0x02 /* Comparator Clear Enable for CEX2 */
1473 #define CPCE2__DISABLED 0x00 /* Disable the comparator clear function on PCA channel 2. */
1474 #define CPCE2__ENABLED 0x04 /* Enable the comparator clear function on PCA channel 2. */
1475
1476 #define CPCPOL__BMASK 0x80 /* Comparator Clear Polarity */
1477 #define CPCPOL__SHIFT 0x07 /* Comparator Clear Polarity */
1478 #define CPCPOL__LOW 0x00 /* PCA channel(s) will be cleared when comparator result goes logic low. */
1479 #define CPCPOL__HIGH 0x80 /* PCA channel(s) will be cleared when comparator result goes logic high. */
1480
1481 /*------------------------------------------------------------------------------ */
1482 /* PCA0CN0 Enums (PCA Control @ 0xD8) */
1483 /*------------------------------------------------------------------------------ */
1484 #define CCF0__BMASK 0x01 /* PCA Module 0 Capture/Compare Flag */
1485 #define CCF0__SHIFT 0x00 /* PCA Module 0 Capture/Compare Flag */
1486 #define CCF0__NOT_SET 0x00 /* A match or capture did not occur on channel 0. */
1487 #define CCF0__SET 0x01 /* A match or capture occurred on channel 0. */
1488
1489 #define CCF1__BMASK 0x02 /* PCA Module 1 Capture/Compare Flag */
1490 #define CCF1__SHIFT 0x01 /* PCA Module 1 Capture/Compare Flag */
1491 #define CCF1__NOT_SET 0x00 /* A match or capture did not occur on channel 1. */
1492 #define CCF1__SET 0x02 /* A match or capture occurred on channel 1. */
1493
1494 #define CCF2__BMASK 0x04 /* PCA Module 2 Capture/Compare Flag */
1495 #define CCF2__SHIFT 0x02 /* PCA Module 2 Capture/Compare Flag */
1496 #define CCF2__NOT_SET 0x00 /* A match or capture did not occur on channel 2. */
1497 #define CCF2__SET 0x04 /* A match or capture occurred on channel 2. */
1498
1499 #define CR__BMASK 0x40 /* PCA Counter/Timer Run Control */
1500 #define CR__SHIFT 0x06 /* PCA Counter/Timer Run Control */
1501 #define CR__STOP 0x00 /* Stop the PCA Counter/Timer. */
1502 #define CR__RUN 0x40 /* Start the PCA Counter/Timer running. */
1503
1504 #define CF__BMASK 0x80 /* PCA Counter/Timer Overflow Flag */
1505 #define CF__SHIFT 0x07 /* PCA Counter/Timer Overflow Flag */
1506 #define CF__NOT_SET 0x00 /* The PCA counter/timer did not overflow. */
1507 #define CF__SET 0x80 /* The PCA counter/timer overflowed. */
1508
1509 /*------------------------------------------------------------------------------ */
1510 /* PCA0MD Enums (PCA Mode @ 0xD9) */
1511 /*------------------------------------------------------------------------------ */
1512 #define ECF__BMASK 0x01 /* PCA Counter/Timer Overflow Interrupt Enable */
1513 #define ECF__SHIFT 0x00 /* PCA Counter/Timer Overflow Interrupt Enable */
1514 #define ECF__OVF_INT_DISABLED 0x00 /* Disable the CF interrupt. */
1515 #define ECF__OVF_INT_ENABLED 0x01 /* Enable a PCA Counter/Timer Overflow interrupt request when CF is set. */
1516
1517 #define CPS__FMASK 0x0E /* PCA Counter/Timer Pulse Select */
1518 #define CPS__SHIFT 0x01 /* PCA Counter/Timer Pulse Select */
1519 #define CPS__SYSCLK_DIV_12 0x00 /* System clock divided by 12. */
1520 #define CPS__SYSCLK_DIV_4 0x02 /* System clock divided by 4. */
1521 #define CPS__T0_OVERFLOW 0x04 /* Timer 0 overflow. */
1522 #define CPS__ECI 0x06 /* High-to-low transitions on ECI (max rate = system clock divided by 4). */
1523 #define CPS__SYSCLK 0x08 /* System clock. */
1524 #define CPS__EXTOSC_DIV_8 0x0A /* External clock divided by 8 (synchronized with the system clock). */
1525 #define CPS__LFOSC_DIV_8 0x0C /* Low frequency oscillator divided by 8. */
1526
1527 #define CIDL__BMASK 0x80 /* PCA Counter/Timer Idle Control */
1528 #define CIDL__SHIFT 0x07 /* PCA Counter/Timer Idle Control */
1529 #define CIDL__NORMAL 0x00 /* PCA continues to function normally while the system controller is in Idle Mode. */
1530 #define CIDL__SUSPEND 0x80 /* PCA operation is suspended while the system controller is in Idle Mode. */
1531
1532 /*------------------------------------------------------------------------------ */
1533 /* PCA0POL Enums (PCA Output Polarity @ 0x96) */
1534 /*------------------------------------------------------------------------------ */
1535 #define CEX0POL__BMASK 0x01 /* CEX0 Output Polarity */
1536 #define CEX0POL__SHIFT 0x00 /* CEX0 Output Polarity */
1537 #define CEX0POL__DEFAULT 0x00 /* Use default polarity. */
1538 #define CEX0POL__INVERT 0x01 /* Invert polarity. */
1539
1540 #define CEX1POL__BMASK 0x02 /* CEX1 Output Polarity */
1541 #define CEX1POL__SHIFT 0x01 /* CEX1 Output Polarity */
1542 #define CEX1POL__DEFAULT 0x00 /* Use default polarity. */
1543 #define CEX1POL__INVERT 0x02 /* Invert polarity. */
1544
1545 #define CEX2POL__BMASK 0x04 /* CEX2 Output Polarity */
1546 #define CEX2POL__SHIFT 0x02 /* CEX2 Output Polarity */
1547 #define CEX2POL__DEFAULT 0x00 /* Use default polarity. */
1548 #define CEX2POL__INVERT 0x04 /* Invert polarity. */
1549
1550 /*------------------------------------------------------------------------------ */
1551 /* PCA0PWM Enums (PCA PWM Configuration @ 0xF7) */
1552 /*------------------------------------------------------------------------------ */
1553 #define CLSEL__FMASK 0x07 /* Cycle Length Select */
1554 #define CLSEL__SHIFT 0x00 /* Cycle Length Select */
1555 #define CLSEL__8_BITS 0x00 /* 8 bits. */
1556 #define CLSEL__9_BITS 0x01 /* 9 bits. */
1557 #define CLSEL__10_BITS 0x02 /* 10 bits. */
1558 #define CLSEL__11_BITS 0x03 /* 11 bits. */
1559
1560 #define COVF__BMASK 0x20 /* Cycle Overflow Flag */
1561 #define COVF__SHIFT 0x05 /* Cycle Overflow Flag */
1562 #define COVF__NO_OVERFLOW 0x00 /* No overflow has occurred since the last time this bit was cleared. */
1563 #define COVF__OVERFLOW 0x20 /* An overflow has occurred since the last time this bit was cleared. */
1564
1565 #define ECOV__BMASK 0x40 /* Cycle Overflow Interrupt Enable */
1566 #define ECOV__SHIFT 0x06 /* Cycle Overflow Interrupt Enable */
1567 #define ECOV__COVF_MASK_DISABLED 0x00 /* COVF will not generate PCA interrupts. */
1568 #define ECOV__COVF_MASK_ENABLED 0x40 /* A PCA interrupt will be generated when COVF is set. */
1569
1570 #define ARSEL__BMASK 0x80 /* Auto-Reload Register Select */
1571 #define ARSEL__SHIFT 0x07 /* Auto-Reload Register Select */
1572 #define ARSEL__CAPTURE_COMPARE 0x00 /* Read/Write Capture/Compare Registers at PCA0CPHn and PCA0CPLn. */
1573 #define ARSEL__AUTORELOAD 0x80 /* Read/Write Auto-Reload Registers at PCA0CPHn and PCA0CPLn. */
1574
1575 /*------------------------------------------------------------------------------ */
1576 /* SPI0CFG Enums (SPI0 Configuration @ 0xA1) */
1577 /*------------------------------------------------------------------------------ */
1578 #define RXBMT__BMASK 0x01 /* Receive Buffer Empty */
1579 #define RXBMT__SHIFT 0x00 /* Receive Buffer Empty */
1580 #define RXBMT__NOT_SET 0x00 /* New data is available in the receive buffer (Slave mode). */
1581 #define RXBMT__SET 0x01 /* No new data in the receive buffer (Slave mode). */
1582
1583 #define SRMT__BMASK 0x02 /* Shift Register Empty */
1584 #define SRMT__SHIFT 0x01 /* Shift Register Empty */
1585 #define SRMT__NOT_SET 0x00 /* The shift register is not empty. */
1586 #define SRMT__SET 0x02 /* The shift register is empty. */
1587
1588 #define NSSIN__BMASK 0x04 /* NSS Instantaneous Pin Input */
1589 #define NSSIN__SHIFT 0x02 /* NSS Instantaneous Pin Input */
1590 #define NSSIN__LOW 0x00 /* The NSS pin is low. */
1591 #define NSSIN__HIGH 0x04 /* The NSS pin is high. */
1592
1593 #define SLVSEL__BMASK 0x08 /* Slave Selected Flag */
1594 #define SLVSEL__SHIFT 0x03 /* Slave Selected Flag */
1595 #define SLVSEL__NOT_SELECTED 0x00 /* The Slave is not selected (NSS is high). */
1596 #define SLVSEL__SELECTED 0x08 /* The Slave is selected (NSS is low). */
1597
1598 #define CKPOL__BMASK 0x10 /* SPI0 Clock Polarity */
1599 #define CKPOL__SHIFT 0x04 /* SPI0 Clock Polarity */
1600 #define CKPOL__IDLE_LOW 0x00 /* SCK line low in idle state. */
1601 #define CKPOL__IDLE_HIGH 0x10 /* SCK line high in idle state. */
1602
1603 #define CKPHA__BMASK 0x20 /* SPI0 Clock Phase */
1604 #define CKPHA__SHIFT 0x05 /* SPI0 Clock Phase */
1605 #define CKPHA__DATA_CENTERED_FIRST 0x00 /* Data centered on first edge of SCK period. */
1606 #define CKPHA__DATA_CENTERED_SECOND 0x20 /* Data centered on second edge of SCK period. */
1607
1608 #define MSTEN__BMASK 0x40 /* Master Mode Enable */
1609 #define MSTEN__SHIFT 0x06 /* Master Mode Enable */
1610 #define MSTEN__MASTER_DISABLED 0x00 /* Disable master mode. Operate in slave mode. */
1611 #define MSTEN__MASTER_ENABLED 0x40 /* Enable master mode. Operate as a master. */
1612
1613 #define SPIBSY__BMASK 0x80 /* SPI Busy */
1614 #define SPIBSY__SHIFT 0x07 /* SPI Busy */
1615 #define SPIBSY__NOT_SET 0x00 /* A SPI transfer is not in progress. */
1616 #define SPIBSY__SET 0x80 /* A SPI transfer is in progress. */
1617
1618 /*------------------------------------------------------------------------------ */
1619 /* SPI0CN0 Enums (SPI0 Control @ 0xF8) */
1620 /*------------------------------------------------------------------------------ */
1621 #define SPIEN__BMASK 0x01 /* SPI0 Enable */
1622 #define SPIEN__SHIFT 0x00 /* SPI0 Enable */
1623 #define SPIEN__DISABLED 0x00 /* Disable the SPI module. */
1624 #define SPIEN__ENABLED 0x01 /* Enable the SPI module. */
1625
1626 #define TXBMT__BMASK 0x02 /* Transmit Buffer Empty */
1627 #define TXBMT__SHIFT 0x01 /* Transmit Buffer Empty */
1628 #define TXBMT__NOT_SET 0x00 /* The transmit buffer is not empty. */
1629 #define TXBMT__SET 0x02 /* The transmit buffer is empty. */
1630
1631 #define NSSMD__FMASK 0x0C /* Slave Select Mode */
1632 #define NSSMD__SHIFT 0x02 /* Slave Select Mode */
1633 #define NSSMD__3_WIRE 0x00 /* 3-Wire Slave or 3-Wire Master Mode. NSS signal is not routed to a port pin. */
1634 #define NSSMD__4_WIRE_SLAVE 0x04 /* 4-Wire Slave or Multi-Master Mode. NSS is an input to the device. */
1635 #define NSSMD__4_WIRE_MASTER_NSS_LOW 0x08 /* 4-Wire Single-Master Mode. NSS is an output and logic low. */
1636 #define NSSMD__4_WIRE_MASTER_NSS_HIGH 0x0C /* 4-Wire Single-Master Mode. NSS is an output and logic high. */
1637
1638 #define RXOVRN__BMASK 0x10 /* Receive Overrun Flag */
1639 #define RXOVRN__SHIFT 0x04 /* Receive Overrun Flag */
1640 #define RXOVRN__NOT_SET 0x00 /* A receive overrun did not occur. */
1641 #define RXOVRN__SET 0x10 /* A receive overrun occurred. */
1642
1643 #define MODF__BMASK 0x20 /* Mode Fault Flag */
1644 #define MODF__SHIFT 0x05 /* Mode Fault Flag */
1645 #define MODF__NOT_SET 0x00 /* A master collision did not occur. */
1646 #define MODF__SET 0x20 /* A master collision occurred. */
1647
1648 #define WCOL__BMASK 0x40 /* Write Collision Flag */
1649 #define WCOL__SHIFT 0x06 /* Write Collision Flag */
1650 #define WCOL__NOT_SET 0x00 /* A write collision did not occur. */
1651 #define WCOL__SET 0x40 /* A write collision occurred. */
1652
1653 #define SPIF__BMASK 0x80 /* SPI0 Interrupt Flag */
1654 #define SPIF__SHIFT 0x07 /* SPI0 Interrupt Flag */
1655 #define SPIF__NOT_SET 0x00 /* A data transfer has not completed since the last time SPIF was cleared. */
1656 #define SPIF__SET 0x80 /* A data transfer completed. */
1657
1658 /*------------------------------------------------------------------------------ */
1659 /* EIE1 Enums (Extended Interrupt Enable 1 @ 0xE6) */
1660 /*------------------------------------------------------------------------------ */
1661 #define ESMB0__BMASK 0x01 /* SMBus (SMB0) Interrupt Enable */
1662 #define ESMB0__SHIFT 0x00 /* SMBus (SMB0) Interrupt Enable */
1663 #define ESMB0__DISABLED 0x00 /* Disable all SMB0 interrupts. */
1664 #define ESMB0__ENABLED 0x01 /* Enable interrupt requests generated by SMB0. */
1665
1666 #define EMAT__BMASK 0x02 /* Port Match Interrupts Enable */
1667 #define EMAT__SHIFT 0x01 /* Port Match Interrupts Enable */
1668 #define EMAT__DISABLED 0x00 /* Disable all Port Match interrupts. */
1669 #define EMAT__ENABLED 0x02 /* Enable interrupt requests generated by a Port Match. */
1670
1671 #define EWADC0__BMASK 0x04 /* ADC0 Window Comparison Interrupt Enable */
1672 #define EWADC0__SHIFT 0x02 /* ADC0 Window Comparison Interrupt Enable */
1673 #define EWADC0__DISABLED 0x00 /* Disable ADC0 Window Comparison interrupt. */
1674 #define EWADC0__ENABLED 0x04 /* Enable interrupt requests generated by ADC0 Window Compare flag (ADWINT). */
1675
1676 #define EADC0__BMASK 0x08 /* ADC0 Conversion Complete Interrupt Enable */
1677 #define EADC0__SHIFT 0x03 /* ADC0 Conversion Complete Interrupt Enable */
1678 #define EADC0__DISABLED 0x00 /* Disable ADC0 Conversion Complete interrupt. */
1679 #define EADC0__ENABLED 0x08 /* Enable interrupt requests generated by the ADINT flag. */
1680
1681 #define EPCA0__BMASK 0x10 /* Programmable Counter Array (PCA0) Interrupt Enable */
1682 #define EPCA0__SHIFT 0x04 /* Programmable Counter Array (PCA0) Interrupt Enable */
1683 #define EPCA0__DISABLED 0x00 /* Disable all PCA0 interrupts. */
1684 #define EPCA0__ENABLED 0x10 /* Enable interrupt requests generated by PCA0. */
1685
1686 #define ECP0__BMASK 0x20 /* Comparator0 (CP0) Interrupt Enable */
1687 #define ECP0__SHIFT 0x05 /* Comparator0 (CP0) Interrupt Enable */
1688 #define ECP0__DISABLED 0x00 /* Disable CP0 interrupts. */
1689 #define ECP0__ENABLED 0x20 /* Enable interrupt requests generated by the comparator 0 CPRIF or CPFIF flags. */
1690
1691 #define ECP1__BMASK 0x40 /* Comparator1 (CP1) Interrupt Enable */
1692 #define ECP1__SHIFT 0x06 /* Comparator1 (CP1) Interrupt Enable */
1693 #define ECP1__DISABLED 0x00 /* Disable CP1 interrupts. */
1694 #define ECP1__ENABLED 0x40 /* Enable interrupt requests generated by the comparator 1 CPRIF or CPFIF flags. */
1695
1696 #define ET3__BMASK 0x80 /* Timer 3 Interrupt Enable */
1697 #define ET3__SHIFT 0x07 /* Timer 3 Interrupt Enable */
1698 #define ET3__DISABLED 0x00 /* Disable Timer 3 interrupts. */
1699 #define ET3__ENABLED 0x80 /* Enable interrupt requests generated by the TF3L or TF3H flags. */
1700
1701 /*------------------------------------------------------------------------------ */
1702 /* EIP1 Enums (Extended Interrupt Priority 1 @ 0xF3) */
1703 /*------------------------------------------------------------------------------ */
1704 #define PSMB0__BMASK 0x01 /* SMBus (SMB0) Interrupt Priority Control */
1705 #define PSMB0__SHIFT 0x00 /* SMBus (SMB0) Interrupt Priority Control */
1706 #define PSMB0__LOW 0x00 /* SMB0 interrupt set to low priority level. */
1707 #define PSMB0__HIGH 0x01 /* SMB0 interrupt set to high priority level. */
1708
1709 #define PMAT__BMASK 0x02 /* Port Match Interrupt Priority Control */
1710 #define PMAT__SHIFT 0x01 /* Port Match Interrupt Priority Control */
1711 #define PMAT__LOW 0x00 /* Port Match interrupt set to low priority level. */
1712 #define PMAT__HIGH 0x02 /* Port Match interrupt set to high priority level. */
1713
1714 #define PWADC0__BMASK 0x04 /* ADC0 Window Comparator Interrupt Priority Control */
1715 #define PWADC0__SHIFT 0x02 /* ADC0 Window Comparator Interrupt Priority Control */
1716 #define PWADC0__LOW 0x00 /* ADC0 Window interrupt set to low priority level. */
1717 #define PWADC0__HIGH 0x04 /* ADC0 Window interrupt set to high priority level. */
1718
1719 #define PADC0__BMASK 0x08 /* ADC0 Conversion Complete Interrupt Priority Control */
1720 #define PADC0__SHIFT 0x03 /* ADC0 Conversion Complete Interrupt Priority Control */
1721 #define PADC0__LOW 0x00 /* ADC0 Conversion Complete interrupt set to low priority level. */
1722 #define PADC0__HIGH 0x08 /* ADC0 Conversion Complete interrupt set to high priority level. */
1723
1724 #define PPCA0__BMASK 0x10 /* Programmable Counter Array (PCA0) Interrupt Priority Control */
1725 #define PPCA0__SHIFT 0x04 /* Programmable Counter Array (PCA0) Interrupt Priority Control */
1726 #define PPCA0__LOW 0x00 /* PCA0 interrupt set to low priority level. */
1727 #define PPCA0__HIGH 0x10 /* PCA0 interrupt set to high priority level. */
1728
1729 #define PCP0__BMASK 0x20 /* Comparator0 (CP0) Interrupt Priority Control */
1730 #define PCP0__SHIFT 0x05 /* Comparator0 (CP0) Interrupt Priority Control */
1731 #define PCP0__LOW 0x00 /* CP0 interrupt set to low priority level. */
1732 #define PCP0__HIGH 0x20 /* CP0 interrupt set to high priority level. */
1733
1734 #define PCP1__BMASK 0x40 /* Comparator1 (CP1) Interrupt Priority Control */
1735 #define PCP1__SHIFT 0x06 /* Comparator1 (CP1) Interrupt Priority Control */
1736 #define PCP1__LOW 0x00 /* CP1 interrupt set to low priority level. */
1737 #define PCP1__HIGH 0x40 /* CP1 interrupt set to high priority level. */
1738
1739 #define PT3__BMASK 0x80 /* Timer 3 Interrupt Priority Control */
1740 #define PT3__SHIFT 0x07 /* Timer 3 Interrupt Priority Control */
1741 #define PT3__LOW 0x00 /* Timer 3 interrupts set to low priority level. */
1742 #define PT3__HIGH 0x80 /* Timer 3 interrupts set to high priority level. */
1743
1744 /*------------------------------------------------------------------------------ */
1745 /* IE Enums (Interrupt Enable @ 0xA8) */
1746 /*------------------------------------------------------------------------------ */
1747 #define EX0__BMASK 0x01 /* External Interrupt 0 Enable */
1748 #define EX0__SHIFT 0x00 /* External Interrupt 0 Enable */
1749 #define EX0__DISABLED 0x00 /* Disable external interrupt 0. */
1750 #define EX0__ENABLED 0x01 /* Enable interrupt requests generated by the INT0 input. */
1751
1752 #define ET0__BMASK 0x02 /* Timer 0 Interrupt Enable */
1753 #define ET0__SHIFT 0x01 /* Timer 0 Interrupt Enable */
1754 #define ET0__DISABLED 0x00 /* Disable all Timer 0 interrupt. */
1755 #define ET0__ENABLED 0x02 /* Enable interrupt requests generated by the TF0 flag. */
1756
1757 #define EX1__BMASK 0x04 /* External Interrupt 1 Enable */
1758 #define EX1__SHIFT 0x02 /* External Interrupt 1 Enable */
1759 #define EX1__DISABLED 0x00 /* Disable external interrupt 1. */
1760 #define EX1__ENABLED 0x04 /* Enable interrupt requests generated by the INT1 input. */
1761
1762 #define ET1__BMASK 0x08 /* Timer 1 Interrupt Enable */
1763 #define ET1__SHIFT 0x03 /* Timer 1 Interrupt Enable */
1764 #define ET1__DISABLED 0x00 /* Disable all Timer 1 interrupt. */
1765 #define ET1__ENABLED 0x08 /* Enable interrupt requests generated by the TF1 flag. */
1766
1767 #define ES0__BMASK 0x10 /* UART0 Interrupt Enable */
1768 #define ES0__SHIFT 0x04 /* UART0 Interrupt Enable */
1769 #define ES0__DISABLED 0x00 /* Disable UART0 interrupt. */
1770 #define ES0__ENABLED 0x10 /* Enable UART0 interrupt. */
1771
1772 #define ET2__BMASK 0x20 /* Timer 2 Interrupt Enable */
1773 #define ET2__SHIFT 0x05 /* Timer 2 Interrupt Enable */
1774 #define ET2__DISABLED 0x00 /* Disable Timer 2 interrupt. */
1775 #define ET2__ENABLED 0x20 /* Enable interrupt requests generated by the TF2L or TF2H flags. */
1776
1777 #define ESPI0__BMASK 0x40 /* SPI0 Interrupt Enable */
1778 #define ESPI0__SHIFT 0x06 /* SPI0 Interrupt Enable */
1779 #define ESPI0__DISABLED 0x00 /* Disable all SPI0 interrupts. */
1780 #define ESPI0__ENABLED 0x40 /* Enable interrupt requests generated by SPI0. */
1781
1782 #define EA__BMASK 0x80 /* All Interrupts Enable */
1783 #define EA__SHIFT 0x07 /* All Interrupts Enable */
1784 #define EA__DISABLED 0x00 /* Disable all interrupt sources. */
1785 #define EA__ENABLED 0x80 /* Enable each interrupt according to its individual mask setting. */
1786
1787 /*------------------------------------------------------------------------------ */
1788 /* SMB0ADM Enums (SMBus 0 Slave Address Mask @ 0xD6) */
1789 /*------------------------------------------------------------------------------ */
1790 #define EHACK__BMASK 0x01 /* Hardware Acknowledge Enable */
1791 #define EHACK__SHIFT 0x00 /* Hardware Acknowledge Enable */
1792 #define EHACK__ADR_ACK_MANUAL 0x00 /* Firmware must manually acknowledge all incoming address and data bytes. */
1793 #define EHACK__ADR_ACK_AUTOMATIC 0x01 /* Automatic slave address recognition and hardware acknowledge is enabled. */
1794
1795 #define SLVM__FMASK 0xFE /* SMBus Slave Address Mask */
1796 #define SLVM__SHIFT 0x01 /* SMBus Slave Address Mask */
1797
1798 /*------------------------------------------------------------------------------ */
1799 /* SMB0ADR Enums (SMBus 0 Slave Address @ 0xD7) */
1800 /*------------------------------------------------------------------------------ */
1801 #define GC__BMASK 0x01 /* General Call Address Enable */
1802 #define GC__SHIFT 0x00 /* General Call Address Enable */
1803 #define GC__IGNORED 0x00 /* General Call Address is ignored. */
1804 #define GC__RECOGNIZED 0x01 /* General Call Address is recognized. */
1805
1806 #define SLV__FMASK 0xFE /* SMBus Hardware Slave Address */
1807 #define SLV__SHIFT 0x01 /* SMBus Hardware Slave Address */
1808
1809 /*------------------------------------------------------------------------------ */
1810 /* SMB0CF Enums (SMBus 0 Configuration @ 0xC1) */
1811 /*------------------------------------------------------------------------------ */
1812 #define SMBCS__FMASK 0x03 /* SMBus Clock Source Selection */
1813 #define SMBCS__SHIFT 0x00 /* SMBus Clock Source Selection */
1814 #define SMBCS__TIMER0 0x00 /* Timer 0 Overflow. */
1815 #define SMBCS__TIMER1 0x01 /* Timer 1 Overflow. */
1816 #define SMBCS__TIMER2_HIGH 0x02 /* Timer 2 High Byte Overflow. */
1817 #define SMBCS__TIMER2_LOW 0x03 /* Timer 2 Low Byte Overflow. */
1818
1819 #define SMBFTE__BMASK 0x04 /* SMBus Free Timeout Detection Enable */
1820 #define SMBFTE__SHIFT 0x02 /* SMBus Free Timeout Detection Enable */
1821 #define SMBFTE__FREE_TO_DISABLED 0x00 /* Disable bus free timeouts. */
1822 #define SMBFTE__FREE_TO_ENABLED 0x04 /* Enable bus free timeouts. The bus the bus will be considered free if SCL and SDA remain high for more than 10 SMBus clock source periods. */
1823
1824 #define SMBTOE__BMASK 0x08 /* SMBus SCL Timeout Detection Enable */
1825 #define SMBTOE__SHIFT 0x03 /* SMBus SCL Timeout Detection Enable */
1826 #define SMBTOE__SCL_TO_DISABLED 0x00 /* Disable SCL low timeouts. */
1827 #define SMBTOE__SCL_TO_ENABLED 0x08 /* Enable SCL low timeouts. */
1828
1829 #define EXTHOLD__BMASK 0x10 /* SMBus Setup and Hold Time Extension Enable */
1830 #define EXTHOLD__SHIFT 0x04 /* SMBus Setup and Hold Time Extension Enable */
1831 #define EXTHOLD__DISABLED 0x00 /* Disable SDA extended setup and hold times. */
1832 #define EXTHOLD__ENABLED 0x10 /* Enable SDA extended setup and hold times. */
1833
1834 #define BUSY__BMASK 0x20 /* SMBus Busy Indicator */
1835 #define BUSY__SHIFT 0x05 /* SMBus Busy Indicator */
1836 #define BUSY__NOT_SET 0x00 /* The bus is not busy. */
1837 #define BUSY__SET 0x20 /* The bus is busy and a transfer is currently in progress. */
1838
1839 #define INH__BMASK 0x40 /* SMBus Slave Inhibit */
1840 #define INH__SHIFT 0x06 /* SMBus Slave Inhibit */
1841 #define INH__SLAVE_ENABLED 0x00 /* Slave states are enabled. */
1842 #define INH__SLAVE_DISABLED 0x40 /* Slave states are inhibited. */
1843
1844 #define ENSMB__BMASK 0x80 /* SMBus Enable */
1845 #define ENSMB__SHIFT 0x07 /* SMBus Enable */
1846 #define ENSMB__DISABLED 0x00 /* Disable the SMBus module. */
1847 #define ENSMB__ENABLED 0x80 /* Enable the SMBus module. */
1848
1849 /*------------------------------------------------------------------------------ */
1850 /* SMB0CN0 Enums (SMBus 0 Control @ 0xC0) */
1851 /*------------------------------------------------------------------------------ */
1852 #define SI__BMASK 0x01 /* SMBus Interrupt Flag */
1853 #define SI__SHIFT 0x00 /* SMBus Interrupt Flag */
1854 #define SI__NOT_SET 0x00 /* */
1855 #define SI__SET 0x01 /* */
1856
1857 #define ACK__BMASK 0x02 /* SMBus Acknowledge */
1858 #define ACK__SHIFT 0x01 /* SMBus Acknowledge */
1859 #define ACK__NOT_SET 0x00 /* Generate a NACK, or the response was a NACK. */
1860 #define ACK__SET 0x02 /* Generate an ACK, or the response was an ACK. */
1861
1862 #define ARBLOST__BMASK 0x04 /* SMBus Arbitration Lost Indicator */
1863 #define ARBLOST__SHIFT 0x02 /* SMBus Arbitration Lost Indicator */
1864 #define ARBLOST__NOT_SET 0x00 /* No arbitration error. */
1865 #define ARBLOST__ERROR 0x04 /* Arbitration error occurred. */
1866
1867 #define ACKRQ__BMASK 0x08 /* SMBus Acknowledge Request */
1868 #define ACKRQ__SHIFT 0x03 /* SMBus Acknowledge Request */
1869 #define ACKRQ__NOT_SET 0x00 /* No ACK requested. */
1870 #define ACKRQ__REQUESTED 0x08 /* ACK requested. */
1871
1872 #define STO__BMASK 0x10 /* SMBus Stop Flag */
1873 #define STO__SHIFT 0x04 /* SMBus Stop Flag */
1874 #define STO__NOT_SET 0x00 /* A STOP is not pending. */
1875 #define STO__SET 0x10 /* Generate a STOP or a STOP is currently pending. */
1876
1877 #define STA__BMASK 0x20 /* SMBus Start Flag */
1878 #define STA__SHIFT 0x05 /* SMBus Start Flag */
1879 #define STA__NOT_SET 0x00 /* A START was not detected. */
1880 #define STA__SET 0x20 /* Generate a START, repeated START, or a START is currently pending. */
1881
1882 #define TXMODE__BMASK 0x40 /* SMBus Transmit Mode Indicator */
1883 #define TXMODE__SHIFT 0x06 /* SMBus Transmit Mode Indicator */
1884 #define TXMODE__RECEIVER 0x00 /* SMBus in Receiver Mode. */
1885 #define TXMODE__TRANSMITTER 0x40 /* SMBus in Transmitter Mode. */
1886
1887 #define MASTER__BMASK 0x80 /* SMBus Master/Slave Indicator */
1888 #define MASTER__SHIFT 0x07 /* SMBus Master/Slave Indicator */
1889 #define MASTER__SLAVE 0x00 /* SMBus operating in slave mode. */
1890 #define MASTER__MASTER 0x80 /* SMBus operating in master mode. */
1891
1892 /*------------------------------------------------------------------------------ */
1893 /* SMB0TC Enums (SMBus 0 Timing and Pin Control @ 0xAC) */
1894 /*------------------------------------------------------------------------------ */
1895 #define SDD__FMASK 0x03 /* SMBus Start Detection Window */
1896 #define SDD__SHIFT 0x00 /* SMBus Start Detection Window */
1897 #define SDD__NONE 0x00 /* No additional hold time window (0-1 SYSCLK). */
1898 #define SDD__ADD_2_SYSCLKS 0x01 /* Increase hold time window to 2-3 SYSCLKs. */
1899 #define SDD__ADD_4_SYSCLKS 0x02 /* Increase hold time window to 4-5 SYSCLKs. */
1900 #define SDD__ADD_8_SYSCLKS 0x03 /* Increase hold time window to 8-9 SYSCLKs. */
1901
1902 #define SWAP__BMASK 0x80 /* SMBus Swap Pins */
1903 #define SWAP__SHIFT 0x07 /* SMBus Swap Pins */
1904 #define SWAP__SDA_LOW_PIN 0x00 /* SDA is mapped to the lower-numbered port pin, and SCL is mapped to the higher-numbered port pin. */
1905 #define SWAP__SDA_HIGH_PIN 0x80 /* SCL is mapped to the lower-numbered port pin, and SDA is mapped to the higher-numbered port pin. */
1906
1907 /*------------------------------------------------------------------------------ */
1908 /* SCON0 Enums (UART0 Serial Port Control @ 0x98) */
1909 /*------------------------------------------------------------------------------ */
1910 #define RI__BMASK 0x01 /* Receive Interrupt Flag */
1911 #define RI__SHIFT 0x00 /* Receive Interrupt Flag */
1912 #define RI__NOT_SET 0x00 /* A byte of data has not been received by UART0. */
1913 #define RI__SET 0x01 /* UART0 received a byte of data. */
1914
1915 #define TI__BMASK 0x02 /* Transmit Interrupt Flag */
1916 #define TI__SHIFT 0x01 /* Transmit Interrupt Flag */
1917 #define TI__NOT_SET 0x00 /* A byte of data has not been transmitted by UART0. */
1918 #define TI__SET 0x02 /* UART0 transmitted a byte of data. */
1919
1920 #define RB8__BMASK 0x04 /* Ninth Receive Bit */
1921 #define RB8__SHIFT 0x02 /* Ninth Receive Bit */
1922 #define RB8__CLEARED_TO_0 0x00 /* In Mode 0, the STOP bit was 0. In Mode 1, the 9th bit was 0. */
1923 #define RB8__SET_TO_1 0x04 /* In Mode 0, the STOP bit was 1. In Mode 1, the 9th bit was 1. */
1924
1925 #define TB8__BMASK 0x08 /* Ninth Transmission Bit */
1926 #define TB8__SHIFT 0x03 /* Ninth Transmission Bit */
1927 #define TB8__CLEARED_TO_0 0x00 /* In Mode 1, set the 9th transmission bit to 0. */
1928 #define TB8__SET_TO_1 0x08 /* In Mode 1, set the 9th transmission bit to 1. */
1929
1930 #define REN__BMASK 0x10 /* Receive Enable */
1931 #define REN__SHIFT 0x04 /* Receive Enable */
1932 #define REN__RECEIVE_DISABLED 0x00 /* UART0 reception disabled. */
1933 #define REN__RECEIVE_ENABLED 0x10 /* UART0 reception enabled. */
1934
1935 #define MCE__BMASK 0x20 /* Multiprocessor Communication Enable */
1936 #define MCE__SHIFT 0x05 /* Multiprocessor Communication Enable */
1937 #define MCE__MULTI_DISABLED 0x00 /* Ignore level of 9th bit / Stop bit. */
1938 #define MCE__MULTI_ENABLED 0x20 /* RI is set and an interrupt is generated only when the stop bit is logic 1 (Mode 0) or when the 9th bit is logic 1 (Mode 1). */
1939
1940 #define SMODE__BMASK 0x80 /* Serial Port 0 Operation Mode */
1941 #define SMODE__SHIFT 0x07 /* Serial Port 0 Operation Mode */
1942 #define SMODE__8_BIT 0x00 /* 8-bit UART with Variable Baud Rate (Mode 0). */
1943 #define SMODE__9_BIT 0x80 /* 9-bit UART with Variable Baud Rate (Mode 1). */
1944
1945 /*------------------------------------------------------------------------------ */
1946 /* CMP0CN0 Enums (Comparator 0 Control 0 @ 0x9B) */
1947 /*------------------------------------------------------------------------------ */
1948 #define CPHYN__FMASK 0x03 /* Comparator Negative Hysteresis Control */
1949 #define CPHYN__SHIFT 0x00 /* Comparator Negative Hysteresis Control */
1950 #define CPHYN__DISABLED 0x00 /* Negative Hysteresis disabled. */
1951 #define CPHYN__ENABLED_MODE1 0x01 /* Negative Hysteresis = Hysteresis 1. */
1952 #define CPHYN__ENABLED_MODE2 0x02 /* Negative Hysteresis = Hysteresis 2. */
1953 #define CPHYN__ENABLED_MODE3 0x03 /* Negative Hysteresis = Hysteresis 3 (Maximum). */
1954
1955 #define CPHYP__FMASK 0x0C /* Comparator Positive Hysteresis Control */
1956 #define CPHYP__SHIFT 0x02 /* Comparator Positive Hysteresis Control */
1957 #define CPHYP__DISABLED 0x00 /* Positive Hysteresis disabled. */
1958 #define CPHYP__ENABLED_MODE1 0x04 /* Positive Hysteresis = Hysteresis 1. */
1959 #define CPHYP__ENABLED_MODE2 0x08 /* Positive Hysteresis = Hysteresis 2. */
1960 #define CPHYP__ENABLED_MODE3 0x0C /* Positive Hysteresis = Hysteresis 3 (Maximum). */
1961
1962 #define CPFIF__BMASK 0x10 /* Comparator Falling-Edge Flag */
1963 #define CPFIF__SHIFT 0x04 /* Comparator Falling-Edge Flag */
1964 #define CPFIF__NOT_SET 0x00 /* No comparator falling edge has occurred since this flag was last cleared. */
1965 #define CPFIF__FALLING_EDGE 0x10 /* Comparator falling edge has occurred. */
1966
1967 #define CPRIF__BMASK 0x20 /* Comparator Rising-Edge Flag */
1968 #define CPRIF__SHIFT 0x05 /* Comparator Rising-Edge Flag */
1969 #define CPRIF__NOT_SET 0x00 /* No comparator rising edge has occurred since this flag was last cleared. */
1970 #define CPRIF__RISING_EDGE 0x20 /* Comparator rising edge has occurred. */
1971
1972 #define CPOUT__BMASK 0x40 /* Comparator Output State Flag */
1973 #define CPOUT__SHIFT 0x06 /* Comparator Output State Flag */
1974 #define CPOUT__POS_LESS_THAN_NEG 0x00 /* Voltage on CP0P < CP0N. */
1975 #define CPOUT__POS_GREATER_THAN_NEG 0x40 /* Voltage on CP0P > CP0N. */
1976
1977 #define CPEN__BMASK 0x80 /* Comparator Enable */
1978 #define CPEN__SHIFT 0x07 /* Comparator Enable */
1979 #define CPEN__DISABLED 0x00 /* Comparator disabled. */
1980 #define CPEN__ENABLED 0x80 /* Comparator enabled. */
1981
1982 /*------------------------------------------------------------------------------ */
1983 /* CMP0MD Enums (Comparator 0 Mode @ 0x9D) */
1984 /*------------------------------------------------------------------------------ */
1985 #define CPMD__FMASK 0x03 /* Comparator Mode Select */
1986 #define CPMD__SHIFT 0x00 /* Comparator Mode Select */
1987 #define CPMD__MODE0 0x00 /* Mode 0 (Fastest Response Time, Highest Power */
1988 /* Consumption) */
1989 #define CPMD__MODE1 0x01 /* Mode 1 */
1990 #define CPMD__MODE2 0x02 /* Mode 2 */
1991 #define CPMD__MODE3 0x03 /* Mode 3 (Slowest Response Time, Lowest Power */
1992 /* Consumption) */
1993
1994 #define CPFIE__BMASK 0x10 /* Comparator Falling-Edge Interrupt Enable */
1995 #define CPFIE__SHIFT 0x04 /* Comparator Falling-Edge Interrupt Enable */
1996 #define CPFIE__FALL_INT_DISABLED 0x00 /* Comparator falling-edge interrupt disabled. */
1997 #define CPFIE__FALL_INT_ENABLED 0x10 /* Comparator falling-edge interrupt enabled. */
1998
1999 #define CPRIE__BMASK 0x20 /* Comparator Rising-Edge Interrupt Enable */
2000 #define CPRIE__SHIFT 0x05 /* Comparator Rising-Edge Interrupt Enable */
2001 #define CPRIE__RISE_INT_DISABLED 0x00 /* Comparator rising-edge interrupt disabled. */
2002 #define CPRIE__RISE_INT_ENABLED 0x20 /* Comparator rising-edge interrupt enabled. */
2003
2004 #define CPLOUT__BMASK 0x80 /* Comparator Latched Output Flag */
2005 #define CPLOUT__SHIFT 0x07 /* Comparator Latched Output Flag */
2006 #define CPLOUT__LOW 0x00 /* Comparator output was logic low at last PCA overflow. */
2007 #define CPLOUT__HIGH 0x80 /* Comparator output was logic high at last PCA overflow. */
2008 #define CPMD__FMASK 0x03 /* Comparator Mode Select */
2009 #define CPMD__SHIFT 0x00 /* Comparator Mode Select */
2010 #define CPMD__MODE0 0x00 /* Mode 0 (Fastest Response Time, Highest Power Consumption) */
2011 #define CPMD__MODE1 0x01 /* Mode 1 */
2012 #define CPMD__MODE2 0x02 /* Mode 2 */
2013 #define CPMD__MODE3 0x03 /* Mode 3 (Slowest Response Time, Lowest Power Consumption) */
2014
2015 #define CPFIE__BMASK 0x10 /* Comparator Falling-Edge Interrupt Enable */
2016 #define CPFIE__SHIFT 0x04 /* Comparator Falling-Edge Interrupt Enable */
2017 #define CPFIE__FALL_INT_DISABLED 0x00 /* Comparator falling-edge interrupt disabled. */
2018 #define CPFIE__FALL_INT_ENABLED 0x10 /* Comparator falling-edge interrupt enabled. */
2019
2020 #define CPRIE__BMASK 0x20 /* Comparator Rising-Edge Interrupt Enable */
2021 #define CPRIE__SHIFT 0x05 /* Comparator Rising-Edge Interrupt Enable */
2022 #define CPRIE__RISE_INT_DISABLED 0x00 /* Comparator rising-edge interrupt disabled. */
2023 #define CPRIE__RISE_INT_ENABLED 0x20 /* Comparator rising-edge interrupt enabled. */
2024
2025 #define CPLOUT__BMASK 0x80 /* Comparator Latched Output Flag */
2026 #define CPLOUT__SHIFT 0x07 /* Comparator Latched Output Flag */
2027 #define CPLOUT__LOW 0x00 /* Comparator output was logic low at last PCA overflow. */
2028 #define CPLOUT__HIGH 0x80 /* Comparator output was logic high at last PCA overflow. */
2029
2030 /*------------------------------------------------------------------------------ */
2031 /* CMP0MX Enums (Comparator 0 Multiplexer Selection @ 0x9F) */
2032 /*------------------------------------------------------------------------------ */
2033 #define CMXP__FMASK 0x0F /* Comparator Positive Input MUX Selection */
2034 #define CMXP__SHIFT 0x00 /* Comparator Positive Input MUX Selection */
2035 #define CMXP__CMP0P0 0x00 /* External pin CMP0P.0. */
2036 #define CMXP__CMP0P1 0x01 /* External pin CMP0P.1. */
2037 #define CMXP__CMP0P2 0x02 /* External pin CMP0P.2. */
2038 #define CMXP__CMP0P3 0x03 /* External pin CMP0P.3. */
2039 #define CMXP__CMP0P4 0x04 /* External pin CMP0P.4. */
2040 #define CMXP__CMP0P5 0x05 /* External pin CMP0P.5. */
2041 #define CMXP__CMP0P6 0x06 /* External pin CMP0P.6. */
2042 #define CMXP__CMP0P7 0x07 /* External pin CMP0P.7. */
2043 #define CMXP__LDO_OUT 0x08 /* External pin CMP0P.8. */
2044 #define CMXP__NONE 0x0F /* No input selected. */
2045
2046 #define CMXN__FMASK 0xF0 /* Comparator Negative Input MUX Selection */
2047 #define CMXN__SHIFT 0x04 /* Comparator Negative Input MUX Selection */
2048 #define CMXN__CMP0N0 0x00 /* External pin CMP0N.0. */
2049 #define CMXN__CMP0N1 0x10 /* External pin CMP0N.1. */
2050 #define CMXN__CMP0N2 0x20 /* External pin CMP0N.2. */
2051 #define CMXN__CMP0N3 0x30 /* External pin CMP0N.3. */
2052 #define CMXN__CMP0N4 0x40 /* External pin CMP0N.4. */
2053 #define CMXN__CMP0N5 0x50 /* External pin CMP0N.5. */
2054 #define CMXN__CMP0N6 0x60 /* External pin CMP0N.6. */
2055 #define CMXN__CMP0N7 0x70 /* External pin CMP0N.7. */
2056 #define CMXN__GND 0x80 /* External pin CMP0N.8. */
2057 #define CMXN__NONE 0xF0 /* No input selected. */
2058
2059 /*------------------------------------------------------------------------------ */
2060 /* CMP1CN0 Enums (Comparator 1 Control 0 @ 0xBF) */
2061 /*------------------------------------------------------------------------------ */
2062 #define CPHYN__FMASK 0x03 /* Comparator Negative Hysteresis Control */
2063 #define CPHYN__SHIFT 0x00 /* Comparator Negative Hysteresis Control */
2064 #define CPHYN__DISABLED 0x00 /* Negative Hysteresis disabled. */
2065 #define CPHYN__ENABLED_MODE1 0x01 /* Negative Hysteresis = Hysteresis 1. */
2066 #define CPHYN__ENABLED_MODE2 0x02 /* Negative Hysteresis = Hysteresis 2. */
2067 #define CPHYN__ENABLED_MODE3 0x03 /* Negative Hysteresis = Hysteresis 3 (Maximum). */
2068
2069 #define CPHYP__FMASK 0x0C /* Comparator Positive Hysteresis Control */
2070 #define CPHYP__SHIFT 0x02 /* Comparator Positive Hysteresis Control */
2071 #define CPHYP__DISABLED 0x00 /* Positive Hysteresis disabled. */
2072 #define CPHYP__ENABLED_MODE1 0x04 /* Positive Hysteresis = Hysteresis 1. */
2073 #define CPHYP__ENABLED_MODE2 0x08 /* Positive Hysteresis = Hysteresis 2. */
2074 #define CPHYP__ENABLED_MODE3 0x0C /* Positive Hysteresis = Hysteresis 3 (Maximum). */
2075
2076 #define CPFIF__BMASK 0x10 /* Comparator Falling-Edge Flag */
2077 #define CPFIF__SHIFT 0x04 /* Comparator Falling-Edge Flag */
2078 #define CPFIF__NOT_SET 0x00 /* No comparator falling edge has occurred since this flag was last cleared. */
2079 #define CPFIF__FALLING_EDGE 0x10 /* Comparator falling edge has occurred. */
2080
2081 #define CPRIF__BMASK 0x20 /* Comparator Rising-Edge Flag */
2082 #define CPRIF__SHIFT 0x05 /* Comparator Rising-Edge Flag */
2083 #define CPRIF__NOT_SET 0x00 /* No comparator rising edge has occurred since this flag was last cleared. */
2084 #define CPRIF__RISING_EDGE 0x20 /* Comparator rising edge has occurred. */
2085
2086 #define CPOUT__BMASK 0x40 /* Comparator Output State Flag */
2087 #define CPOUT__SHIFT 0x06 /* Comparator Output State Flag */
2088 #define CPOUT__POS_LESS_THAN_NEG 0x00 /* Voltage on CP1P < CP1N. */
2089 #define CPOUT__POS_GREATER_THAN_NEG 0x40 /* Voltage on CP1P > CP1N. */
2090
2091 #define CPEN__BMASK 0x80 /* Comparator Enable */
2092 #define CPEN__SHIFT 0x07 /* Comparator Enable */
2093 #define CPEN__DISABLED 0x00 /* Comparator disabled. */
2094 #define CPEN__ENABLED 0x80 /* Comparator enabled. */
2095
2096 /*------------------------------------------------------------------------------ */
2097 /* CMP1MD Enums (Comparator 1 Mode @ 0xAB) */
2098 /*------------------------------------------------------------------------------ */
2099 #define CPMD__FMASK 0x03 /* Comparator Mode Select */
2100 #define CPMD__SHIFT 0x00 /* Comparator Mode Select */
2101 #define CPMD__MODE0 0x00 /* Mode 0 (Fastest Response Time, Highest Power Consumption) */
2102 #define CPMD__MODE1 0x01 /* Mode 1 */
2103 #define CPMD__MODE2 0x02 /* Mode 2 */
2104 #define CPMD__MODE3 0x03 /* Mode 3 (Slowest Response Time, Lowest Power Consumption) */
2105
2106 #define CPFIE__BMASK 0x10 /* Comparator Falling-Edge Interrupt Enable */
2107 #define CPFIE__SHIFT 0x04 /* Comparator Falling-Edge Interrupt Enable */
2108 #define CPFIE__FALL_INT_DISABLED 0x00 /* Comparator falling-edge interrupt disabled. */
2109 #define CPFIE__FALL_INT_ENABLED 0x10 /* Comparator falling-edge interrupt enabled. */
2110
2111 #define CPRIE__BMASK 0x20 /* Comparator Rising-Edge Interrupt Enable */
2112 #define CPRIE__SHIFT 0x05 /* Comparator Rising-Edge Interrupt Enable */
2113 #define CPRIE__RISE_INT_DISABLED 0x00 /* Comparator rising-edge interrupt disabled. */
2114 #define CPRIE__RISE_INT_ENABLED 0x20 /* Comparator rising-edge interrupt enabled. */
2115
2116 #define CPLOUT__BMASK 0x80 /* Comparator Latched Output Flag */
2117 #define CPLOUT__SHIFT 0x07 /* Comparator Latched Output Flag */
2118 #define CPLOUT__LOW 0x00 /* Comparator output was logic low at last PCA overflow. */
2119 #define CPLOUT__HIGH 0x80 /* Comparator output was logic high at last PCA overflow. */
2120
2121 /*------------------------------------------------------------------------------ */
2122 /* CMP1MX Enums (Comparator 1 Multiplexer Selection @ 0xAA) */
2123 /*------------------------------------------------------------------------------ */
2124 #define CMXP__FMASK 0x0F /* Comparator Positive Input MUX Selection */
2125 #define CMXP__SHIFT 0x00 /* Comparator Positive Input MUX Selection */
2126 #define CMXP__CMP1P0 0x00 /* External pin CMP1P.0. */
2127 #define CMXP__CMP1P1 0x01 /* External pin CMP1P.1. */
2128 #define CMXP__CMP1P2 0x02 /* External pin CMP1P.2. */
2129 #define CMXP__CMP1P3 0x03 /* External pin CMP1P.3. */
2130 #define CMXP__CMP1P4 0x04 /* External pin CMP1P.4. */
2131 #define CMXP__CMP1P5 0x05 /* External pin CMP1P.5. */
2132 #define CMXP__CMP1P6 0x06 /* External pin CMP1P.6. */
2133 #define CMXP__CMP1P7 0x07 /* External pin CMP1P.7. */
2134 #define CMXP__LDO_OUT 0x08 /* External pin CMP1P.8. */
2135 #define CMXP__NONE 0x0F /* No input selected. */
2136
2137 #define CMXN__FMASK 0xF0 /* Comparator Negative Input MUX Selection */
2138 #define CMXN__SHIFT 0x04 /* Comparator Negative Input MUX Selection */
2139 #define CMXN__CMP1N0 0x00 /* External pin CMP1N.0. */
2140 #define CMXN__CMP1N1 0x10 /* External pin CMP1N.1. */
2141 #define CMXN__CMP1N2 0x20 /* External pin CMP1N.2. */
2142 #define CMXN__CMP1N3 0x30 /* External pin CMP1N.3. */
2143 #define CMXN__CMP1N4 0x40 /* External pin CMP1N.4. */
2144 #define CMXN__CMP1N5 0x50 /* External pin CMP1N.5. */
2145 #define CMXN__CMP1N6 0x60 /* External pin CMP1N.6. */
2146 #define CMXN__CMP1N7 0x70 /* External pin CMP1N.7. */
2147 #define CMXN__GND 0x80 /* External pin CMP1N.8. */
2148 #define CMXN__NONE 0xF0 /* No input selected. */
2149
2150 /*------------------------------------------------------------------------------ */
2151 /* CRC0AUTO Enums (CRC0 Automatic Control @ 0xD2) */
2152 /*------------------------------------------------------------------------------ */
2153 #define CRCST__FMASK 0x3F /* Automatic CRC Calculation Starting Block */
2154 #define CRCST__SHIFT 0x00 /* Automatic CRC Calculation Starting Block */
2155
2156 #define AUTOEN__BMASK 0x80 /* Automatic CRC Calculation Enable */
2157 #define AUTOEN__SHIFT 0x07 /* Automatic CRC Calculation Enable */
2158 #define AUTOEN__DISABLED 0x00 /* Disable automatic CRC operations on flash. */
2159 #define AUTOEN__ENABLED 0x80 /* Enable automatic CRC operations on flash. */
2160
2161 /*------------------------------------------------------------------------------ */
2162 /* CRC0CN0 Enums (CRC0 Control 0 @ 0xCE) */
2163 /*------------------------------------------------------------------------------ */
2164 #define CRCPNT__BMASK 0x01 /* CRC Result Pointer */
2165 #define CRCPNT__SHIFT 0x00 /* CRC Result Pointer */
2166 #define CRCPNT__ACCESS_LOWER 0x00 /* CRC0DAT accesses bits 7-0 of the 16-bit CRC result. */
2167 #define CRCPNT__ACCESS_UPPER 0x01 /* CRC0DAT accesses bits 15-8 of the 16-bit CRC result. */
2168
2169 #define CRCVAL__BMASK 0x04 /* CRC Initialization Value */
2170 #define CRCVAL__SHIFT 0x02 /* CRC Initialization Value */
2171 #define CRCVAL__SET_ZEROES 0x00 /* CRC result is set to 0x0000 on write of 1 to CRCINIT. */
2172 #define CRCVAL__SET_ONES 0x04 /* CRC result is set to 0xFFFF on write of 1 to CRCINIT. */
2173
2174 #define CRCINIT__BMASK 0x08 /* CRC Initialization Enable */
2175 #define CRCINIT__SHIFT 0x03 /* CRC Initialization Enable */
2176 #define CRCINIT__DO_NOT_INIT 0x00 /* Do not initialize the CRC result. */
2177 #define CRCINIT__INIT 0x08 /* Initialize the CRC result to ones or zeroes vased on the value of CRCVAL. */
2178
2179 /*------------------------------------------------------------------------------ */
2180 /* CRC0CNT Enums (CRC0 Automatic Flash Sector Count @ 0xD3) */
2181 /*------------------------------------------------------------------------------ */
2182 #define CRCCNT__FMASK 0x1F /* Automatic CRC Calculation Block Count */
2183 #define CRCCNT__SHIFT 0x00 /* Automatic CRC Calculation Block Count */
2184
2185 #define CRCDN__BMASK 0x80 /* Automatic CRC Calculation Complete */
2186 #define CRCDN__SHIFT 0x07 /* Automatic CRC Calculation Complete */
2187 #define CRCDN__NOT_SET 0x00 /* A CRC calculation is in progress. */
2188 #define CRCDN__SET 0x80 /* A CRC calculation is not in progress. */
2189
2190
2191 /*------------------------------------------------------------------------------ */
2192 /* DERIVID Enums (Derivative Identification @ 0xAD) */
2193 /*------------------------------------------------------------------------------ */
2194 #define DERIVID__FMASK 0xFF /* Derivative ID */
2195 #define DERIVID__SHIFT 0x00 /* Derivative ID */
2196 #define DERIVID__EFM8BB10F8G_QSOP24 0x01 /* EFM8BB10F8G-{R}-QSOP24 */
2197 #define DERIVID__EFM8BB10F8G_QFN20 0x02 /* EFM8BB10F8G-{R}-QFN20 */
2198 #define DERIVID__EFM8BB10F8G_SOIC16 0x03 /* EFM8BB10F8G-{R}-SOIC16 */
2199 #define DERIVID__EFM8BB10F4G_QFN20 0x05 /* EFM8BB10F4G-{R}-QFN20 */
2200 #define DERIVID__EFM8BB10F2G_QFN20 0x08 /* EFM8BB10F2G-{R}-QFN20 */
2201
2202 /*------------------------------------------------------------------------------ */
2203 /* REVID Enums (Revision Identifcation @ 0xB6) */
2204 /*------------------------------------------------------------------------------ */
2205 #define REVID__FMASK 0xFF /* Revision ID */
2206 #define REVID__SHIFT 0x00 /* Revision ID */
2207 #define REVID__REV_A 0x02 /* Revision A */
2208
2209 /*------------------------------------------------------------------------------ */
2210 /* IT01CF Enums (INT0/INT1 Configuration @ 0xE4) */
2211 /*------------------------------------------------------------------------------ */
2212 #define IN0SL__FMASK 0x07 /* INT0 Port Pin Selection */
2213 #define IN0SL__SHIFT 0x00 /* INT0 Port Pin Selection */
2214 #define IN0SL__P0_0 0x00 /* Select P0.0. */
2215 #define IN0SL__P0_1 0x01 /* Select P0.1. */
2216 #define IN0SL__P0_2 0x02 /* Select P0.2. */
2217 #define IN0SL__P0_3 0x03 /* Select P0.3. */
2218 #define IN0SL__P0_4 0x04 /* Select P0.4. */
2219 #define IN0SL__P0_5 0x05 /* Select P0.5. */
2220 #define IN0SL__P0_6 0x06 /* Select P0.6. */
2221 #define IN0SL__P0_7 0x07 /* Select P0.7. */
2222
2223 #define IN0PL__BMASK 0x08 /* INT0 Polarity */
2224 #define IN0PL__SHIFT 0x03 /* INT0 Polarity */
2225 #define IN0PL__ACTIVE_LOW 0x00 /* INT0 input is active low. */
2226 #define IN0PL__ACTIVE_HIGH 0x08 /* INT0 input is active high. */
2227
2228 #define IN1SL__FMASK 0x70 /* INT1 Port Pin Selection */
2229 #define IN1SL__SHIFT 0x04 /* INT1 Port Pin Selection */
2230 #define IN1SL__P0_0 0x00 /* Select P0.0. */
2231 #define IN1SL__P0_1 0x10 /* Select P0.1. */
2232 #define IN1SL__P0_2 0x20 /* Select P0.2. */
2233 #define IN1SL__P0_3 0x30 /* Select P0.3. */
2234 #define IN1SL__P0_4 0x40 /* Select P0.4. */
2235 #define IN1SL__P0_5 0x50 /* Select P0.5. */
2236 #define IN1SL__P0_6 0x60 /* Select P0.6. */
2237 #define IN1SL__P0_7 0x70 /* Select P0.7. */
2238
2239 #define IN1PL__BMASK 0x80 /* INT1 Polarity */
2240 #define IN1PL__SHIFT 0x07 /* INT1 Polarity */
2241 #define IN1PL__ACTIVE_LOW 0x00 /* INT1 input is active low. */
2242 #define IN1PL__ACTIVE_HIGH 0x80 /* INT1 input is active high. */
2243
2244 /*------------------------------------------------------------------------------ */
2245 /* FLKEY Enums (Flash Lock and Key @ 0xB7) */
2246 /*------------------------------------------------------------------------------ */
2247 #define FLKEY__FMASK 0xFF /* Flash Lock and Key */
2248 #define FLKEY__SHIFT 0x00 /* Flash Lock and Key */
2249 #define FLKEY__LOCKED 0x00 /* Flash is write/erase locked. */
2250 #define FLKEY__FIRST 0x01 /* The first key code has been written (0xA5). */
2251 #define FLKEY__UNLOCKED 0x02 /* Flash is unlocked (writes/erases allowed). */
2252 #define FLKEY__DISABLED 0x03 /* Flash writes/erases are disabled until the next reset. */
2253 #define FLKEY__KEY1 0xA5 /* Flash writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. */
2254 #define FLKEY__KEY2 0xF1 /* Flash writes and erases are enabled by writing 0xA5 followed by 0xF1 to the FLKEY register. */
2255
2256 /*------------------------------------------------------------------------------ */
2257 /* PSCTL Enums (Program Store Control @ 0x8F) */
2258 /*------------------------------------------------------------------------------ */
2259 #define PSWE__BMASK 0x01 /* Program Store Write Enable */
2260 #define PSWE__SHIFT 0x00 /* Program Store Write Enable */
2261 #define PSWE__WRITE_DISABLED 0x00 /* Writes to flash program memory disabled. */
2262 #define PSWE__WRITE_ENABLED 0x01 /* Writes to flash program memory enabled; the MOVX write instruction targets flash memory. */
2263
2264 #define PSEE__BMASK 0x02 /* Program Store Erase Enable */
2265 #define PSEE__SHIFT 0x01 /* Program Store Erase Enable */
2266 #define PSEE__ERASE_DISABLED 0x00 /* Flash program memory erasure disabled. */
2267 #define PSEE__ERASE_ENABLED 0x02 /* Flash program memory erasure enabled. */
2268
2269 /*------------------------------------------------------------------------------ */
2270 /* IP Enums (Interrupt Priority @ 0xB8) */
2271 /*------------------------------------------------------------------------------ */
2272 #define PX0__BMASK 0x01 /* External Interrupt 0 Priority Control */
2273 #define PX0__SHIFT 0x00 /* External Interrupt 0 Priority Control */
2274 #define PX0__LOW 0x00 /* External Interrupt 0 set to low priority level. */
2275 #define PX0__HIGH 0x01 /* External Interrupt 0 set to high priority level. */
2276
2277 #define PT0__BMASK 0x02 /* Timer 0 Interrupt Priority Control */
2278 #define PT0__SHIFT 0x01 /* Timer 0 Interrupt Priority Control */
2279 #define PT0__LOW 0x00 /* Timer 0 interrupt set to low priority level. */
2280 #define PT0__HIGH 0x02 /* Timer 0 interrupt set to high priority level. */
2281
2282 #define PX1__BMASK 0x04 /* External Interrupt 1 Priority Control */
2283 #define PX1__SHIFT 0x02 /* External Interrupt 1 Priority Control */
2284 #define PX1__LOW 0x00 /* External Interrupt 1 set to low priority level. */
2285 #define PX1__HIGH 0x04 /* External Interrupt 1 set to high priority level. */
2286
2287 #define PT1__BMASK 0x08 /* Timer 1 Interrupt Priority Control */
2288 #define PT1__SHIFT 0x03 /* Timer 1 Interrupt Priority Control */
2289 #define PT1__LOW 0x00 /* Timer 1 interrupt set to low priority level. */
2290 #define PT1__HIGH 0x08 /* Timer 1 interrupt set to high priority level. */
2291
2292 #define PS0__BMASK 0x10 /* UART0 Interrupt Priority Control */
2293 #define PS0__SHIFT 0x04 /* UART0 Interrupt Priority Control */
2294 #define PS0__LOW 0x00 /* UART0 interrupt set to low priority level. */
2295 #define PS0__HIGH 0x10 /* UART0 interrupt set to high priority level. */
2296
2297 #define PT2__BMASK 0x20 /* Timer 2 Interrupt Priority Control */
2298 #define PT2__SHIFT 0x05 /* Timer 2 Interrupt Priority Control */
2299 #define PT2__LOW 0x00 /* Timer 2 interrupt set to low priority level. */
2300 #define PT2__HIGH 0x20 /* Timer 2 interrupt set to high priority level. */
2301
2302 #define PSPI0__BMASK 0x40 /* Serial Peripheral Interface (SPI0) Interrupt Priority Control */
2303 #define PSPI0__SHIFT 0x06 /* Serial Peripheral Interface (SPI0) Interrupt Priority Control */
2304 #define PSPI0__LOW 0x00 /* SPI0 interrupt set to low priority level. */
2305 #define PSPI0__HIGH 0x40 /* SPI0 interrupt set to high priority level. */
2306
2307 /*------------------------------------------------------------------------------ */
2308 /* LFO0CN Enums (Low Frequency Oscillator Control @ 0xB1) */
2309 /*------------------------------------------------------------------------------ */
2310 typedef union {
2311 uint8_t reg;
2312 struct {
2313 uint8_t OSCLD : 2;
2314 uint8_t OSCLF : 4;
2315 uint8_t OSCLRDY : 1;
2316 uint8_t OSCLEN : 1;
2317 } bf;
2318 } LFO0CN_t;
2319
2320 #define OSCLD__DIVIDE_BY_8 0x00 /* Divide by 8 selected. */
2321 #define OSCLD__DIVIDE_BY_4 0x01 /* Divide by 4 selected. */
2322 #define OSCLD__DIVIDE_BY_2 0x02 /* Divide by 2 selected. */
2323 #define OSCLD__DIVIDE_BY_1 0x03 /* Divide by 1 selected. */
2324
2325 #define OSCLRDY__NOT_SET 0x00 /* Internal L-F Oscillator frequency not stabilized. */
2326 #define OSCLRDY__SET 0x01 /* Internal L-F Oscillator frequency stabilized. */
2327
2328 #define OSCLEN__DISABLED 0x00 /* Internal L-F Oscillator Disabled. */
2329 #define OSCLEN__ENABLED 0x01 /* Internal L-F Oscillator Enabled. */
2330
2331 /*------------------------------------------------------------------------------ */
2332 /* PRTDRV Enums (Port Drive Strength @ 0xF6) */
2333 /*------------------------------------------------------------------------------ */
2334 #define P0DRV__BMASK 0x01 /* Port 0 Drive Strength */
2335 #define P0DRV__SHIFT 0x00 /* Port 0 Drive Strength */
2336 #define P0DRV__LOW_DRIVE 0x00 /* All pins on P0 use low drive strength. */
2337 #define P0DRV__HIGH_DRIVE 0x01 /* All pins on P0 use high drive strength. */
2338
2339 #define P1DRV__BMASK 0x02 /* Port 1 Drive Strength */
2340 #define P1DRV__SHIFT 0x01 /* Port 1 Drive Strength */
2341 #define P1DRV__LOW_DRIVE 0x00 /* All pins on P1 use low drive strength. */
2342 #define P1DRV__HIGH_DRIVE 0x02 /* All pins on P1 use high drive strength. */
2343
2344 #define P2DRV__BMASK 0x04 /* Port 2 Drive Strength */
2345 #define P2DRV__SHIFT 0x02 /* Port 2 Drive Strength */
2346 #define P2DRV__LOW_DRIVE 0x00 /* All pins on P2 use low drive strength. */
2347 #define P2DRV__HIGH_DRIVE 0x04 /* All pins on P2 use high drive strength. */
2348
2349 /*------------------------------------------------------------------------------ */
2350 /* PCON0 Enums (Power Control @ 0x87) */
2351 /*------------------------------------------------------------------------------ */
2352 #define IDLE__BMASK 0x01 /* Idle Mode Select */
2353 #define IDLE__SHIFT 0x00 /* Idle Mode Select */
2354 #define IDLE__NORMAL 0x00 /* Idle mode not activated. */
2355 #define IDLE__IDLE 0x01 /* CPU goes into Idle mode (shuts off clock to CPU, but clocks to enabled peripherals are still active). */
2356
2357 #define STOP__BMASK 0x02 /* Stop Mode Select */
2358 #define STOP__SHIFT 0x01 /* Stop Mode Select */
2359 #define STOP__NORMAL 0x00 /* Stop mode not activated. */
2360 #define STOP__STOP 0x02 /* CPU goes into Stop mode (internal oscillator stopped). */
2361
2362 #define GF0__BMASK 0x04 /* General Purpose Flag 0 */
2363 #define GF0__SHIFT 0x02 /* General Purpose Flag 0 */
2364 #define GF0__NOT_SET 0x00 /* The GF0 flag is not set. Clear the GF0 flag. */
2365 #define GF0__SET 0x04 /* The GF0 flag is set. Set the GF0 flag. */
2366
2367 #define GF1__BMASK 0x08 /* General Purpose Flag 1 */
2368 #define GF1__SHIFT 0x03 /* General Purpose Flag 1 */
2369 #define GF1__NOT_SET 0x00 /* The GF1 flag is not set. Clear the GF1 flag. */
2370 #define GF1__SET 0x08 /* The GF1 flag is set. Set the GF1 flag. */
2371
2372 #define GF2__BMASK 0x10 /* General Purpose Flag 2 */
2373 #define GF2__SHIFT 0x04 /* General Purpose Flag 2 */
2374 #define GF2__NOT_SET 0x00 /* The GF2 flag is not set. Clear the GF2 flag. */
2375 #define GF2__SET 0x10 /* The GF2 flag is set. Set the GF2 flag. */
2376
2377 #define GF3__BMASK 0x20 /* General Purpose Flag 3 */
2378 #define GF3__SHIFT 0x05 /* General Purpose Flag 3 */
2379 #define GF3__NOT_SET 0x00 /* The GF3 flag is not set. Clear the GF3 flag. */
2380 #define GF3__SET 0x20 /* The GF3 flag is set. Set the GF3 flag. */
2381
2382 #define GF4__BMASK 0x40 /* General Purpose Flag 4 */
2383 #define GF4__SHIFT 0x06 /* General Purpose Flag 4 */
2384 #define GF4__NOT_SET 0x00 /* The GF4 flag is not set. Clear the GF4 flag. */
2385 #define GF4__SET 0x40 /* The GF4 flag is set. Set the GF4 flag. */
2386
2387 #define GF5__BMASK 0x80 /* General Purpose Flag 5 */
2388 #define GF5__SHIFT 0x07 /* General Purpose Flag 5 */
2389 #define GF5__NOT_SET 0x00 /* The GF5 flag is not set. Clear the GF5 flag. */
2390 #define GF5__SET 0x80 /* The GF5 flag is set. Set the GF5 flag. */
2391
2392 /*------------------------------------------------------------------------------ */
2393 /* RSTSRC Enums (Reset Source @ 0xEF) */
2394 /*------------------------------------------------------------------------------ */
2395 #define PINRSF__BMASK 0x01 /* HW Pin Reset Flag */
2396 #define PINRSF__SHIFT 0x00 /* HW Pin Reset Flag */
2397 #define PINRSF__NOT_SET 0x00 /* The RSTb pin did not cause the last reset. */
2398 #define PINRSF__SET 0x01 /* The RSTb pin caused the last reset. */
2399
2400 #define PORSF__BMASK 0x02 /* Power-On / Supply Monitor Reset Flag, and Supply Monitor Reset Enable */
2401 #define PORSF__SHIFT 0x01 /* Power-On / Supply Monitor Reset Flag, and Supply Monitor Reset Enable */
2402 #define PORSF__NOT_SET 0x00 /* A power-on or supply monitor reset did not occur. */
2403 #define PORSF__SET 0x02 /* A power-on or supply monitor reset occurred. */
2404
2405 #define MCDRSF__BMASK 0x04 /* Missing Clock Detector Enable and Flag */
2406 #define MCDRSF__SHIFT 0x02 /* Missing Clock Detector Enable and Flag */
2407 #define MCDRSF__NOT_SET 0x00 /* A missing clock detector reset did not occur. */
2408 #define MCDRSF__SET 0x04 /* A missing clock detector reset occurred. */
2409
2410 #define WDTRSF__BMASK 0x08 /* Watchdog Timer Reset Flag */
2411 #define WDTRSF__SHIFT 0x03 /* Watchdog Timer Reset Flag */
2412 #define WDTRSF__NOT_SET 0x00 /* A watchdog timer overflow reset did not occur. */
2413 #define WDTRSF__SET 0x08 /* A watchdog timer overflow reset occurred. */
2414
2415 #define SWRSF__BMASK 0x10 /* Software Reset Force and Flag */
2416 #define SWRSF__SHIFT 0x04 /* Software Reset Force and Flag */
2417 #define SWRSF__NOT_SET 0x00 /* A software reset did not occur. */
2418 #define SWRSF__SET 0x10 /* A software reset occurred. */
2419
2420 #define C0RSEF__BMASK 0x20 /* Comparator0 Reset Enable and Flag */
2421 #define C0RSEF__SHIFT 0x05 /* Comparator0 Reset Enable and Flag */
2422 #define C0RSEF__NOT_SET 0x00 /* A Comparator 0 reset did not occur. */
2423 #define C0RSEF__SET 0x20 /* A Comparator 0 reset occurred. */
2424
2425 #define FERROR__BMASK 0x40 /* Flash Error Reset Flag */
2426 #define FERROR__SHIFT 0x06 /* Flash Error Reset Flag */
2427 #define FERROR__NOT_SET 0x00 /* A flash error reset did not occur. */
2428 #define FERROR__SET 0x40 /* A flash error reset occurred. */
2429
2430 /*------------------------------------------------------------------------------ */
2431 /* CKCON0 Enums (Clock Control 0 @ 0x8E) */
2432 /*------------------------------------------------------------------------------ */
2433 #define SCA__FMASK 0x03 /* Timer 0/1 Prescale */
2434 #define SCA__SHIFT 0x00 /* Timer 0/1 Prescale */
2435 #define SCA__SYSCLK_DIV_12 0x00 /* System clock divided by 12. */
2436 #define SCA__SYSCLK_DIV_4 0x01 /* System clock divided by 4. */
2437 #define SCA__SYSCLK_DIV_48 0x02 /* System clock divided by 48. */
2438 #define SCA__EXTOSC_DIV_8 0x03 /* External oscillator divided by 8 (synchronized with the system clock). */
2439
2440 #define T0M__PRESCALE 0x00 /* Counter/Timer 0 uses the clock defined by the prescale field, SCA. */
2441 #define T0M__SYSCLK 0x04 /* Counter/Timer 0 uses the system clock. */
2442
2443 #define T1M__PRESCALE 0x00 /* Timer 1 uses the clock defined by the prescale field, SCA. */
2444 #define T1M__SYSCLK 0x08 /* Timer 1 uses the system clock. */
2445
2446 #define T2ML__BMASK 0x10 /* Timer 2 Low Byte Clock Select */
2447 #define T2ML__SHIFT 0x04 /* Timer 2 Low Byte Clock Select */
2448 #define T2ML__EXTERNAL_CLOCK 0x00 /* Timer 2 low byte uses the clock defined by T2XCLK in TMR2CN0. */
2449 #define T2ML__SYSCLK 0x10 /* Timer 2 low byte uses the system clock. */
2450
2451 #define T2MH__BMASK 0x20 /* Timer 2 High Byte Clock Select */
2452 #define T2MH__SHIFT 0x05 /* Timer 2 High Byte Clock Select */
2453 #define T2MH__EXTERNAL_CLOCK 0x00 /* Timer 2 high byte uses the clock defined by T2XCLK in TMR2CN0. */
2454 #define T2MH__SYSCLK 0x20 /* Timer 2 high byte uses the system clock. */
2455
2456 #define T3ML__BMASK 0x40 /* Timer 3 Low Byte Clock Select */
2457 #define T3ML__SHIFT 0x06 /* Timer 3 Low Byte Clock Select */
2458 #define T3ML__EXTERNAL_CLOCK 0x00 /* Timer 3 low byte uses the clock defined by T3XCLK in TMR3CN0. */
2459 #define T3ML__SYSCLK 0x40 /* Timer 3 low byte uses the system clock. */
2460
2461 #define T3MH__BMASK 0x80 /* Timer 3 High Byte Clock Select */
2462 #define T3MH__SHIFT 0x07 /* Timer 3 High Byte Clock Select */
2463 #define T3MH__EXTERNAL_CLOCK 0x00 /* Timer 3 high byte uses the clock defined by T3XCLK in TMR3CN0. */
2464 #define T3MH__SYSCLK 0x80 /* Timer 3 high byte uses the system clock. */
2465
2466 /*------------------------------------------------------------------------------ */
2467 /* TCON Enums (Timer 0/1 Control @ 0x88) */
2468 /*------------------------------------------------------------------------------ */
2469 #define IT0__BMASK 0x01 /* Interrupt 0 Type Select */
2470 #define IT0__SHIFT 0x00 /* Interrupt 0 Type Select */
2471 #define IT0__LEVEL 0x00 /* INT0 is level triggered. */
2472 #define IT0__EDGE 0x01 /* INT0 is edge triggered. */
2473
2474 #define IE0__BMASK 0x02 /* External Interrupt 0 */
2475 #define IE0__SHIFT 0x01 /* External Interrupt 0 */
2476 #define IE0__NOT_SET 0x00 /* Edge/level not detected. */
2477 #define IE0__SET 0x02 /* Edge/level detected */
2478
2479 #define IT1__BMASK 0x04 /* Interrupt 1 Type Select */
2480 #define IT1__SHIFT 0x02 /* Interrupt 1 Type Select */
2481 #define IT1__LEVEL 0x00 /* INT1 is level triggered. */
2482 #define IT1__EDGE 0x04 /* INT1 is edge triggered. */
2483
2484 #define IE1__BMASK 0x08 /* External Interrupt 1 */
2485 #define IE1__SHIFT 0x03 /* External Interrupt 1 */
2486 #define IE1__NOT_SET 0x00 /* Edge/level not detected. */
2487 #define IE1__SET 0x08 /* Edge/level detected */
2488
2489 #define TR0__BMASK 0x10 /* Timer 0 Run Control */
2490 #define TR0__SHIFT 0x04 /* Timer 0 Run Control */
2491 #define TR0__STOP 0x00 /* Stop Timer 0. */
2492 #define TR0__RUN 0x10 /* Start Timer 0 running. */
2493
2494 #define TF0__BMASK 0x20 /* Timer 0 Overflow Flag */
2495 #define TF0__SHIFT 0x05 /* Timer 0 Overflow Flag */
2496 #define TF0__NOT_SET 0x00 /* Timer 0 did not overflow. */
2497 #define TF0__SET 0x20 /* Timer 0 overflowed. */
2498
2499 #define TR1__BMASK 0x40 /* Timer 1 Run Control */
2500 #define TR1__SHIFT 0x06 /* Timer 1 Run Control */
2501 #define TR1__STOP 0x00 /* Stop Timer 1. */
2502 #define TR1__RUN 0x40 /* Start Timer 1 running. */
2503
2504 #define TF1__BMASK 0x80 /* Timer 1 Overflow Flag */
2505 #define TF1__SHIFT 0x07 /* Timer 1 Overflow Flag */
2506 #define TF1__NOT_SET 0x00 /* Timer 1 did not overflow. */
2507 #define TF1__SET 0x80 /* Timer 1 overflowed. */
2508
2509 /*------------------------------------------------------------------------------ */
2510 /* TMOD Enums (Timer 0/1 Mode @ 0x89) */
2511 /*------------------------------------------------------------------------------ */
2512 #define T0M__MODE0 0x00 /* Mode 0, 13-bit Counter/Timer */
2513 #define T0M__MODE1 0x01 /* Mode 1, 16-bit Counter/Timer */
2514 #define T0M__MODE2 0x02 /* Mode 2, 8-bit Counter/Timer with Auto-Reload */
2515 #define T0M__MODE3 0x03 /* Mode 3, Two 8-bit Counter/Timers */
2516
2517 #define CT0__BMASK 0x04 /* Counter/Timer 0 Select */
2518 #define CT0__SHIFT 0x02 /* Counter/Timer 0 Select */
2519 #define CT0__TIMER 0x00 /* Timer Mode. Timer 0 increments on the clock defined by T0M in the CKCON0 register. */
2520 #define CT0__COUNTER 0x04 /* Counter Mode. Timer 0 increments on high-to-low transitions of an external pin (T0). */
2521
2522 #define GATE0__BMASK 0x08 /* Timer 0 Gate Control */
2523 #define GATE0__SHIFT 0x03 /* Timer 0 Gate Control */
2524 #define GATE0__DISABLED 0x00 /* Timer 0 enabled when TR0 = 1 irrespective of INT0 logic level. */
2525 #define GATE0__ENABLED 0x08 /* Timer 0 enabled only when TR0 = 1 and INT0 is active as defined by bit IN0PL in register IT01CF. */
2526
2527 #define T1M__FMASK 0x30 /* Timer 1 Mode Select */
2528 #define T1M__SHIFT 0x04 /* Timer 1 Mode Select */
2529 #define T1M__MODE0 0x00 /* Mode 0, 13-bit Counter/Timer */
2530 #define T1M__MODE1 0x10 /* Mode 1, 16-bit Counter/Timer */
2531 #define T1M__MODE2 0x20 /* Mode 2, 8-bit Counter/Timer with Auto-Reload */
2532 #define T1M__MODE3 0x30 /* Mode 3, Timer 1 Inactive */
2533
2534 #define CT1__BMASK 0x40 /* Counter/Timer 1 Select */
2535 #define CT1__SHIFT 0x06 /* Counter/Timer 1 Select */
2536 #define CT1__TIMER 0x00 /* Timer Mode. Timer 1 increments on the clock defined by T1M in the CKCON0 register. */
2537 #define CT1__COUNTER 0x40 /* Counter Mode. Timer 1 increments on high-to-low transitions of an external pin (T1). */
2538
2539 #define GATE1__BMASK 0x80 /* Timer 1 Gate Control */
2540 #define GATE1__SHIFT 0x07 /* Timer 1 Gate Control */
2541 #define GATE1__DISABLED 0x00 /* Timer 1 enabled when TR1 = 1 irrespective of INT1 logic level. */
2542 #define GATE1__ENABLED 0x80 /* Timer 1 enabled only when TR1 = 1 and INT1 is active as defined by bit IN1PL in register IT01CF. */
2543
2544 /*------------------------------------------------------------------------------ */
2545 /* VDM0CN Enums (Supply Monitor Control @ 0xFF) */
2546 /*------------------------------------------------------------------------------ */
2547 #define VDDSTAT__BMASK 0x40 /* Supply Status */
2548 #define VDDSTAT__SHIFT 0x06 /* Supply Status */
2549 #define VDDSTAT__BELOW 0x00 /* VDD is at or below the supply monitor threshold. */
2550 #define VDDSTAT__ABOVE 0x40 /* VDD is above the supply monitor threshold. */
2551
2552 #define VDMEN__BMASK 0x80 /* Supply Monitor Enable */
2553 #define VDMEN__SHIFT 0x07 /* Supply Monitor Enable */
2554 #define VDMEN__DISABLED 0x00 /* Supply Monitor Disabled. */
2555 #define VDMEN__ENABLED 0x80 /* Supply Monitor Enabled. */
2556
2557 /*------------------------------------------------------------------------------ */
2558 /* Watchdog Timer Control */
2559 /*------------------------------------------------------------------------------ */
2560
2561 #ifdef WDT_no
2562
2563 #define WDT_lockout()
2564 #define WDT_reset()
2565 #define WDT_enable()
2566 #define WDT_1ms()
2567 #define WDT_2ms()
2568 #define WDT_13ms()
2569 #define WDT_51ms()
2570 #define WDT_204ms()
2571 #define WDT_819ms()
2572 #define WDT_32767ms()
2573 #define WDT_13107ms()
2574
2575 #else
2576
2577 #define WDT_lockout() WDTCN=0xff
2578 #define WDT_reset() WDTCN=0xA5
2579 #define WDT_enable() WDTCN=0xA5
2580 #define WDT_1ms() WDTCN=0x00
2581 #define WDT_2ms() WDTCN=0x01
2582 #define WDT_13ms() WDTCN=0x02
2583 #define WDT_51ms() WDTCN=0x03
2584 #define WDT_204ms() WDTCN=0x04
2585 #define WDT_819ms() WDTCN=0x05
2586 #define WDT_32767ms() WDTCN=0x06
2587 #define WDT_13107ms() WDTCN=0x07
2588
2589 #endif /* WDT_no */
2590
2591 #endif /* EFM8BB1_H */
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