sdcc/device/include/mcs51/P89LPC922.h

   1 /*------------------------------------------------------------------//--------
   2 P89LPC922.H
   3 (English)
   4 This header allows to use the microcontroler Philips P89LPC922
   5 with the compiler SDCC.
   6
   7 Copyright (c) 2005 Omar Espinosa--e-mail: opiedrahita2003 AT yahoo.com.
   8
   9    This library is free software; you can redistribute it and/or
  10    modify it under the terms of the GNU Lesser General Public
  11    License as published by the Free Software Foundation; either
  12    version 2.1 of the License, or (at your option) any later version.
  13
  14    This library is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17    Lesser General Public License for more details.
  18
  19    You should have received a copy of the GNU Lesser General Public
  20    License along with this library; if not, write to the Free Software
  21    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  22
  23 (Spanish)
  24 Archivo encabezador para el ucontrolador Philips P89LPC922.
  25 Derechos de copy (DC) 2005.  OMAR ESPINOSA P.  E-mail: opiedrahita2003 AT yahoo.com
  26 Uso libre
  27 //------------------------------------------------------------------//--//------*/
  28 #ifndef __REG922_H__
  29 #define __REG922_H__
  30
  31 //*  BYTE Registers  *//
  32 __sfr __at (0x80) P0     ;
  33 __sfr __at (0x90) P1     ;
  34 __sfr __at (0xB0) P3     ;
  35 __sfr __at (0xD0) PSW    ;
  36 __sfr __at (0xE0) ACC    ;
  37 __sfr __at (0xF0) B      ;
  38 __sfr __at (0x81) SP     ;
  39 __sfr __at (0x82) DPL    ;
  40 __sfr __at (0x83) DPH    ;
  41 __sfr __at (0x87) PCON   ;
  42 __sfr __at (0x88) TCON   ;
  43 __sfr __at (0x89) TMOD   ;
  44 __sfr __at (0x8A) TL0    ;
  45 __sfr __at (0x8B) TL1    ;
  46 __sfr __at (0x8C) TH0    ;
  47 __sfr __at (0x8D) TH1    ;
  48 __sfr __at (0xA8) IEN0   ;
  49 __sfr __at (0xB8) IP0    ;
  50 __sfr __at (0x98) SCON   ;
  51 __sfr __at (0x99) SBUF   ;
  52
  53
  54 __sfr __at (0xA2) AUXR1  ;
  55 __sfr __at (0xA9) SADDR  ;
  56 __sfr __at (0xB9) SADEN  ;
  57 __sfr __at (0xBE) BRGR0  ;
  58 __sfr __at (0xBF) BRGR1  ;
  59 __sfr __at (0xBD) BRGCON ;
  60 __sfr __at (0xAC) CMP1   ;
  61 __sfr __at (0xAD) CMP2   ;
  62 __sfr __at (0x95) DIVM   ;
  63 __sfr __at (0xE7) FMADRH ;
  64 __sfr __at (0xE6) FMADRL ;
  65 __sfr __at (0xE4) FMCON  ;
  66 __sfr __at (0xE5) FMDATA ;
  67 __sfr __at (0xDB) I2ADR  ;
  68 __sfr __at (0xD8) I2CON  ;
  69 __sfr __at (0xDA) I2DAT  ;
  70 __sfr __at (0xDD) I2SCLH ;
  71 __sfr __at (0xDC) I2SCLL ;
  72 __sfr __at (0xD9) I2STAT ;
  73 __sfr __at (0xF8) IP1    ;
  74 __sfr __at (0xF7) IP1H   ;
  75 __sfr __at (0x94) KBCON  ;
  76 __sfr __at (0x86) KBMASK ;
  77 __sfr __at (0x93) KBPATN ;
  78 __sfr __at (0x84) P0M1   ;
  79 __sfr __at (0x85) P0M2   ;
  80 __sfr __at (0x91) P1M1   ;
  81 __sfr __at (0x92) P1M2   ;
  82 __sfr __at (0xB1) P3M1   ;
  83 __sfr __at (0xB2) P3M2   ;
  84 __sfr __at (0xB5) PCONA  ;
  85 __sfr __at (0xF6) PT0AD  ;
  86 __sfr __at (0xDF) RSTSRC ;
  87 __sfr __at (0xD1) RTCCON ;
  88 __sfr __at (0xD2) RTCH   ;
  89 __sfr __at (0xD3) RTCL   ;
  90 __sfr __at (0xBA) SSTAT  ;
  91 __sfr __at (0x8F) TAMOD  ;
  92 __sfr __at (0x96) TRIM   ;
  93 __sfr __at (0xA7) WDCON  ;
  94 __sfr __at (0xC1) WDL    ;
  95 __sfr __at (0xC2) WFEED1 ;
  96 __sfr __at (0xC3) WFEED2 ;
  97 __sfr __at (0xB7) IP0H   ;
  98 __sfr __at (0xE8) IEN1   ;
  99
 100 /*  BIT Registers  */
 101 /*  PSW   */
 102 __sbit __at (0xD0) PSW_0   ;
 103 __sbit __at (0xD1) PSW_1   ;
 104 __sbit __at (0xD2) PSW_2   ;
 105 __sbit __at (0xD3) PSW_3   ;
 106 __sbit __at (0xD4) PSW_4   ;
 107 __sbit __at (0xD5) PSW_5   ;
 108 __sbit __at (0xD6) PSW_6   ;
 109 __sbit __at (0xD7) PSW_7   ;
 110
 111 #define CY    PSW_7
 112 #define AC    PSW_6
 113 #define F0    PSW_5
 114 #define RS1   PSW_4
 115 #define RS0   PSW_3
 116 #define OV    PSW_2
 117 #define F1    PSW_1
 118 #define P     PSW_0
 119
 120 /*  TCON  */
 121 __sbit __at (0x8F) TCON_7  ;
 122 __sbit __at (0x8E) TCON_6  ;
 123 __sbit __at (0x8D) TCON_5  ;
 124 __sbit __at (0x8C) TCON_4  ;
 125 __sbit __at (0x8B) TCON_3  ;
 126 __sbit __at (0x8A) TCON_2  ;
 127 __sbit __at (0x89) TCON_1  ;
 128 __sbit __at (0x88) TCON_0  ;
 129
 130 #define TF1   TCON_7
 131 #define TR1   TCON_6
 132 #define TF0   TCON_5
 133 #define TR0   TCON_4
 134 #define IE1   TCON_3
 135 #define IT1   TCON_2
 136 #define IE0   TCON_1
 137 #define IT0   TCON_0
 138
 139 /*  IEN0   */
 140 __sbit __at (0xAF) IEN0_7  ;
 141 __sbit __at (0xAE) IEN0_6  ;
 142 __sbit __at (0xAD) IEN0_5  ;
 143 __sbit __at (0xAC) IEN0_4  ;
 144 __sbit __at (0xAB) IEN0_3  ;
 145 __sbit __at (0xAA) IEN0_2  ;
 146 __sbit __at (0xA9) IEN0_1  ;
 147 __sbit __at (0xA8) IEN0_0  ;
 148
 149 #define EA    IEN0_7
 150 #define EWDRT IEN0_6
 151 #define EBO   IEN0_5
 152 #define ES    IEN0_4    // alternatively "ESR"
 153 #define ESR   IEN0_4
 154 #define ET1   IEN0_3
 155 #define EX1   IEN0_2
 156 #define ET0   IEN0_1
 157 #define EX0   IEN0_0
 158
 159 /*  IEN1   */
 160 __sbit __at (0xEA) IEN1_2  ;
 161 __sbit __at (0xE9) IEN1_1  ;
 162 __sbit __at (0xE8) IEN1_0  ;
 163
 164 #define EC    IEN1_2
 165 #define EKBI  IEN1_1
 166 #define EI2C  IEN1_0
 167
 168 /*  IP1   */
 169 __sbit __at (0xFE) IP1_6   ;
 170 __sbit __at (0xFA) IP1_2   ;
 171 __sbit __at (0xF9) IP1_1   ;
 172 __sbit __at (0xF8) IP1_0   ;
 173
 174 #define PST   IP1_6
 175 #define PC    IP1_2
 176 #define PKBI  IP1_1
 177 #define PI2C  IP1_0
 178
 179 /*  IP0   */
 180 __sbit __at (0xBE) IP0_6   ;
 181 __sbit __at (0xBD) IP0_5   ;
 182 __sbit __at (0xBC) IP0_4   ; // alternatively "PSR"
 183 __sbit __at (0xBB) IP0_3   ;
 184 __sbit __at (0xBA) IP0_2   ;
 185 __sbit __at (0xB9) IP0_1   ;
 186 __sbit __at (0xB8) IP0_0   ;
 187
 188 #define PWDRT IP0_6
 189 #define PBO   IP0_5
 190 #define PS    IP0_4      // alternatively "PSR"
 191 #define PSR   IP0_4
 192 #define PT1   IP0_3
 193 #define PX1   IP0_2
 194 #define PT0   IP0_1
 195 #define PX0   IP0_0
 196
 197 /*  SCON  */
 198 __sbit __at (0x98) SCON_0  ;
 199 __sbit __at (0x99) SCON_1  ;
 200 __sbit __at (0x9A) SCON_2  ;
 201 __sbit __at (0x9B) SCON_3  ;
 202 __sbit __at (0x9C) SCON_4  ;
 203 __sbit __at (0x9D) SCON_5  ;
 204 __sbit __at (0x9E) SCON_6  ;
 205 __sbit __at (0x9F) SCON_7  ;
 206
 207 #define SM0   SCON_7  // alternatively "FE"
 208 #define FE    SCON_7
 209 #define SM1   SCON_6
 210 #define SM2   SCON_5
 211 #define REN   SCON_4
 212 #define TB8   SCON_3
 213 #define RB8   SCON_2
 214 #define TI    SCON_1
 215 #define RI    SCON_0
 216
 217 /*  I2CON  */
 218 __sbit __at (0xDE) I2CON_6 ;
 219 __sbit __at (0xDD) I2CON_5 ;
 220 __sbit __at (0xDC) I2CON_4 ;
 221 __sbit __at (0xDB) I2CON_3 ;
 222 __sbit __at (0xDA) I2CON_2 ;
 223 __sbit __at (0xD8) I2CON_0 ;
 224
 225 #define I2EN  I2CON_6
 226 #define STA   I2CON_5
 227 #define STO   I2CON_4
 228 #define SI    I2CON_3
 229 #define AA    I2CON_2
 230 #define CRSEL I2CON_0
 231
 232 /*  P0    */
 233 __sbit __at (0x80) P0_0    ;
 234 __sbit __at (0x81) P0_1    ;
 235 __sbit __at (0x82) P0_2    ;
 236 __sbit __at (0x83) P0_3    ;
 237 __sbit __at (0x84) P0_4    ;
 238 __sbit __at (0x85) P0_5    ;
 239 __sbit __at (0x86) P0_6    ;
 240 __sbit __at (0x87) P0_7    ;
 241
 242 #define KB7   P0_7   // alternatively "T1"
 243 #define T1    P0_7
 244 #define KB6   P0_6   // alternatively "CMP_1"
 245 #define CMP_1 P0_6
 246 #define KB5   P0_5
 247 #define KB4   P0_4
 248 #define KB3   P0_3
 249 #define KB2   P0_2
 250 #define KB1   P0_1
 251 #define KB0   P0_0   // alternatively "CMP_2"
 252 #define CMP_2 P0_0
 253
 254 /*  P1  */
 255 __sbit __at (0x90) P1_0    ;
 256 __sbit __at (0x91) P1_1    ;
 257 __sbit __at (0x92) P1_2    ;
 258 __sbit __at (0x93) P1_3    ;
 259 __sbit __at (0x94) P1_4    ;
 260 __sbit __at (0x95) P1_5    ;
 261 __sbit __at (0x96) P1_6    ;
 262 __sbit __at (0x97) P1_7    ;
 263
 264 #define RST   P1_5
 265 #define INT1  P1_4
 266 #define INT0  P1_3   // alternatively "SDA"
 267 #define SDA   P1_3
 268 #define T0    P1_2   // alternatively "SCL"
 269 #define SCL   P1_2
 270 #define RxD   P1_1
 271 #define TxD   P1_0
 272
 273 /*  P3  */
 274 __sbit __at (0xB0)  P3_0   ;
 275 __sbit __at (0xB1)  P3_1   ;
 276
 277 #define XTAL1 P3_1
 278 #define XTAL2 P3_0
 279
 280 #endif