sdcc/device/include/mcs51/P89LPC925.h

   1 /*-------------------------------------------------------------------------
   2    P89LPC925.h - Register Declarations for NXP  P89LPC924 and P89LPC925
   3    (Based on datasheet Rev. 03 - 15 December 2004)
   4
   5    Copyright (C) 2007, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef REG_P89LPC925_H
  31 #define REG_P89LPC925_H
  32
  33 #include <compiler.h>
  34
  35 SFR(ACC, 0xE0); // Accumulator
  36    SBIT(ACC_7, 0xE0, 7);
  37    SBIT(ACC_6, 0xE0, 6);
  38    SBIT(ACC_5, 0xE0, 5);
  39    SBIT(ACC_4, 0xE0, 4);
  40    SBIT(ACC_3, 0xE0, 3);
  41    SBIT(ACC_2, 0xE0, 2);
  42    SBIT(ACC_1, 0xE0, 1);
  43    SBIT(ACC_0, 0xE0, 0);
  44
  45 SFR(ADCON1, 0x97); // A/D control register 1
  46    #define ENBI1   0x80
  47    #define ENADCI1 0x40
  48    #define TMM1    0x20
  49    #define EDGE1   0x10
  50    #define ADCI1   0x08
  51    #define ENADC1  0x04
  52    #define ADCS11  0x02
  53    #define ADCS10  0x01
  54
  55 SFR(ADINS, 0xA3); // A/D input select
  56    #define ADI13 0x80
  57    #define ADI12 0x40
  58    #define ADI11 0x20
  59    #define ADI10 0x10
  60
  61 SFR(ADMODA, 0xC0); // A/D mode register A
  62    #define BNDI1  0x80
  63    #define BURST1 0x40
  64    #define SCC1   0x20
  65    #define SCAN1  0x10
  66
  67 SFR(ADMODB, 0xA1); // A/D mode register B
  68    #define CLK2   0x80
  69    #define CLK1   0x40
  70    #define CLK0   0x20
  71    #define ENDAC1 0x08
  72    #define BSA1   0x02
  73
  74 SFR(AD1BH, 0xC4); // A/D_1 boundary high register
  75
  76 SFR(AD1BL, 0xBC); // A/D_1 boundary low register
  77
  78 SFR(AD1DAT0, 0xD5); // A/D_1 data register 0
  79
  80 SFR(AD1DAT1, 0xD6); // A/D_1 data register 1
  81
  82 SFR(AD1DAT2, 0xD7); // A/D_1 data register 2
  83
  84 SFR(AD1DAT3, 0xF5); // A/D_1 data register 3
  85
  86 SFR(AUXR1, 0xA2); // Auxiliary function register
  87    #define CLKLP 0x80
  88    #define EBRR  0x40
  89    #define ENT1  0x20
  90    #define ENT0  0x10
  91    #define SRST  0x08
  92    #define DPS   0x01
  93
  94 SFR(B, 0xF0); // B register
  95    SBIT(B_7, 0xF0, 7);
  96    SBIT(B_6, 0xF0, 6);
  97    SBIT(B_5, 0xF0, 5);
  98    SBIT(B_4, 0xF0, 4);
  99    SBIT(B_3, 0xF0, 3);
 100    SBIT(B_2, 0xF0, 2);
 101    SBIT(B_1, 0xF0, 1);
 102    SBIT(B_0, 0xF0, 0);
 103
 104 SFR(BRGR0, 0xBE); // Baud rate generator rate LOW
 105
 106 SFR(BRGR1, 0xBF); // Baud rate generator rate HIGH
 107
 108 SFR(BRGCON, 0xBD); // Baud rate generator control
 109    #define SBRGS 0x02
 110    #define BRGEN 0x01
 111
 112 SFR(CMP1, 0xAC); // Comparator1 control register
 113    #define CE1  0x20
 114    #define CP1  0x10
 115    #define CN1  0x08
 116    #define OE1  0x04
 117    #define CO1  0x02
 118    #define CMF1 0x01
 119
 120 SFR(CMP2, 0xAD); // Comparator2 control register
 121    #define CE2  0x20
 122    #define CP2  0x10
 123    #define CN2  0x08
 124    #define OE2  0x04
 125    #define CO2  0x02
 126    #define CMF2 0x01
 127
 128 SFR(DIVM, 0x95); // CPU clock divide-by-M control
 129
 130 SFR(DPH, 0x83); // Data pointer HIGH
 131
 132 SFR(DPL, 0x82); // Data pointer LOW
 133
 134 SFR(FMADRH, 0xE7); // Program Flash address HIGH
 135
 136 SFR(FMADRL, 0xE6); // Program Flash address LOW
 137
 138 SFR(FMCON, 0xE4); // Program Flash control (Read)
 139    #define BUSY 0x80
 140    #define HVA  0x08
 141    #define HVE  0x04
 142    #define SV  0x02
 143    #define OI  0x01
 144
 145 SFR(FMCON, 0xE4); // Program Flash control (Write)
 146    #define FMCMD_7 0x80
 147    #define FMCMD_6 0x40
 148    #define FMCMD_5 0x20
 149    #define FMCMD_4 0x10
 150    #define FMCMD_3 0x08
 151    #define FMCMD_2 0x04
 152    #define FMCMD_1 0x02
 153    #define FMCMD_0 0x01
 154
 155 SFR(FMDATA, 0xE5); // Program Flash data
 156
 157 SFR(I2ADR, 0xDB); // I2C slave address register
 158    #define I2ADR_6 0x80
 159    #define I2ADR_5 0x40
 160    #define I2ADR_4 0x20
 161    #define I2ADR_3 0x10
 162    #define I2ADR_2 0x08
 163    #define I2ADR_1 0x04
 164    #define I2ADR_0 0x02
 165    #define GC      0x01
 166
 167 SFR(I2CON, 0xD8); // I2C control register
 168    SBIT(I2EN,  0xD8, 6);
 169    SBIT(STA,   0xD8, 5);
 170    SBIT(STO,   0xD8, 4);
 171    SBIT(SI,    0xD8, 3);
 172    SBIT(AA,    0xD8, 2);
 173    SBIT(CRSEL, 0xD8, 0);
 174
 175 SFR(I2DAT, 0xDA); // I2C data register
 176
 177 SFR(I2SCLH, 0xDD); // Serial clock generator/SCL duty cycle register HIGH
 178
 179 SFR(I2SCLL, 0xDC); // Serial clock generator/SCL duty cycle register LOW
 180
 181 SFR(I2STAT, 0xD9); // I2C status register
 182    #define STA_4 0x80
 183    #define STA_3 0x40
 184    #define STA_2 0x20
 185    #define STA_1 0x10
 186    #define STA_0 0x08
 187
 188 SFR(IEN0, 0xA8); // Interrupt enable 0
 189    SBIT(EA,    0xA8, 7);
 190    SBIT(EWDRT, 0xA8, 6);
 191    SBIT(EBO,   0xA8, 5);
 192    SBIT(ES,    0xA8, 4);
 193    SBIT(ESR,   0xA8, 4);
 194    SBIT(ET1,   0xA8, 3);
 195    SBIT(EX1,   0xA8, 2);
 196    SBIT(ET0,   0xA8, 1);
 197    SBIT(EX0,   0xA8, 0);
 198
 199 SFR(IEN1, 0xE8); // Interrupt enable 1
 200    SBIT(EAD,  0xE8, 7);
 201    SBIT(EST,  0xE8, 6);
 202    SBIT(EC,   0xE8, 2);
 203    SBIT(EKBI, 0xE8, 1);
 204    SBIT(EI2C, 0xE8, 0);
 205
 206 SFR(IP0, 0xB8); // Interrupt priority 0
 207    SBIT(PWDRT, 0xB8, 6);
 208    SBIT(PBO,   0xB8, 5);
 209    SBIT(PS,    0xB8, 4);
 210    SBIT(PSR,   0xB8, 4);
 211    SBIT(PT1,   0xB8, 3);
 212    SBIT(PX1,   0xB8, 2);
 213    SBIT(PT0,   0xB8, 1);
 214    SBIT(PX0,   0xB8, 0);
 215
 216 SFR(IP0H, 0xB7); // Interrupt priority 0 HIGH
 217    #define PWDRTH 0x40
 218    #define PBOH   0x20
 219    #define PSH    0x10
 220    #define PSRH   0x10
 221    #define PT1H   0x08
 222    #define PX1H   0x04
 223    #define PT0H   0x02
 224    #define PX0H   0x01
 225
 226 SFR(IP1, 0xF8); // Interrupt priority 1
 227    SBIT(PAD,  0xF8, 7);
 228    SBIT(PST,  0xF8, 6);
 229    SBIT(PC,   0xF8, 2);
 230    SBIT(PKBI, 0xF8, 1);
 231    SBIT(PI2C, 0xF8, 0);
 232
 233 SFR(IP1H, 0xF7); // Interrupt priority 1 HIGH
 234    #define PADH  0x80
 235    #define PSTH  0x40
 236    #define PCH   0x04
 237    #define PKBIH 0x02
 238    #define PI2CH 0x01
 239
 240 SFR(KBCON, 0x94); // Keypad control register
 241    #define PATN_SEL 0x02 //Pattern Matching Polarity selection
 242    #define KBIF     0x01 // Keypad Interrupt Flag
 243
 244 SFR(KBMASK, 0x86); // Keypad interrupt register mask
 245
 246 SFR(KBPATN, 0x93); // Keypad pattern register
 247
 248 SFR(P0, 0x80); // Port 0
 249    SBIT(P0_7, 0x80, 7);
 250    SBIT(P0_6, 0x80, 6);
 251    SBIT(P0_5, 0x80, 5);
 252    SBIT(P0_4, 0x80, 4);
 253    SBIT(P0_3, 0x80, 3);
 254    SBIT(P0_2, 0x80, 2);
 255    SBIT(P0_1, 0x80, 1);
 256    SBIT(P0_0, 0x80, 0);
 257    //P0 alternate pin functions
 258    SBIT(T1,     0x80, 7);
 259    SBIT(CMP_1,  0x80, 6); //Should be CMP1 but there is SFR with that name
 260    SBIT(CMPREF, 0x80, 5);
 261    SBIT(CIN1A,  0x80, 4);
 262    SBIT(CIN1B,  0x80, 3);
 263    SBIT(CIN2A,  0x80, 2);
 264    SBIT(CIN2B,  0x80, 1);
 265    SBIT(CMP_2,  0x80, 0); //Should be CMP2 but there is SFR with that name
 266    //More P0 alternate pin functions
 267    SBIT(KB7, 0x80, 7);
 268    SBIT(KB6, 0x80, 6);
 269    SBIT(KB5, 0x80, 5);
 270    SBIT(KB4, 0x80, 4);
 271    SBIT(KB3, 0x80, 3);
 272    SBIT(KB2, 0x80, 2);
 273    SBIT(KB1, 0x80, 1);
 274    SBIT(KB0, 0x80, 0);
 275
 276 SFR(P1, 0x90); // Port 1
 277    SBIT(P1_7, 0x90, 7);
 278    SBIT(P1_6, 0x90, 6);
 279    SBIT(P1_5, 0x90, 5);
 280    SBIT(P1_4, 0x90, 4);
 281    SBIT(P1_3, 0x90, 3);
 282    SBIT(P1_2, 0x90, 2);
 283    SBIT(P1_1, 0x90, 1);
 284    SBIT(P1_0, 0x90, 0);
 285    //P1 alternate pin functions
 286    SBIT(RST,  0x90, 5);
 287    SBIT(INT1, 0x90, 4);
 288    SBIT(INT0, 0x90, 3);
 289    SBIT(SDA,  0x90, 3);
 290    SBIT(T0,   0x90, 2);
 291    SBIT(SCL,  0x90, 2);
 292    SBIT(RXD,  0x90, 1);
 293    SBIT(TXD,  0x90, 0);
 294
 295 SFR(P3, 0xB0); // Port 3
 296    SBIT(P3_1, 0xB0, 1);
 297    SBIT(P3_0, 0xB0, 0);
 298    SBIT(XTAL1, 0xB0, 1);
 299    SBIT(XTAL2, 0xB0, 0);
 300
 301 SFR(P0M1, 0x84); // Port0 output mode1
 302    #define P0M1_7 0x80
 303    #define P0M1_6 0x40
 304    #define P0M1_5 0x20
 305    #define P0M1_4 0x10
 306    #define P0M1_3 0x08
 307    #define P0M1_2 0x04
 308    #define P0M1_1 0x02
 309    #define P0M1_0 0x01
 310
 311 SFR(P0M2, 0x85); // Port0 output mode2
 312    #define P0M2_7 0x80
 313    #define P0M2_6 0x40
 314    #define P0M2_5 0x20
 315    #define P0M2_4 0x10
 316    #define P0M2_3 0x08
 317    #define P0M2_2 0x04
 318    #define P0M2_1 0x02
 319    #define P0M2_0 0x01
 320
 321 SFR(P1M1, 0x91); // Port1 output mode1
 322    #define P1M1_7 0x80
 323    #define P1M1_6 0x40
 324    #define P1M1_4 0x10
 325    #define P1M1_3 0x08
 326    #define P1M1_2 0x04
 327    #define P1M1_1 0x02
 328    #define P1M1_0 0x01
 329
 330 SFR(P1M2, 0x92); // Port1 output mode2
 331    #define P1M2_7 0x80
 332    #define P1M2_6 0x40
 333    #define P1M2_4 0x10
 334    #define P1M2_3 0x08
 335    #define P1M2_2 0x04
 336    #define P1M2_1 0x02
 337    #define P1M2_0 0x01
 338
 339 SFR(P3M1, 0xB1); // Port3 output mode1
 340    #define P3M1_1 0x02
 341    #define P3M1_0 0x01
 342
 343 SFR(P3M2, 0xB2); // Port3 output mode2
 344    #define P3M2_1 0x02
 345    #define P3M2_0 0x01
 346
 347 SFR(PCON, 0x87); // Power control register
 348    #define SMOD1 0x80
 349    #define SMOD0 0x40
 350    #define BOPD  0x20
 351    #define BOI   0x10
 352    #define GF1   0x08
 353    #define GF0   0x04
 354    #define PMOD1 0x02
 355    #define PMOD0 0x01
 356
 357 SFR(PCONA, 0xB5); // Power control register A
 358    #define RTCPD 0x80
 359    #define VCPD  0x20
 360    #define ADPD  0x10
 361    #define I2PD  0x08
 362    #define SPD   0x02
 363
 364 SFR(PSW, 0xD0); // Program status word
 365    SBIT(CY,  0xD0, 7);
 366    SBIT(AC,  0xD0, 6);
 367    SBIT(F0,  0xD0, 5);
 368    SBIT(RS1, 0xD0, 4);
 369    SBIT(RS0, 0xD0, 3);
 370    SBIT(OV,  0xD0, 2);
 371    SBIT(F1,  0xD0, 1);
 372    SBIT(P,   0xD0, 0);
 373
 374 SFR(PT0AD, 0xF6); // Port0 digital input disable
 375    #define PT0AD_5 0x20
 376    #define PT0AD_4 0x10
 377    #define PT0AD_3 0x08
 378    #define PT0AD_2 0x04
 379    #define PT0AD_1 0x02
 380
 381 SFR(RSTSRC, 0xDF); // Reset source register
 382    #define BOF 0x20
 383    #define POF 0x10
 384    #define R_BK 0x08
 385    #define R_WD 0x04
 386    #define R_SF 0x02
 387    #define R_EX 0x01
 388
 389 SFR(RTCCON, 0xD1); // Real-time clock control
 390    #define RTCF  0x80
 391    #define RTCS1 0x40
 392    #define RTCS0 0x20
 393    #define ERTC  0x02
 394    #define RTCEN 0x01
 395
 396 SFR(RTCH, 0xD2); // Real-time clock register HIGH
 397
 398 SFR(RTCL, 0xD3); // Real-time clock register LOW
 399
 400 SFR(SADDR, 0xA9); // Serial port address register
 401
 402 SFR(SADEN, 0xB9); // Serial port address enable
 403
 404 SFR(SBUF, 0x99); // Serial Port data buffer register
 405
 406 SFR(SCON, 0x98); // Serial port control
 407    SBIT(FE,  0x98, 7);
 408    SBIT(SM0, 0x98, 7);
 409    SBIT(SM1, 0x98, 6);
 410    SBIT(SM2, 0x98, 5);
 411    SBIT(REN, 0x98, 4);
 412    SBIT(TB8, 0x98, 3);
 413    SBIT(RB8, 0x98, 2);
 414    SBIT(TI,  0x98, 1);
 415    SBIT(RI,  0x98, 0);
 416
 417 SFR(SSTAT, 0xBA); // Serial port extended status register
 418    #define DBMOD  0x80
 419    #define INTLO  0x40
 420    #define CIDIS  0x20
 421    #define DBISEL 0x10
 422    #define FE     0x08
 423    #define BR     0x04
 424    #define OE     0x02
 425    #define STINT  0x01
 426
 427 SFR(SP, 0x81); // Stack pointer
 428
 429 SFR(TAMOD, 0x8F); // Timer0 and 1 auxiliary mode
 430    #define T1M2 0x10
 431    #define T0M2 0x01
 432
 433 SFR(TCON, 0x88); // Timer0 and 1 control
 434    SBIT(TF1, 0x88, 7);
 435    SBIT(TR1, 0x88, 6);
 436    SBIT(TF0, 0x88, 5);
 437    SBIT(TR0, 0x88, 4);
 438    SBIT(IE1, 0x88, 3);
 439    SBIT(IT1, 0x88, 2);
 440    SBIT(IE0, 0x88, 1);
 441    SBIT(IT0, 0x88, 0);
 442
 443 SFR(TH0, 0x8C); // Timer0 HIGH
 444
 445 SFR(TH1, 0x8D); // Timer 1 HIGH
 446
 447 SFR(TL0, 0x8A); // Timer 0 LOW
 448
 449 SFR(TL1, 0x8B); // Timer 1 LOW
 450
 451 SFR(TMOD, 0x89); // Timer0 and 1 mode
 452    #define T1GATE 0x80
 453    #define T1C_T  0x40
 454    #define T1M1   0x20
 455    #define T1M0   0x10
 456    #define T0GATE 0x08
 457    #define T0C_T  0x04
 458    #define T0M1   0x02
 459    #define T0M0   0x01
 460
 461 SFR(TRIM, 0x96); // Internal oscillator trim register
 462    #define RCCLK  0x80
 463    #define ENCLK  0x40
 464    #define TRIM_5 0x20
 465    #define TRIM_4 0x10
 466    #define TRIM_3 0x08
 467    #define TRIM_2 0x04
 468    #define TRIM_1 0x02
 469    #define TRIM_0 0x01
 470
 471 SFR(WDCON, 0xA7); // Watchdog control register
 472    #define PRE2  0x80 //Watchdog Prescaler Tap Select bit 2
 473    #define PRE1  0x40 //Watchdog Prescaler Tap Select bit 1
 474    #define PRE0  0x20 //Watchdog Prescaler Tap Select bit 0
 475    #define WDRUN 0x04 //Watchdog Run Control
 476    #define WDTOF 0x02 //Watchdog Timer Time-Out Flag
 477    #define WDCLK 0x01 //Watchdog input clock select
 478
 479 SFR(WDL, 0xC1); // Watchdog load
 480
 481 SFR(WFEED1, 0xC2); // Watchdog feed 1
 482
 483 SFR(WFEED2, 0xC3); // Watchdog feed 2
 484
 485 #endif /*REG_P89LPC925_H*/