sdcc/device/include/mcs51/SST89x5xRDx.h

   1 /*-------------------------------------------------------------------------
   2    SST89x5xRDx.h Register Declarations for SST SST89E516RD2, ST89E516RD,
   3    SST89V516RD2, and SST89V516RD Processors
   4    (Based on datasheed S71273-03-000 1/07)
   5
   6    Copyright (C) 2007, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   7
   8    This library is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published by the
  10    Free Software Foundation; either version 2, or (at your option) any
  11    later version.
  12
  13    This library is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this library; see the file COPYING. If not, write to the
  20    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  21    MA 02110-1301, USA.
  22
  23    As a special exception, if you link this library with other files,
  24    some of which are compiled with SDCC, to produce an executable,
  25    this library does not by itself cause the resulting executable to
  26    be covered by the GNU General Public License. This exception does
  27    not however invalidate any other reasons why the executable file
  28    might be covered by the GNU General Public License.
  29 -------------------------------------------------------------------------*/
  30
  31 #ifndef REG_SST89x5xRDx_H
  32 #define REG_SST89x5xRDx_H
  33
  34 #include <compiler.h>
  35
  36 // From TABLE 3-5: CPU related SFRs
  37
  38 SFR(ACC, 0xE0); // Accumulator
  39    SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0
  40    SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1
  41    SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2
  42    SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3
  43    SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4
  44    SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5
  45    SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6
  46    SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7
  47 SFR(B,   0xF0); // B Register
  48    SBIT(B_0, 0xF0, 0); // Register B bit 0
  49    SBIT(B_1, 0xF0, 1); // Register B bit 1
  50    SBIT(B_2, 0xF0, 2); // Register B bit 2
  51    SBIT(B_3, 0xF0, 3); // Register B bit 3
  52    SBIT(B_4, 0xF0, 4); // Register B bit 4
  53    SBIT(B_5, 0xF0, 5); // Register B bit 5
  54    SBIT(B_6, 0xF0, 6); // Register B bit 6
  55    SBIT(B_7, 0xF0, 7); // Register B bit 7
  56 SFR(PSW, 0xD0); // Program Status Word
  57    SBIT(P,   0xD0, 0); // Parity Flag
  58    SBIT(F1,  0xD0, 1); // User-Defined Flag
  59    SBIT(OV,  0xD0, 2); // Overflow Flag
  60    SBIT(RS0, 0xD0, 3); // Register Bank Select 0
  61    SBIT(RS1, 0xD0, 4); // Register Bank Select 1
  62    SBIT(F0,  0xD0, 5); // User-Defined Flag
  63    SBIT(AC,  0xD0, 6); // Auxiliary Carry Flag
  64    SBIT(CY,  0xD0, 7); // Carry Flag
  65 SFR(SP,  0x81); // Stack Pointer
  66 SFR(DPL, 0x82); // Data Pointer Low
  67 SFR(DPH, 0x83); // Data Pointer High
  68 SFR(IE,  0xA8); // Interrupt Enable
  69    SBIT(EA,   0xA8, 7); // Global Interrupt Enable
  70    SBIT(EC,   0xA8, 6); // PCA Interrupt Enable
  71    SBIT(ET2,  0xA8, 5); // Timer 2 Interrupt Enable
  72    SBIT(ES,   0xA8, 4); // Serial Interrupt Enable
  73    SBIT(ET1,  0xA8, 3); // Timer 1 Interrupt Enable
  74    SBIT(EX1,  0xA8, 2); // External 1 Interrupt Enable
  75    SBIT(ET0,  0xA8, 1); // Timer 0 Interrupt Enable
  76    SBIT(EX0,  0xA8, 0); // External 0 Interrupt Enable
  77 SFR(IEA, 0xE8); // Interrupt Enable A
  78    SBIT(EBO,  0xE8, 3); // Brown-out Interrupt Enable. (Vector is 0x00b4)
  79 SFR(IP,  0xB8); // Interrupt Priority Reg
  80    SBIT(PPC,  0xB8, 6); // PCA interrupt priority bit
  81    SBIT(PT2,  0xB8, 5); // Timer 2 interrupt priority bit
  82    SBIT(PS,   0xB8, 4); // Serial Port interrupt priority bit
  83    SBIT(PT1,  0xB8, 3); // Timer 1 interrupt priority bit
  84    SBIT(PX1,  0xB8, 2); // External interrupt 1 priority bit
  85    SBIT(PT0,  0xB8, 1); // Timer 0 interrupt priority bit
  86    SBIT(PX0,  0xB8, 0); // External interrupt 0 priority bit
  87 SFR(IPH, 0xB7); // Interrupt Priority Reg High
  88    #define PPCH 0x40   // PCA Interrupt Priority High Bit
  89    #define PT2H 0x20   // Timer 2 Interrupt Interrupt Priority High Bit
  90    #define PSH  0x10   // Serial Port Interrupt Priority High Bit
  91    #define PT1H 0x08   // Timer 1 Interrupt Priority High Bit
  92    #define PX1H 0x04   // External Interrupt 1 Priority High Bit
  93    #define PT0H 0x02   // Timer 0 Interrupt Priority High Bit
  94    #define PX0H 0x01   // External Interrupt 0 Priority High Bit
  95 SFR(IP1, 0xF8); // Interrupt Priority Reg A
  96    SBIT(PBO, 0xF8, 4);   // Brown-out interrupt priority bit
  97    SBIT(PX2, 0xF8, 1);   // External Interrupt 2 priority bit
  98    SBIT(PX3, 0xF8, 2);   // External Interrupt 3 priority bit
  99 SFR(IP1H, 0xF7); // Interrupt Priority Reg A High
 100    #define PBOH 0x08   // Brown-out Interrupt priority bit high
 101    #define PX2H 0x02   // External Interrupt 2 priority bit high
 102    #define PX3H 0x04   // External Interrupt 3 priority bit high
 103 SFR(PCON, 0x87); // Power Control
 104    #define SMOD1 0x80  // Double Baud rate bit
 105    #define SMOD0 0x40  // FE/SM0 Selection bit
 106    #define BOF   0x20  // Brown-out detection status bit
 107    #define POF   0x10  // Power-on reset status bit
 108    #define GF1   0x08  // General-purpose flag bit
 109    #define GF0   0x04  // General-purpose flag bit
 110    #define PD    0x02  // Power-down bit
 111    #define IDL   0x01  // Idle mode bit
 112 SFR(AUXR, 0x8E); // Auxiliary Reg
 113    #define EXTRAM 0x02 // Internal/External RAM access
 114    #define AO     0x01 // Disable/Enable ALE
 115 SFR(AUXR1, 0xA2); // Auxiliary Reg 1
 116    #define GF2    0x08 // General purpose user-defined flag
 117    #define DPS    0x01 // DPTR registers select bit
 118 SFR(XICON, 0xAE); // External Interrupt Control
 119    #define EX2 0x04
 120    #define IE2 0x02
 121    #define IT2 0x01
 122    #define EX3 0x40
 123    #define IE3 0x20
 124    #define IT3 0x10
 125
 126 // TABLE 3-6: Flash Memory Programming SFRs
 127
 128 SFR(SFCF, 0xB1); // SuperFlash Configuration
 129    #define IAPEN  0x40 // Enable IAP operation
 130    #define SWR    0x02 // Software Reset
 131    #define BSEL   0x01 // Program memory block switching bit
 132 SFR(SFCM, 0xB2); // SuperFlash Command
 133    #define FIE                 0x80 // Flash Interrupt Enable
 134    #define CHIP_ERASE          0x01
 135    #define SECTOR_ERASE        0x0B
 136    #define BLOCK_ERASE         0x0D
 137    #define BYTE_VERIFY         0x0C
 138    #define BYTE_PROGRAM        0x0E
 139    #define PROG_SB1            0x0F
 140    #define PROG_SB2            0x03
 141    #define PROG_SB3            0x05
 142    #define PROG_SC0            0x09
 143    #define ENABLE_CLOCK_DOUBLE 0x08
 144 SFR(SFAL, 0xB3); // SuperFlash Address Low Register - A7 to A0
 145 SFR(SFAH, 0xB4); // SuperFlash Address High Register - A15 to A8
 146 SFR(SFDT, 0xB5); // SuperFlash Data Register
 147 SFR(SFST, 0xB6); // SuperFlash Status
 148    #define SB1_i      0x80 // Security Bit 1 status (inverse of SB1 bit)
 149    #define SB2_i      0x40 // Security Bit 2 status (inverse of SB2 bit)
 150    #define SB3_i      0x20 // Security Bit 3 status (inverse of SB3 bit)
 151    #define EDC_i      0x08 // Double Clock Status
 152    #define FLASH_BUSY 0x04 // Flash operation completion polling bit
 153
 154 // TABLE 3-7: Watchdog Timer SFRs
 155
 156 SFR(WDTC, 0xC0); // Watchdog Timer Control
 157    SBIT(WDOUT, 0xC0, 4); // Watchdog output enable
 158    SBIT(WDRE,  0xC0, 3); // Watchdog timer reset enable
 159    SBIT(WDTS,  0xC0, 2); // Watchdog timer reset flag
 160    SBIT(WDT,   0xC0, 1); // Watchdog timer refresh
 161    SBIT(SWDT,  0xC0, 0); // Start watchdog timer
 162 SFR(WDTD, 0x85); // Watchdog Timer Data/Reload
 163
 164 // TABLE 3-8: Timer/Counters SFRs
 165
 166 SFR(TMOD,   0x89); // Timer/Counter Mode Control GATE C/T# M1 M0 GATE C/T# M1 M0
 167    #define GATE1 0x80 // External enable for timer 1
 168    #define C_T1  0x40 // Timer or counter select for timer 1
 169    #define M1_1  0x20 // Operation mode bit 1 for timer 1
 170    #define M0_1  0x10 // Operation mode bit 0 for timer 1
 171    #define GATE0 0x08 // External enable for timer 0
 172    #define C_T0  0x04 // Timer or counter select for timer 0
 173    #define M1_0  0x02 // Operation mode bit 1 for timer 0
 174    #define M0_0  0x01 // Operation mode bit 0 for timer 0
 175 SFR(TCON,   0x88); // Timer/Counter Control  TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
 176    SBIT(TF1, 0x88, 7); // Timer 1 overflow flag
 177    SBIT(TR1, 0x88, 6); // Timer 1 run control flag
 178    SBIT(TF0, 0x88, 5); // Timer 0 overflow flag
 179    SBIT(TR0, 0x88, 4); // Timer 0 run control flag
 180    SBIT(IE1, 0x88, 3); // Interrupt 1 flag
 181    SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit
 182    SBIT(IE0, 0x88, 1); // Interrupt 0 flag
 183    SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit
 184 SFR(TH0,   0x8C); // Timer 0 MSB
 185 SFR(TL0,   0x8A); // Timer 0 LSB
 186 SFR(TH1,   0x8D); // Timer 1 MSB
 187 SFR(TL1,   0x8B); // Timer 1 LSB
 188 SFR(T2CON, 0xC8); // Timer / Counter 2 Control
 189    SBIT(TF2,   0xC8, 7); // Timer 2 overflow flag
 190    SBIT(EXF2,  0xC8, 6); // Timer 2 external flag
 191    SBIT(RCLK,  0xC8, 5); // Receive clock flag
 192    SBIT(TCLK,  0xC8, 4); // Transmit clock flag
 193    SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag
 194    SBIT(TR2,   0xC8, 2); // Start/stop control for timer 2
 195    SBIT(C_T2,  0xC8, 1); // Timer or coutner select
 196    SBIT(CP_RL2,0xC8, 0); // Capture/reload flag
 197 SFR(T2MOD,  0xC9); // Timer 2 Mode Control
 198    #define DCEN  0x02 // Down count enable bit
 199    #define T2OE  0x01 // Timer 2 output enable bit
 200 SFR(TH2,    0xCD); // Timer 2 MSB
 201 SFR(TL2,    0xCC); // Timer 2 LSB
 202 SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB
 203 SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB
 204
 205 // TABLE 3-9: Interface SFRs
 206
 207 SFR(SBUF, 0x99); // Serial Data Buffer
 208 SFR(SCON, 0x98); // Serial Port Control
 209    SBIT(FE,  0x98, 7); // Framing Error when reading, SM0 when writing
 210    SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0
 211    SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1
 212    SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2
 213    SBIT(REN, 0x98, 4); // Enables serial reception
 214    SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3
 215    SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received
 216    SBIT(TI,  0x98, 1); // Transmit interrupt flag
 217    SBIT(RI,  0x98, 0); // Receive interrupt flag
 218 SFR(SADDR, 0xA9); // Slave Address
 219 SFR(SADEN, 0xB9); // Slave Address Mask
 220 SFR(SPCR,  0xD5); // SPI Control Register
 221    #define SPIE 0x80 // If both SPIE and ES are set to one, SPI interrupts are enabled
 222    #define SPE  0x40 // SPI enable bit.  When set enables SPI
 223    #define DORD 0x20 // Data trans. order. 0=MSB first; 1=LSB first
 224    #define MSTR 0x10 // 1=master mode.  0=slave mode
 225    #define CPOL 0x08 // 1=SCK is high when idle (active low), 0=SCK is low when idle (active high)
 226    #define CPHA 0x04 // 1=shift triggered on the trailing edge of SCK.  0=shift trig. on leading edge
 227    #define SPR1 0x02 // SPI Clork Rate select bit 1
 228    #define SPR0 0x01 // SPI Clork Rate select bit 0
 229                      // 00 = Fosc/4
 230                      // 01 = Fosc/16
 231                      // 10 = Fosc/64
 232                      // 11 = Fosc/128
 233 SFR(SPSR, 0xAA); // SPI Status Register
 234    #define SPIF 0x80 // SPI interrupt flag
 235    #define WCOL 0x40 // Write collision Flag
 236 SFR(SPDR, 0x86); // SPI Data Register
 237 SFR(P0, 0x80); // Port 0
 238    SBIT(P0_0, 0x80, 0); // Port 0 bit 0
 239    SBIT(P0_1, 0x80, 1); // Port 0 bit 1
 240    SBIT(P0_2, 0x80, 2); // Port 0 bit 2
 241    SBIT(P0_3, 0x80, 3); // Port 0 bit 3
 242    SBIT(P0_4, 0x80, 4); // Port 0 bit 4
 243    SBIT(P0_5, 0x80, 5); // Port 0 bit 5
 244    SBIT(P0_6, 0x80, 6); // Port 0 bit 6
 245    SBIT(P0_7, 0x80, 7); // Port 0 bit 7
 246 SFR(P1, 0x90); // Port 1
 247    SBIT(P1_0, 0x90, 0); // Port 1 bit 0
 248    SBIT(P1_1, 0x90, 1); // Port 1 bit 1
 249    SBIT(P1_2, 0x90, 2); // Port 1 bit 2
 250    SBIT(P1_3, 0x90, 3); // Port 1 bit 3
 251    SBIT(P1_4, 0x90, 4); // Port 1 bit 4
 252    SBIT(P1_5, 0x90, 5); // Port 1 bit 5
 253    SBIT(P1_6, 0x90, 6); // Port 1 bit 6
 254    SBIT(P1_7, 0x90, 7); // Port 1 bit 7
 255    // Alternate names
 256    SBIT(T2,   0x90, 0); // Port 1 bit 0
 257    SBIT(T2EX, 0x90, 1); // Port 1 bit 1
 258    SBIT(ECI,  0x90, 2); // Port 1 bit 2
 259    SBIT(CEX0, 0x90, 3); // Port 1 bit 3
 260    SBIT(CEX1, 0x90, 4); // Port 1 bit 4
 261    SBIT(CEX2, 0x90, 5); // Port 1 bit 5
 262    SBIT(CEX3, 0x90, 6); // Port 1 bit 6
 263    SBIT(CEX4, 0x90, 7); // Port 1 bit 7
 264    // More alternate names
 265    SBIT(SS,   0x90, 4); // Port 1 bit 4
 266    SBIT(MOSI, 0x90, 5); // Port 1 bit 5
 267    SBIT(MISO, 0x90, 6); // Port 1 bit 6
 268    SBIT(SCK,  0x90, 7); // Port 1 bit 7
 269 SFR(P2, 0xA0); // Port 2
 270    SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
 271    SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
 272    SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
 273    SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
 274    SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
 275    SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
 276    SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
 277    SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
 278 SFR(P3, 0xB0); // Port 3
 279    SBIT(P3_0, 0xB0, 0); // Port 2 bit 0
 280    SBIT(P3_1, 0xB0, 1); // Port 2 bit 1
 281    SBIT(P3_2, 0xB0, 2); // Port 2 bit 2
 282    SBIT(P3_3, 0xB0, 3); // Port 2 bit 3
 283    SBIT(P3_4, 0xB0, 4); // Port 2 bit 4
 284    SBIT(P3_5, 0xB0, 5); // Port 2 bit 5
 285    SBIT(P3_6, 0xB0, 6); // Port 2 bit 6
 286    SBIT(P3_7, 0xB0, 7); // Port 2 bit 7
 287    // Alternate names
 288    SBIT(RXD,  0xB0, 0); // Port 2 bit 0
 289    SBIT(TXD,  0xB0, 1); // Port 2 bit 1
 290    SBIT(INT0, 0xB0, 2); // Port 2 bit 2
 291    SBIT(INT1, 0xB0, 3); // Port 2 bit 3
 292    SBIT(T0,   0xB0, 4); // Port 2 bit 4
 293    SBIT(T1,   0xB0, 5); // Port 2 bit 5
 294    SBIT(WR,   0xB0, 6); // Port 2 bit 6
 295    SBIT(RD,   0xB0, 7); // Port 2 bit 7
 296 SFR(P4, 0xA5); // Port 4 - not bit addressable
 297    #define P4_0 0x01
 298    #define P4_1 0x02
 299    #define P4_2 0x04
 300    #define P4_3 0x08
 301
 302 // TABLE 3-10: PCA SFRs
 303
 304 SFR(CH, 0xF9); // PCA Timer/Counter High
 305 SFR(CL, 0xE9); // PCA Timer/Counter Low
 306 SFR(CCON, 0xD8); // PCA Timer/Counter Control Register  CF CR - CCF4 CCF3 CCF2 CCF1 CCF0 00x00000b
 307    SBIT(CF,   0xD8, 7); // PCA Counter overflow flag
 308    SBIT(CR,   0xD8, 6); // PCA Counter Run Control Bit
 309    SBIT(CCF4, 0xD8, 4); // PCA Module 4 Interrupt Flag
 310    SBIT(CCF3, 0xD8, 3); // PCA Module 3 Interrupt Flag
 311    SBIT(CCF2, 0xD8, 2); // PCA Module 2 Interrupt Flag
 312    SBIT(CCF1, 0xD8, 1); // PCA Module 1 Interrupt Flag
 313    SBIT(CCF0, 0xD8, 0); // PCA Module 0 Interrupt Flag
 314 SFR(CMOD, 0xD9); // PCA Timer/Counter Mode Register
 315    #define CIDL 0x80 // CIDL=0 program the PCA counter to work during idle mode
 316    #define WDTE 0x40 // Watchdog Timer Enable
 317    #define CPS1 0x04 // PCA Count Pulse Select bit 1
 318    #define CPS0 0x02 // PCA Count Pulse Select bit 0
 319                      // 00=Internal clock, Fosc/6
 320                      // 01=Internal clock, Fosc/6
 321                      // 10=Timer 0 overflow
 322                      // 11=External clock at ECI/P1.2 pin (max rate=Fosc/4)
 323    #define ECF 0x01  // PCA Enable Counter Overflow Interrupt
 324 SFR(CCAP0H, 0xFA); // PCA Module 0 Compare/Capture Register High
 325 SFR(CCAP0L, 0xEA); // PCA Module 0 Compare/Capture Register Low
 326 SFR(CCAP1H, 0xFB); // PCA Module 1 Compare/Capture Register High
 327 SFR(CCAP1L, 0xEB); // PCA Module 1 Compare/Capture Register Low
 328 SFR(CCAP2H, 0xFC); // PCA Module 2 Compare/Capture Register High
 329 SFR(CCAP2L, 0xEC); // PCA Module 2 Compare/Capture Register Low
 330 SFR(CCAP3H, 0xFD); // PCA Module 3 Compare/Capture Register High
 331 SFR(CCAP3L, 0xED); // PCA Module 3 Compare/Capture Register Low
 332 SFR(CCAP4H, 0xFE); // PCA Module 4 Compare/Capture Register High
 333 SFR(CCAP4L, 0xEE); // PCA Module 4 Compare/Capture Register Low
 334 SFR(CCAPM0, 0xDA); // PCA Compare/Capture Module 0 Mode Register
 335 SFR(CCAPM1, 0xDB); // PCA Compare/Capture Module 1 Mode Register
 336 SFR(CCAPM2, 0xDC); // PCA Compare/Capture Module 2 Mode Register
 337 SFR(CCAPM3, 0xDD); // PCA Compare/Capture Module 3 Mode Register
 338 SFR(CCAPM4, 0xDE); // PCA Compare/Capture Module 4 Mode Register
 339 // The preceding five registers have the following bits:
 340    #define ECOM 0x40 // Enable Comparator
 341    #define CAPP 0x20 // 1=enables positive edge capture
 342    #define CAPN 0x10 // 1=enables negative edge capture
 343    #define MAT  0x08 // When counter matches sets CCFn bit causing and interrupt
 344    #define TOG  0x04 // Toggle output on match
 345    #define PWM  0x02 // Pulse width modulation mode
 346    #define ECCF 0x01 // Enable CCF interrupt
 347
 348 #endif /*REG_SST89x5xRDx_H*/