sdcc/device/include/mcs51/XC866.h

   1 /*-------------------------------------------------------------------------
   2    XC866.h - register Declarations for the Infineon XC866
   3
   4    Copyright (C) 2005, Llewellyn van Zyl <eduprep AT myconnection.co.za>
   5
   6    This library is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published by the
   8    Free Software Foundation; either version 2, or (at your option) any
   9    later version.
  10
  11    This library is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this library; see the file COPYING. If not, write to the
  18    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  19    MA 02110-1301, USA.
  20
  21    As a special exception, if you link this library with other files,
  22    some of which are compiled with SDCC, to produce an executable,
  23    this library does not by itself cause the resulting executable to
  24    be covered by the GNU General Public License. This exception does
  25    not however invalidate any other reasons why the executable file
  26    might be covered by the GNU General Public License.
  27 -------------------------------------------------------------------------*/
  28
  29 #ifndef XC866_H
  30 #define XC866_H
  31
  32 //   SFR byte definitions
  33 __sfr __at (0xE0) A;
  34 __sfr __at (0xCA) ADC_CHCTR0;
  35 __sfr __at (0xCB) ADC_CHCTR1;
  36 __sfr __at (0xCC) ADC_CHCTR2;
  37 __sfr __at (0xCD) ADC_CHCTR3;
  38 __sfr __at (0xCE) ADC_CHCTR4;
  39 __sfr __at (0xCF) ADC_CHCTR5;
  40 __sfr __at (0xD2) ADC_CHCTR6;
  41 __sfr __at (0xD3) ADC_CHCTR7;
  42 __sfr __at (0xCB) ADC_CHINCR;
  43 __sfr __at (0xCA) ADC_CHINFR;
  44 __sfr __at (0xCD) ADC_CHINPR;
  45 __sfr __at (0xCC) ADC_CHINSR;
  46 __sfr __at (0xCA) ADC_CRCR1;
  47 __sfr __at (0xCC) ADC_CRMR1;
  48 __sfr __at (0xCB) ADC_CRPR1;
  49 __sfr __at (0xCF) ADC_ETRCR;
  50 __sfr __at (0xCF) ADC_EVINCR;
  51 __sfr __at (0xCE) ADC_EVINFR;
  52 __sfr __at (0xD3) ADC_EVINPR;
  53 __sfr __at (0xD2) ADC_EVINSR;
  54 __sfr __at (0xCA) ADC_GLOBCTR;
  55 __sfr __at (0xCB) ADC_GLOBSTR;
  56 __sfr __at (0xCE) ADC_INPCR0;
  57 __sfr __at (0xCD) ADC_LCBR;
  58 __sfr __at (0xD1) ADC_PAGE;
  59 __sfr __at (0xCC) ADC_PRAR;
  60 __sfr __at (0xCF) ADC_Q0R0;
  61 __sfr __at (0xD2) ADC_QBUR0;
  62 __sfr __at (0xD2) ADC_QINR0;
  63 __sfr __at (0xCD) ADC_QMR0;
  64 __sfr __at (0xCE) ADC_QSR0;
  65 __sfr __at (0xCA) ADC_RCR0;
  66 __sfr __at (0xCB) ADC_RCR1;
  67 __sfr __at (0xCC) ADC_RCR2;
  68 __sfr __at (0xCD) ADC_RCR3;
  69 __sfr __at (0xCB) ADC_RESR0H;
  70 __sfr __at (0xCA) ADC_RESR0L;
  71 __sfr __at (0xCD) ADC_RESR1H;
  72 __sfr __at (0xCC) ADC_RESR1L;
  73 __sfr __at (0xCF) ADC_RESR2H;
  74 __sfr __at (0xCE) ADC_RESR2L;
  75 __sfr __at (0xD3) ADC_RESR3H;
  76 __sfr __at (0xD2) ADC_RESR3L;
  77 __sfr __at (0xCB) ADC_RESRA0H;
  78 __sfr __at (0xCA) ADC_RESRA0L;
  79 __sfr __at (0xCD) ADC_RESRA1H;
  80 __sfr __at (0xCC) ADC_RESRA1L;
  81 __sfr __at (0xCF) ADC_RESRA2H;
  82 __sfr __at (0xCE) ADC_RESRA2L;
  83 __sfr __at (0xD3) ADC_RESRA3H;
  84 __sfr __at (0xD2) ADC_RESRA3L;
  85 __sfr __at (0xCE) ADC_VFCR;
  86 __sfr __at (0xF0) B;
  87 __sfr __at (0xBD) BCON;
  88 __sfr __at (0xBE) BG;
  89 __sfr __at (0xFB) CCU6_CC60RH;
  90 __sfr __at (0xFA) CCU6_CC60RL;
  91 __sfr __at (0xFB) CCU6_CC60SRH;
  92 __sfr __at (0xFA) CCU6_CC60SRL;
  93 __sfr __at (0xFD) CCU6_CC61RH;
  94 __sfr __at (0xFC) CCU6_CC61RL;
  95 __sfr __at (0xFD) CCU6_CC61SRH;
  96 __sfr __at (0xFC) CCU6_CC61SRL;
  97 __sfr __at (0xFF) CCU6_CC62RH;
  98 __sfr __at (0xFE) CCU6_CC62RL;
  99 __sfr __at (0xFF) CCU6_CC62SRH;
 100 __sfr __at (0xFE) CCU6_CC62SRL;
 101 __sfr __at (0x9B) CCU6_CC63RH;
 102 __sfr __at (0x9A) CCU6_CC63RL;
 103 __sfr __at (0x9B) CCU6_CC63SRH;
 104 __sfr __at (0x9A) CCU6_CC63SRL;
 105 __sfr __at (0xA7) CCU6_CMPMODIFH;
 106 __sfr __at (0xA6) CCU6_CMPMODIFL;
 107 __sfr __at (0xFF) CCU6_CMPSTATH;
 108 __sfr __at (0xFE) CCU6_CMPSTATL;
 109 __sfr __at (0x9D) CCU6_IENH;
 110 __sfr __at (0x9C) CCU6_IENL;
 111 __sfr __at (0x9F) CCU6_INPH;
 112 __sfr __at (0x9E) CCU6_INPL;
 113 __sfr __at (0x9D) CCU6_ISH;
 114 __sfr __at (0x9C) CCU6_ISL;
 115 __sfr __at (0xA5) CCU6_ISRH;
 116 __sfr __at (0xA4) CCU6_ISRL;
 117 __sfr __at (0xA5) CCU6_ISSH;
 118 __sfr __at (0xA4) CCU6_ISSL;
 119 __sfr __at (0xA7) CCU6_MCMCTR;
 120 __sfr __at (0x9B) CCU6_MCMOUTH;
 121 __sfr __at (0x9A) CCU6_MCMOUTL;
 122 __sfr __at (0x9F) CCU6_MCMOUTSH;
 123 __sfr __at (0x9E) CCU6_MCMOUTSL;
 124 __sfr __at (0xFD) CCU6_MODCTRH;
 125 __sfr __at (0xFC) CCU6_MODCTRL;
 126 __sfr __at (0xA3) CCU6_PAGE;
 127 __sfr __at (0x9F) CCU6_PISEL0H;
 128 __sfr __at (0x9E) CCU6_PISEL0L;
 129 __sfr __at (0xA4) CCU6_PISEL2;
 130 __sfr __at (0xA6) CCU6_PSLR;
 131 __sfr __at (0xA5) CCU6_T12DTCH;
 132 __sfr __at (0xA4) CCU6_T12DTCL;
 133 __sfr __at (0xFB) CCU6_T12H;
 134 __sfr __at (0xFA) CCU6_T12L;
 135 __sfr __at (0x9B) CCU6_T12MSELH;
 136 __sfr __at (0x9A) CCU6_T12MSELL;
 137 __sfr __at (0x9D) CCU6_T12PRH;
 138 __sfr __at (0x9C) CCU6_T12PRL;
 139 __sfr __at (0xFD) CCU6_T13H;
 140 __sfr __at (0xFC) CCU6_T13L;
 141 __sfr __at (0x9F) CCU6_T13PRH;
 142 __sfr __at (0x9E) CCU6_T13PRL;
 143 __sfr __at (0xA7) CCU6_TCTR0H;
 144 __sfr __at (0xA6) CCU6_TCTR0L;
 145 __sfr __at (0xFB) CCU6_TCTR2H;
 146 __sfr __at (0xFA) CCU6_TCTR2L;
 147 __sfr __at (0x9D) CCU6_TCTR4H;
 148 __sfr __at (0x9C) CCU6_TCTR4L;
 149 __sfr __at (0xFF) CCU6_TRPCTRH;
 150 __sfr __at (0xFE) CCU6_TRPCTRL;
 151 __sfr __at (0xBA) CMCON;
 152 __sfr __at (0x83) DPH;
 153 __sfr __at (0x82) DPL;
 154 __sfr __at (0xA2) EO;
 155 __sfr __at (0xB7) EXICON0;
 156 __sfr __at (0xBA) EXICON1;
 157 __sfr __at (0xBD) FEAH;
 158 __sfr __at (0xBC) FEAL;
 159 __sfr __at (0xF7) HWBPDR;
 160 __sfr __at (0xF6) HWBPSR;
 161 __sfr __at (0xB3) ID;
 162 __sfr __at (0xA8) IEN0;
 163 __sfr __at (0xE8) IEN1;
 164 __sfr __at (0xB8) IP;
 165 __sfr __at (0xF8) IP1;
 166 __sfr __at (0xB9) IPH;
 167 __sfr __at (0xF9) IPH1;
 168 __sfr __at (0xB4) IRCON0;
 169 __sfr __at (0xB5) IRCON1;
 170 __sfr __at (0xF3) MMBPCR;
 171 __sfr __at (0xF1) MMCR;
 172 __sfr __at (0xE9) MMCR2;
 173 __sfr __at (0xF5) MMDR;
 174 __sfr __at (0xF4) MMICR;
 175 __sfr __at (0xF2) MMSR;
 176 __sfr __at (0xB3) MODPISEL;
 177 __sfr __at (0xBB) NMICON;
 178 __sfr __at (0xBC) NMISR;
 179 __sfr __at (0xB6) OSC_CON;
 180 __sfr __at (0x80) P0_ALTSEL0;
 181 __sfr __at (0x86) P0_ALTSEL1;
 182 __sfr __at (0x80) P0_DATA;
 183 __sfr __at (0x86) P0_DIR;
 184 __sfr __at (0x80) P0_OD;
 185 __sfr __at (0x86) P0_PUDEN;
 186 __sfr __at (0x80) P0_PUDSEL;
 187 __sfr __at (0x90) P1_ALTSEL0;
 188 __sfr __at (0x91) P1_ALTSEL1;
 189 __sfr __at (0x90) P1_DATA;
 190 __sfr __at (0x91) P1_DIR;
 191 __sfr __at (0x90) P1_OD;
 192 __sfr __at (0x91) P1_PUDEN;
 193 __sfr __at (0x90) P1_PUDSEL;
 194 __sfr __at (0xA0) P2_DATA;
 195 __sfr __at (0xA1) P2_PUDEN;
 196 __sfr __at (0xA0) P2_PUDSEL;
 197 __sfr __at (0xB0) P3_ALTSEL0;
 198 __sfr __at (0xB1) P3_ALTSEL1;
 199 __sfr __at (0xB0) P3_DATA;
 200 __sfr __at (0xB1) P3_DIR;
 201 __sfr __at (0xB0) P3_OD;
 202 __sfr __at (0xB1) P3_PUDEN;
 203 __sfr __at (0xB0) P3_PUDSEL;
 204 __sfr __at (0xBB) PASSWD;
 205 __sfr __at (0x87) PCON;
 206 __sfr __at (0xB7) PLL_CON;
 207 __sfr __at (0xB4) PMCON0;
 208 __sfr __at (0xB5) PMCON1;
 209 __sfr __at (0xB2) PORT_PAGE;
 210 __sfr __at (0xD0) PSW;
 211 __sfr __at (0x99) SBUF;
 212 __sfr __at (0x98) SCON;
 213 __sfr __at (0xBF) SCU_PAGE;
 214 __sfr __at (0x81) SP;
 215 __sfr __at (0xAF) SSC_BRH;
 216 __sfr __at (0xAE) SSC_BRL;
 217 __sfr __at (0xAB) SSC_CONH_O;
 218 __sfr __at (0xAB) SSC_CONH_P;
 219 __sfr __at (0xAA) SSC_CONL_O;
 220 __sfr __at (0xAA) SSC_CONL_P;
 221 __sfr __at (0xA9) SSC_PISEL;
 222 __sfr __at (0xAD) SSC_RBL;
 223 __sfr __at (0xAC) SSC_TBL;
 224 __sfr __at (0x8F) SYSCON0;
 225 __sfr __at (0xC3) T2_RC2H;
 226 __sfr __at (0xC2) T2_RC2L;
 227 __sfr __at (0xC0) T2_T2CON;
 228 __sfr __at (0xC5) T2_T2H;
 229 __sfr __at (0xC4) T2_T2L;
 230 __sfr __at (0xC1) T2_T2MOD;
 231 __sfr __at (0x88) TCON;
 232 __sfr __at (0x8C) TH0;
 233 __sfr __at (0x8D) TH1;
 234 __sfr __at (0x8A) TL0;
 235 __sfr __at (0x8B) TL1;
 236 __sfr __at (0x89) TMOD;
 237 __sfr __at (0xBB) WDTCON;    // located in the mapped SFR area
 238 __sfr __at (0xBF) WDTH;      // located in the mapped SFR area
 239 __sfr __at (0xBE) WDTL;      // located in the mapped SFR area
 240 __sfr __at (0xBC) WDTREL;    // located in the mapped SFR area
 241 __sfr __at (0xBD) WDTWINB;   // located in the mapped SFR area
 242
 243 __sfr __at (0xB3) XADDRH;    // beware this is in an sfr page!
 244 __sfr __at (0xB3) _XPAGE;    // this is the name SDCC expects for this sfr
 245
 246 //   SFR bit definitions
 247
 248 /*  P0  */
 249 __sbit __at (0x80) P0_0 ;
 250 __sbit __at (0x81) P0_1 ;
 251 __sbit __at (0x82) P0_2 ;
 252 __sbit __at (0x83) P0_3 ;
 253 __sbit __at (0x84) P0_4 ;
 254 __sbit __at (0x85) P0_5 ;
 255
 256 /*  P1  */
 257 __sbit __at (0x90) P1_0 ;
 258 __sbit __at (0x91) P1_1 ;
 259 __sbit __at (0x92) P1_5 ;
 260 __sbit __at (0x93) P1_6 ;
 261 __sbit __at (0x94) P1_7 ;
 262
 263 /*  P2  */
 264 __sbit __at (0xA0) P2_0 ;
 265 __sbit __at (0xA1) P2_1 ;
 266 __sbit __at (0xA2) P2_2 ;
 267 __sbit __at (0xA3) P2_3 ;
 268 __sbit __at (0xA4) P2_4 ;
 269 __sbit __at (0xA5) P2_5 ;
 270 __sbit __at (0xA6) P2_6 ;
 271 __sbit __at (0xA7) P2_7 ;
 272
 273 /*  P3  */
 274 __sbit __at (0xB0) P3_0 ;
 275 __sbit __at (0xB1) P3_1 ;
 276 __sbit __at (0xB2) P3_2 ;
 277 __sbit __at (0xB3) P3_3 ;
 278 __sbit __at (0xB4) P3_4 ;
 279 __sbit __at (0xB5) P3_5 ;
 280 __sbit __at (0xB6) P3_6 ;
 281 __sbit __at (0xB7) P3_7 ;
 282
 283
 284 //   IEN0
 285 __sbit __at (0xAF) EA;
 286 __sbit __at (0xAC) ES;
 287 __sbit __at (0xA9) ET0;
 288 __sbit __at (0xAB) ET1;
 289 __sbit __at (0xAD) ET2;
 290 __sbit __at (0xA8) EX0;
 291 __sbit __at (0xAA) EX1;
 292
 293 //   IEN1
 294 __sbit __at (0xE8) EADC;
 295 __sbit __at (0xEC) ECCIP0;
 296 __sbit __at (0xED) ECCIP1;
 297 __sbit __at (0xEE) ECCIP2;
 298 __sbit __at (0xEF) ECCIP3;
 299 __sbit __at (0xE9) ESSC;
 300 __sbit __at (0xEA) EX2;
 301 __sbit __at (0xEB) EXM;
 302
 303 //   IP1
 304 __sbit __at (0xF8) PADC;
 305 __sbit __at (0xFC) PCCIP0;
 306 __sbit __at (0xFD) PCCIP1;
 307 __sbit __at (0xFE) PCCIP2;
 308 __sbit __at (0xFF) PCCIP3;
 309 __sbit __at (0xF9) PSSC;
 310 __sbit __at (0xFA) PX2;
 311 __sbit __at (0xFB) PXM;
 312
 313 //   IP
 314 __sbit __at (0xBC) PS;
 315 __sbit __at (0xB9) PT0;
 316 __sbit __at (0xBB) PT1;
 317 __sbit __at (0xBD) PT2;
 318 __sbit __at (0xB8) PX0;
 319 __sbit __at (0xBA) PX1;
 320
 321 //   PSW
 322 __sbit __at (0xD6) AC;
 323 __sbit __at (0xD7) CY;
 324 __sbit __at (0xD5) F0;
 325 __sbit __at (0xD1) F1;
 326 __sbit __at (0xD2) OV;
 327 __sbit __at (0xD0) P;
 328 __sbit __at (0xD3) RS0;
 329 __sbit __at (0xD4) RS1;
 330
 331 //   SCON
 332 __sbit __at (0x9A) RB8;
 333 __sbit __at (0x9C) REN;
 334 __sbit __at (0x98) RI;
 335 __sbit __at (0x9F) SM0;
 336 __sbit __at (0x9E) SM1;
 337 __sbit __at (0x9D) SM2;
 338 __sbit __at (0x9B) TB8;
 339 __sbit __at (0x99) TI;
 340
 341 //   T2_T2CON
 342 __sbit __at (0xC0) CP_RL2;
 343 __sbit __at (0xC3) EXEN2;
 344 __sbit __at (0xC6) EXF2;
 345 __sbit __at (0xC7) TF2;
 346 __sbit __at (0xC2) TR2;
 347
 348 //   TCON
 349 __sbit __at (0x89) IE0;
 350 __sbit __at (0x8B) IE1;
 351 __sbit __at (0x88) IT0;
 352 __sbit __at (0x8A) IT1;
 353 __sbit __at (0x8D) TF0;
 354 __sbit __at (0x8F) TF1;
 355 __sbit __at (0x8C) TR0;
 356 __sbit __at (0x8E) TR1;
 357
 358 //   Definition of the PAGE SFR
 359
 360 //   PORT_PAGE
 361 #define _pp0 PORT_PAGE=0 // PORT_PAGE postfix
 362 #define _pp1 PORT_PAGE=1 // PORT_PAGE postfix
 363 #define _pp2 PORT_PAGE=2 // PORT_PAGE postfix
 364 #define _pp3 PORT_PAGE=3 // PORT_PAGE postfix
 365
 366 //   ADC_PAGE
 367 #define _ad0 ADC_PAGE=0 // ADC_PAGE postfix
 368 #define _ad1 ADC_PAGE=1 // ADC_PAGE postfix
 369 #define _ad2 ADC_PAGE=2 // ADC_PAGE postfix
 370 #define _ad3 ADC_PAGE=3 // ADC_PAGE postfix
 371 #define _ad4 ADC_PAGE=4 // ADC_PAGE postfix
 372 #define _ad5 ADC_PAGE=5 // ADC_PAGE postfix
 373 #define _ad6 ADC_PAGE=6 // ADC_PAGE postfix
 374
 375 //   SCU_PAGE
 376 #define _su0 SCU_PAGE=0 // SCU_PAGE postfix
 377 #define _su1 SCU_PAGE=1 // SCU_PAGE postfix
 378 #define _su2 SCU_PAGE=2 // SCU_PAGE postfix
 379
 380 //   CCU_PAGE
 381 #define _cc0 CCU_PAGE=0 // CCU_PAGE postfix
 382 #define _cc1 CCU_PAGE=1 // CCU_PAGE postfix
 383 #define _cc2 CCU_PAGE=2 // CCU_PAGE postfix
 384 #define _cc3 CCU_PAGE=3 // CCU_PAGE postfix
 385
 386 //   FLASH_PAGE
 387 #define _fl0 FLASH_PAGE=0 // FLASH_PAGE postfix
 388 #define _fl1 FLASH_PAGE=1 // FLASH_PAGE postfix
 389 #define _fl2 FLASH_PAGE=2 // FLASH_PAGE postfix
 390
 391 #define SST0 0x80         // Save SFR page to ST0
 392 #define RST0 0xC0         // Restore SFR page from ST0
 393 #define SST1 0x90         // Save SFR page to ST1
 394 #define RST1 0xD0         // Restore SFR page from ST1
 395 #define SST2 0xA0         // Save SFR page to ST2
 396 #define RST2 0xE0         // Restore SFR page from ST2
 397 #define SST3 0xB0         // Save SFR page to ST3
 398 #define RST3 0xF0         // Restore SFR page from ST3
 399 #define noSST 0x00        // Switch page without saving
 400
 401 #define SFR_PAGE(pg,op) pg+op
 402
 403 #endif