sdcc/device/include/mcs51/at89S8252.h

   1 /*-------------------------------------------------------------------------
   2    at89S8252.h - register declarations for ATMEL 89S8252 and 89LS8252 processors
   3
   4    Copyright (C) 2005, Dipl.-Ing. (FH) Michael Schmitt <michael.schmitt AT t-online.de>
   5
   6    Bug-Fix Jun 29 1999
   7
   8    Additional definitions Nov 23 1999
   9      by Bernd Krueger-Knauber <bkk AT infratec-plus.de>
  10
  11    based on reg51.h by Sandeep Dutta <sandeep.dutta AT usa.net>
  12    KEIL C compatible definitions are included
  13
  14    Bug-Fix Feb 16 2006
  15      by Krzysztof Polomka <del_p AT op.pl>
  16
  17    This library is free software; you can redistribute it and/or modify it
  18    under the terms of the GNU General Public License as published by the
  19    Free Software Foundation; either version 2, or (at your option) any
  20    later version.
  21
  22    This library is distributed in the hope that it will be useful,
  23    but WITHOUT ANY WARRANTY; without even the implied warranty of
  24    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25    GNU General Public License for more details.
  26
  27    You should have received a copy of the GNU General Public License
  28    along with this library; see the file COPYING. If not, write to the
  29    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  30    MA 02110-1301, USA.
  31
  32    As a special exception, if you link this library with other files,
  33    some of which are compiled with SDCC, to produce an executable,
  34    this library does not by itself cause the resulting executable to
  35    be covered by the GNU General Public License. This exception does
  36    not however invalidate any other reasons why the executable file
  37    might be covered by the GNU General Public License.
  38 -------------------------------------------------------------------------*/
  39
  40 #ifndef AT89S8252_H
  41 #define AT89S8252_H
  42
  43 /* BYTE addressable registers */
  44 __sfr __at (0x80) P0          ;
  45 __sfr __at (0x81) SP          ;
  46 __sfr __at (0x82) DPL         ;
  47 __sfr __at (0x82) DP0L        ; /* as called by Atmel */
  48 __sfr __at (0x83) DPH         ;
  49 __sfr __at (0x83) DP0H        ; /* as called by Atmel */
  50 __sfr __at (0x84) DP1L        ; /* at89S8252 specific register */
  51 __sfr __at (0x85) DP1H        ; /* at89S8252 specific register */
  52 __sfr __at (0x86) SPDR        ; /* at89S8252 specific register */
  53 __sfr __at (0x87) PCON        ;
  54 __sfr __at (0x88) TCON        ;
  55 __sfr __at (0x89) TMOD        ;
  56 __sfr __at (0x8A) TL0         ;
  57 __sfr __at (0x8B) TL1         ;
  58 __sfr __at (0x8C) TH0         ;
  59 __sfr __at (0x8D) TH1         ;
  60 __sfr __at (0x90) P1          ;
  61 __sfr __at (0x96) WMCON       ; /* at89S8252 specific register */
  62 __sfr __at (0x98) SCON        ;
  63 __sfr __at (0x99) SBUF        ;
  64 __sfr __at (0xA0) P2          ;
  65 __sfr __at (0xA8) IE          ;
  66 __sfr __at (0xAA) SPSR        ; /* at89S8252 specific register */
  67 __sfr __at (0xB0) P3          ;
  68 __sfr __at (0xB8) IP          ;
  69 __sfr __at (0xC8) T2CON       ;
  70 __sfr __at (0xC9) T2MOD       ;
  71 __sfr __at (0xCA) RCAP2L      ;
  72 __sfr __at (0xCB) RCAP2H      ;
  73 __sfr __at (0xCC) TL2         ;
  74 __sfr __at (0xCD) TH2         ;
  75 __sfr __at (0xD0) PSW         ;
  76 __sfr __at (0xD5) SPCR        ; /* at89S8252 specific register */
  77 __sfr __at (0xE0) ACC         ;
  78 __sfr __at (0xE0) A           ;
  79 __sfr __at (0xF0) B           ;
  80
  81
  82 /* BIT addressable registers */
  83 /* P0 */
  84 __sbit __at (0x80) P0_0       ;
  85 __sbit __at (0x81) P0_1       ;
  86 __sbit __at (0x82) P0_2       ;
  87 __sbit __at (0x83) P0_3       ;
  88 __sbit __at (0x84) P0_4       ;
  89 __sbit __at (0x85) P0_5       ;
  90 __sbit __at (0x86) P0_6       ;
  91 __sbit __at (0x87) P0_7       ;
  92
  93 /* TCON */
  94 __sbit __at (0x88) IT0        ;
  95 __sbit __at (0x89) IE0        ;
  96 __sbit __at (0x8A) IT1        ;
  97 __sbit __at (0x8B) IE1        ;
  98 __sbit __at (0x8C) TR0        ;
  99 __sbit __at (0x8D) TF0        ;
 100 __sbit __at (0x8E) TR1        ;
 101 __sbit __at (0x8F) TF1        ;
 102
 103 /* P1 */
 104 __sbit __at (0x90) P1_0       ;
 105 __sbit __at (0x91) P1_1       ;
 106 __sbit __at (0x92) P1_2       ;
 107 __sbit __at (0x93) P1_3       ;
 108 __sbit __at (0x94) P1_4       ;
 109 __sbit __at (0x95) P1_5       ;
 110 __sbit __at (0x96) P1_6       ;
 111 __sbit __at (0x97) P1_7       ;
 112
 113 __sbit __at (0x90) T2         ;
 114 __sbit __at (0x91) T2EX       ;
 115
 116 /* P1 SPI portpins */
 117 __sbit __at (0x94) SS         ; /* SPI: SS - Slave port select input */
 118 __sbit __at (0x95) MOSI       ; /* SPI: MOSI - Master data output, slave data input */
 119 __sbit __at (0x96) MISO       ; /* SPI: MISO - Master data input, slave data output */
 120 __sbit __at (0x97) SCK        ; /* SPI: SCK - Master clock output, slave clock input */
 121
 122
 123 /* SCON */
 124 __sbit __at (0x98) RI         ;
 125 __sbit __at (0x99) TI         ;
 126 __sbit __at (0x9A) RB8        ;
 127 __sbit __at (0x9B) TB8        ;
 128 __sbit __at (0x9C) REN        ;
 129 __sbit __at (0x9D) SM2        ;
 130 __sbit __at (0x9E) SM1        ;
 131 __sbit __at (0x9F) SM0        ;
 132
 133 /* P2 */
 134 __sbit __at (0xA0) P2_0       ;
 135 __sbit __at (0xA1) P2_1       ;
 136 __sbit __at (0xA2) P2_2       ;
 137 __sbit __at (0xA3) P2_3       ;
 138 __sbit __at (0xA4) P2_4       ;
 139 __sbit __at (0xA5) P2_5       ;
 140 __sbit __at (0xA6) P2_6       ;
 141 __sbit __at (0xA7) P2_7       ;
 142
 143 /* IE */
 144 __sbit __at (0xA8) EX0        ;
 145 __sbit __at (0xA9) ET0        ;
 146 __sbit __at (0xAA) EX1        ;
 147 __sbit __at (0xAB) ET1        ;
 148 __sbit __at (0xAC) ES         ;
 149 __sbit __at (0xAD) ET2        ;
 150 __sbit __at (0xAF) EA         ;
 151
 152 /* P3 */
 153 __sbit __at (0xB0) P3_0       ;
 154 __sbit __at (0xB1) P3_1       ;
 155 __sbit __at (0xB2) P3_2       ;
 156 __sbit __at (0xB3) P3_3       ;
 157 __sbit __at (0xB4) P3_4       ;
 158 __sbit __at (0xB5) P3_5       ;
 159 __sbit __at (0xB6) P3_6       ;
 160 __sbit __at (0xB7) P3_7       ;
 161
 162 __sbit __at (0xB0) RXD        ;
 163 __sbit __at (0xB1) TXD        ;
 164 __sbit __at (0xB2) INT0       ;
 165 __sbit __at (0xB3) INT1       ;
 166 __sbit __at (0xB4) T0         ;
 167 __sbit __at (0xB5) T1         ;
 168 __sbit __at (0xB6) WR         ;
 169 __sbit __at (0xB7) RD         ;
 170
 171 /* IP */
 172 __sbit __at (0xB8) PX0        ;
 173 __sbit __at (0xB9) PT0        ;
 174 __sbit __at (0xBA) PX1        ;
 175 __sbit __at (0xBB) PT1        ;
 176 __sbit __at (0xBC) PS         ;
 177 __sbit __at (0xBD) PT2        ;
 178
 179 /* T2CON */
 180 __sbit __at (0xC8) T2CON_0    ;
 181 __sbit __at (0xC9) T2CON_1    ;
 182 __sbit __at (0xCA) T2CON_2    ;
 183 __sbit __at (0xCB) T2CON_3    ;
 184 __sbit __at (0xCC) T2CON_4    ;
 185 __sbit __at (0xCD) T2CON_5    ;
 186 __sbit __at (0xCE) T2CON_6    ;
 187 __sbit __at (0xCF) T2CON_7    ;
 188
 189 __sbit __at (0xC8) CP_RL2     ;
 190 __sbit __at (0xC9) C_T2       ;
 191 __sbit __at (0xCA) TR2        ;
 192 __sbit __at (0xCB) EXEN2      ;
 193 __sbit __at (0xCC) TCLK       ;
 194 __sbit __at (0xCD) RCLK       ;
 195 __sbit __at (0xCE) EXF2       ;
 196 __sbit __at (0xCF) TF2        ;
 197
 198 /* PSW */
 199 __sbit __at (0xD0) P          ;
 200 __sbit __at (0xD1) FL         ;
 201 __sbit __at (0xD2) OV         ;
 202 __sbit __at (0xD3) RS0        ;
 203 __sbit __at (0xD4) RS1        ;
 204 __sbit __at (0xD5) F0         ;
 205 __sbit __at (0xD6) AC         ;
 206 __sbit __at (0xD7) CY         ;
 207
 208 /* B */
 209 __sbit __at (0xF0) BREG_F0    ;
 210 __sbit __at (0xF1) BREG_F1    ;
 211 __sbit __at (0xF2) BREG_F2    ;
 212 __sbit __at (0xF3) BREG_F3    ;
 213 __sbit __at (0xF4) BREG_F4    ;
 214 __sbit __at (0xF5) BREG_F5    ;
 215 __sbit __at (0xF6) BREG_F6    ;
 216 __sbit __at (0xF7) BREG_F7    ;
 217
 218
 219 /* BIT definitions for bits that are not directly accessible */
 220 /* PCON bits */
 221 #define IDL             0x01
 222 #define PD              0x02
 223 #define GF0             0x04
 224 #define GF1             0x08
 225 #define SMOD            0x80
 226
 227 #define IDL_            0x01
 228 #define PD_             0x02
 229 #define GF0_            0x04
 230 #define GF1_            0x08
 231 #define SMOD_           0x80
 232
 233 /* TMOD bits */
 234 #define M0_0            0x01
 235 #define M1_0            0x02
 236 #define C_T0            0x04
 237 #define GATE0           0x08
 238 #define M0_1            0x10
 239 #define M1_1            0x20
 240 #define C_T1            0x40
 241 #define GATE1           0x80
 242
 243 #define M0_0_           0x01
 244 #define M1_0_           0x02
 245 #define C_T0_           0x04
 246 #define GATE0_          0x08
 247 #define M0_1_           0x10
 248 #define M1_1_           0x20
 249 #define C_T1_           0x40
 250 #define GATE1_          0x80
 251
 252 #define T0_M0           0x01
 253 #define T0_M1           0x02
 254 #define T0_CT           0x04
 255 #define T0_GATE         0x08
 256 #define T1_M0           0x10
 257 #define T1_M1           0x20
 258 #define T1_CT           0x40
 259 #define T1_GATE         0x80
 260
 261 #define T0_M0_          0x01
 262 #define T0_M1_          0x02
 263 #define T0_CT_          0x04
 264 #define T0_GATE_        0x08
 265 #define T1_M0_          0x10
 266 #define T1_M1_          0x20
 267 #define T1_CT_          0x40
 268 #define T1_GATE_        0x80
 269
 270 #define T0_MASK         0x0F
 271 #define T1_MASK         0xF0
 272
 273 #define T0_MASK_        0x0F
 274 #define T1_MASK_        0xF0
 275
 276 /* T2MOD bits */
 277 #define DCEN            0x01
 278 #define T2OE            0x02
 279
 280 #define DCEN_           0x01
 281 #define T2OE_           0x02
 282
 283 /* WMCON bits */
 284 #define WMCON_WDTEN     0x01
 285 #define WMCON_WDTRST    0x02
 286 #define WMCON_DPS       0x04
 287 #define WMCON_EEMEN     0x08
 288 #define WMCON_EEMWE     0x10
 289 #define WMCON_PS0       0x20
 290 #define WMCON_PS1       0x40
 291 #define WMCON_PS2       0x80
 292
 293 /* SPCR-SPI bits */
 294 #define SPCR_SPR0       0x01
 295 #define SPCR_SPR1       0x02
 296 #define SPCR_CPHA       0x04
 297 #define SPCR_CPOL       0x08
 298 #define SPCR_MSTR       0x10
 299 #define SPCR_DORD       0x20
 300 #define SPCR_SPE        0x40
 301 #define SPCR_SPIE       0x80
 302
 303 /* SPSR-SPI bits */
 304 #define SPSR_WCOL       0x40
 305 #define SPSR_SPIF       0x80
 306
 307 /* SPDR-SPI bits */
 308 #define SPDR_SPD0       0x01
 309 #define SPDR_SPD1       0x02
 310 #define SPDR_SPD2       0x04
 311 #define SPDR_SPD3       0x08
 312 #define SPDR_SPD4       0x10
 313 #define SPDR_SPD5       0x20
 314 #define SPDR_SPD6       0x40
 315 #define SPDR_SPD7       0x80
 316
 317 /* Interrupt numbers: address = (number * 8) + 3 */
 318 #define IE0_VECTOR      0       /* 0x03 external interrupt 0 */
 319 #define EX0_VECTOR      0       /* 0x03 external interrupt 0 */
 320 #define TF0_VECTOR      1       /* 0x0b timer 0 */
 321 #define IE1_VECTOR      2       /* 0x13 external interrupt 1 */
 322 #define EX1_VECTOR      2       /* 0x13 external interrupt 1 */
 323 #define TF1_VECTOR      3       /* 0x1b timer 1 */
 324 #define SI0_VECTOR      4       /* 0x23 serial port 0 */
 325 #define TF2_VECTOR      5       /* 0x2B timer 2 */
 326 #define EX2_VECTOR      5       /* 0x2B external interrupt 2 */
 327
 328
 329 /* This is one of the addons coming from Bernd Krueger-Knauber   */
 330
 331 /* ALE (0x8E) Bit Values */
 332 __sfr __at (0x8E) ALE;          /* at89S8252 specific register */
 333
 334 /* Macro to enable and disable the toggling of the ALE-pin (EMV) */
 335
 336 /* Explanation : Original Intel 8051 Cores (Atmel has to use the */
 337 /* Intel Core) have a feature that ALE is only active during     */
 338 /* MOVX or MOVC instruction. Otherwise the ALE-Pin is weakly     */
 339 /* pulled high. This can be used to force some external devices  */
 340 /* into standby mode and reduced EMI noise                       */
 341
 342 #define ALE_OFF  ALE = ALE | 0x01
 343 #define ALE_ON   ALE = ALE & 0xFE
 344
 345 #endif