sdcc/device/include/mcs51/at89c51snd1c.h

   1 /*-------------------------------------------------------------------------
   2    at89c51snd1c.h - Register Declarations for the Atmel AT89C51SND1C Processor
   3
   4    Copyright (C) 2005, Weston Schmidt <weston_schmidt@alumni.purdue.edu>
   5
   6    This document is based on the AT8xC51SND1C document
   7        4109H-8051-01/05
   8
   9    This library is free software; you can redistribute it and/or modify it
  10    under the terms of the GNU General Public License as published by the
  11    Free Software Foundation; either version 2, or (at your option) any
  12    later version.
  13
  14    This library is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this library; see the file COPYING. If not, write to the
  21    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  22    MA 02110-1301, USA.
  23
  24    As a special exception, if you link this library with other files,
  25    some of which are compiled with SDCC, to produce an executable,
  26    this library does not by itself cause the resulting executable to
  27    be covered by the GNU General Public License. This exception does
  28    not however invalidate any other reasons why the executable file
  29    might be covered by the GNU General Public License.
  30 -------------------------------------------------------------------------*/
  31
  32
  33 #ifndef __AT89C51SND1_H__
  34 #define __AT89C51SND1_H__
  35
  36
  37 /*  BYTE Registers */
  38 __sfr __at (0xE0) ACC     ; /* C51 Core SFRs */
  39 __sfr __at (0xF0) B       ;
  40 __sfr __at (0xD0) PSW     ;
  41 __sfr __at (0x81) SP      ;
  42 __sfr __at (0x82) DPL     ;
  43 __sfr __at (0x83) DPH     ;
  44 __sfr __at (0x87) PCON    ; /* System Management SFRs */
  45 __sfr __at (0x8E) AUXR0   ;
  46 __sfr __at (0xA2) AUXR1   ;
  47 __sfr __at (0xFB) NVERS   ;
  48 __sfr __at (0x8F) CKCON   ; /* PLL and System Clock SFRs */
  49 __sfr __at (0xE9) PLLCON  ;
  50 __sfr __at (0xEE) PLLNDIV ;
  51 __sfr __at (0xEF) PLLRDIV ;
  52 __sfr __at (0xA8) IEN0    ; /* Interrupt SFRs */
  53 __sfr __at (0xB1) IEN1    ;
  54 __sfr __at (0xB7) IPH0    ;
  55 __sfr __at (0xB8) IPL0    ;
  56 __sfr __at (0xB3) IPH1    ;
  57 __sfr __at (0xB2) IPL1    ;
  58 __sfr __at (0x80) P0      ; /* Port SFRs */
  59 __sfr __at (0x90) P1      ;
  60 __sfr __at (0xA0) P2      ;
  61 __sfr __at (0xB0) P3      ;
  62 __sfr __at (0xC0) P4      ;
  63 __sfr __at (0xD8) P5      ;
  64 __sfr __at (0xD1) FCON    ; /* Flash Memory SFR */
  65 __sfr __at (0x88) TCON    ; /* Timer SFRs */
  66 __sfr __at (0x89) TMOD    ;
  67 __sfr __at (0x8A) TL0     ;
  68 __sfr __at (0x8C) TH0     ;
  69 __sfr __at (0x8B) TL1     ;
  70 __sfr __at (0x8D) TH1     ;
  71 __sfr __at (0xA6) WDTRST  ;
  72 __sfr __at (0xA7) WDTPRG  ;
  73 __sfr __at (0xAA) MP3CON  ; /* MP3 Decoder SFRs */
  74 __sfr __at (0xC8) MP3STA  ;
  75 __sfr __at (0xAF) MP3STA1 ;
  76 __sfr __at (0xAC) MP3DAT  ;
  77 __sfr __at (0xAD) MP3ANC  ;
  78 __sfr __at (0x9E) MP3VOL  ;
  79 __sfr __at (0x9F) MP3VOR  ;
  80 __sfr __at (0xB4) MP3BAS  ;
  81 __sfr __at (0xB5) MP3MED  ;
  82 __sfr __at (0xB6) MP3TRE  ;
  83 __sfr __at (0xEB) MP3CLK  ;
  84 __sfr __at (0xAE) MP3DBG  ;
  85 __sfr __at (0x9A) AUDCON0 ; /* Audio Interface SFRs */
  86 __sfr __at (0x9B) AUDCON1 ;
  87 __sfr __at (0x9C) AUDSTA  ;
  88 __sfr __at (0x9D) AUDDAT  ;
  89 __sfr __at (0xEC) AUDCLK  ;
  90 __sfr __at (0xBC) USBCON  ; /* USB Controller SFRs */
  91 __sfr __at (0xC6) USBADDR ;
  92 __sfr __at (0xBD) USBINT  ;
  93 __sfr __at (0xBE) USBIEN  ;
  94 __sfr __at (0xC7) UEPNUM  ;
  95 __sfr __at (0xD4) UEPCONX ;
  96 __sfr __at (0xCE) UEPSTAX ;
  97 __sfr __at (0xD5) UEPRST  ;
  98 __sfr __at (0xF8) UEPINT  ;
  99 __sfr __at (0xC2) UEPIEN  ;
 100 __sfr __at (0xCF) UEPDATX ;
 101 __sfr __at (0xE2) UBYCTX  ;
 102 __sfr __at (0xBA) UFNUML  ;
 103 __sfr __at (0xBB) UFNUMH  ;
 104 __sfr __at (0xEA) USBCLK  ;
 105 __sfr __at (0xE4) MMCON0  ; /* MMC Controller SFRs */
 106 __sfr __at (0xE5) MMCON1  ;
 107 __sfr __at (0xE6) MMCON2  ;
 108 __sfr __at (0xDE) MMSTA   ;
 109 __sfr __at (0xE7) MMINT   ;
 110 __sfr __at (0xDF) MMMSK   ;
 111 __sfr __at (0xDD) MMCMD   ;
 112 __sfr __at (0xDC) MMDAT   ;
 113 __sfr __at (0xED) MMCLK   ;
 114 __sfr __at (0xF9) DAT16H  ; /* IDE Interface SFR */
 115 __sfr __at (0x98) SCON    ; /* Serial I/O Port SFRs */
 116 __sfr __at (0x99) SBUF    ;
 117 __sfr __at (0xB9) SADEN   ;
 118 __sfr __at (0xA9) SADDR   ;
 119 __sfr __at (0x92) BDRCON  ;
 120 __sfr __at (0x91) BRL     ;
 121 __sfr __at (0xC3) SPCON   ; /* SPI Controller SFRs */
 122 __sfr __at (0xC4) SPSTA   ;
 123 __sfr __at (0xC5) SPDAT   ;
 124 __sfr __at (0x93) SSCON   ; /* Two Wire Controller SFRs */
 125 __sfr __at (0x94) SSSTA   ;
 126 __sfr __at (0x95) SSDAT   ;
 127 __sfr __at (0x96) SSADR   ;
 128 __sfr __at (0xA3) KBCON   ; /* Keyboard Interface SFRs */
 129 __sfr __at (0xA4) KBSTA   ;
 130 __sfr __at (0xF3) ADCON   ; /* A/D Controller SFRs */
 131 __sfr __at (0xF4) ADDL    ;
 132 __sfr __at (0xF5) ADDH    ;
 133 __sfr __at (0xF2) ADCLK   ;
 134
 135
 136 /*  BIT Registers */
 137 /*  PSW */
 138 __sbit __at (0xD7) CY     ;
 139 __sbit __at (0xD6) AC     ;
 140 __sbit __at (0xD5) F0     ;
 141 __sbit __at (0xD4) RS1    ;
 142 __sbit __at (0xD3) RS0    ;
 143 __sbit __at (0xD2) OV     ;
 144 __sbit __at (0xD1) F1     ;
 145 __sbit __at (0xD0) P      ;
 146
 147 /*  IEN0    */
 148 __sbit __at (0xAF) EA     ;
 149 __sbit __at (0xAE) EAUD   ;
 150 __sbit __at (0xAD) EMP3   ;
 151 __sbit __at (0xAC) ES     ;
 152 __sbit __at (0xAB) ET1    ;
 153 __sbit __at (0xAA) EX1    ;
 154 __sbit __at (0xA9) ET0    ;
 155 __sbit __at (0xA8) EX0    ;
 156
 157 /*  IPLO */
 158 __sbit __at (0xBE) IPLAUD ;
 159 __sbit __at (0xBD) IPLMP3 ;
 160 __sbit __at (0xBC) IPLS   ;
 161 __sbit __at (0xBB) IPLT1  ;
 162 __sbit __at (0xBA) IPLX1  ;
 163 __sbit __at (0xB9) IPLT0  ;
 164 __sbit __at (0xB8) IPLX0  ;
 165
 166 /*  P0  */
 167 __sbit __at (0x87) P0_7   ;
 168 __sbit __at (0x86) P0_6   ;
 169 __sbit __at (0x85) P0_5   ;
 170 __sbit __at (0x84) P0_4   ;
 171 __sbit __at (0x83) P0_3   ;
 172 __sbit __at (0x82) P0_2   ;
 173 __sbit __at (0x81) P0_1   ;
 174 __sbit __at (0x80) P0_0   ;
 175
 176 /*  P1  */
 177 __sbit __at (0x97) P1_7   ;
 178 __sbit __at (0x96) P1_6   ;
 179 __sbit __at (0x95) P1_5   ;
 180 __sbit __at (0x94) P1_4   ;
 181 __sbit __at (0x93) P1_3   ;
 182 __sbit __at (0x92) P1_2   ;
 183 __sbit __at (0x91) P1_1   ;
 184 __sbit __at (0x90) P1_0   ;
 185
 186 __sbit __at (0x97) SDA    ;
 187 __sbit __at (0x96) SCL    ;
 188 __sbit __at (0x93) KIN3   ;
 189 __sbit __at (0x92) KIN2   ;
 190 __sbit __at (0x91) KIN1   ;
 191 __sbit __at (0x90) KIN0   ;
 192
 193 /*  P2  */
 194 __sbit __at (0xA7) P2_7   ;
 195 __sbit __at (0xA6) P2_6   ;
 196 __sbit __at (0xA5) P2_5   ;
 197 __sbit __at (0xA4) P2_4   ;
 198 __sbit __at (0xA3) P2_3   ;
 199 __sbit __at (0xA2) P2_2   ;
 200 __sbit __at (0xA1) P2_1   ;
 201 __sbit __at (0xA0) P2_0   ;
 202
 203 /*  P3  */
 204 __sbit __at (0xB7) P3_7   ;
 205 __sbit __at (0xB6) P3_6   ;
 206 __sbit __at (0xB5) P3_5   ;
 207 __sbit __at (0xB4) P3_4   ;
 208 __sbit __at (0xB3) P3_3   ;
 209 __sbit __at (0xB2) P3_2   ;
 210 __sbit __at (0xB1) P3_1   ;
 211 __sbit __at (0xB0) P3_0   ;
 212
 213 __sbit __at (0xB7) RD     ;
 214 __sbit __at (0xB6) WR     ;
 215 __sbit __at (0xB5) T1     ;
 216 __sbit __at (0xB4) T0     ;
 217 __sbit __at (0xB3) INT1   ;
 218 __sbit __at (0xB2) INT0   ;
 219 __sbit __at (0xB1) TXD    ;
 220 __sbit __at (0xB0) RXD    ;
 221
 222 /*  P4  */
 223 __sbit __at (0xC7) P4_7   ;
 224 __sbit __at (0xC6) P4_6   ;
 225 __sbit __at (0xC5) P4_5   ;
 226 __sbit __at (0xC4) P4_4   ;
 227 __sbit __at (0xC3) P4_3   ;
 228 __sbit __at (0xC2) P4_2   ;
 229 __sbit __at (0xC1) P4_1   ;
 230 __sbit __at (0xC0) P4_0   ;
 231
 232 __sbit __at (0xC3) SS_    ;
 233 __sbit __at (0xC2) SCK    ;
 234 __sbit __at (0xC1) MOSI   ;
 235 __sbit __at (0xC0) MISO   ;
 236
 237 /*  P5  */
 238 __sbit __at (0xDB) P5_3   ;
 239 __sbit __at (0xDA) P5_2   ;
 240 __sbit __at (0xD9) P5_1   ;
 241 __sbit __at (0xD8) P5_0   ;
 242
 243 /*  TCON    */
 244 __sbit __at (0x8F) TF1    ;
 245 __sbit __at (0x8E) TR1    ;
 246 __sbit __at (0x8D) TF0    ;
 247 __sbit __at (0x8C) TR0    ;
 248 __sbit __at (0x8B) IE1    ;
 249 __sbit __at (0x8A) IT1    ;
 250 __sbit __at (0x89) IE0    ;
 251 __sbit __at (0x88) IT0    ;
 252
 253 /*  MP3STA  */
 254 __sbit __at (0xCF) MPANC  ;
 255 __sbit __at (0xCE) MPREQ  ;
 256 __sbit __at (0xCD) ERRLAY ;
 257 __sbit __at (0xCC) ERRSYN ;
 258 __sbit __at (0xCB) ERRCRC ;
 259 __sbit __at (0xCA) MPFS1  ;
 260 __sbit __at (0xC9) MPFS0  ;
 261 __sbit __at (0xC8) MPVER  ;
 262
 263 /*  UEPINT  */
 264 __sbit __at (0xFA) EP2INT ;
 265 __sbit __at (0xF9) EP1INT ;
 266 __sbit __at (0xF8) EP0INT ;
 267
 268 /*  SCON  */
 269 __sbit __at (0x9F) SM0    ;
 270 __sbit __at (0x9F) FE     ;
 271 __sbit __at (0x9E) SM1    ;
 272 __sbit __at (0x9D) SM2    ;
 273 __sbit __at (0x9C) REN    ;
 274 __sbit __at (0x9B) TB8    ;
 275 __sbit __at (0x9A) RB8    ;
 276 __sbit __at (0x99) TI     ;
 277 __sbit __at (0x98) RI     ;
 278
 279
 280 /* BIT definitions for bits that are not directly accessible */
 281 /* PCON bits */
 282 #define MSK_SMOD1   0x80
 283 #define MSK_SMOD0   0x40
 284 #define MSK_GF1     0x08
 285 #define MSK_GF0     0x04
 286 #define MSK_PD      0x02
 287 #define MSK_IDL     0x01
 288
 289 /* AUXR0 bits */
 290 #define MSK_EXT16   0x40
 291 #define MSK_M0      0x20
 292 #define MSK_DPHDIS  0x10
 293 #define MSK_XRS     0x0C
 294 #define MSK_EXTRAM  0x02
 295 #define MSK_AO      0x01
 296
 297 /* AUXR1 bits */
 298 #define MSK_ENBOOT  0x20
 299 #define MSK_GF3     0x08
 300 #define MSK_DPS     0x01
 301
 302 /* CKCON bits */
 303 #define MSK_X2      0x01
 304
 305 /* PLLCON bits */
 306 #define MSK_PLL_R   0xC0
 307 #define MSK_PLLRES  0x08
 308 #define MSK_PLLEN   0x02
 309 #define MSK_PLOCK   0x01
 310
 311 /* PLLNDIV bits */
 312 #define MSK_PLL_N   0x7F
 313
 314 /* IEN1 bits */
 315 #define MSK_EUSB    0x40
 316 #define MSK_EKB     0x10
 317 #define MSK_EADC    0x08
 318 #define MSK_ESPI    0x04
 319 #define MSK_EI2C    0x02
 320 #define MSK_EMMC    0x01
 321
 322 /* IPHO bits */
 323 #define MSK_IPHAUD  0x40
 324 #define MSK_IPHMP3  0x20
 325 #define MSK_IPHS    0x10
 326 #define MSK_IPHT1   0x08
 327 #define MSK_IPHX1   0x04
 328 #define MSK_IPHT0   0x02
 329 #define MSK_IPHX0   0x01
 330
 331 /* IPH1 bits */
 332 #define MSK_IPHUSB  0x40
 333 #define MSK_IPHKB   0x10
 334 #define MSK_IPHADC  0x08
 335 #define MSK_IPHSPI  0x04
 336 #define MSK_IPHI2C  0x02
 337 #define MSK_IPHMMC  0x01
 338
 339 /* IPL1 bits */
 340 #define MSK_IPLUSB  0x40
 341 #define MSK_IPLKB   0x10
 342 #define MSK_IPLADC  0x08
 343 #define MSK_IPLSPI  0x04
 344 #define MSK_IPLI2C  0x02
 345 #define MSK_IPLMMC  0x01
 346
 347 /* TMOD bits */
 348 #define MSK_GATE1   0x80
 349 #define MSK_C_T1    0x40
 350 #define MSK_MO1     0x30
 351 #define MSK_GATE0   0x08
 352 #define MSK_C_T0    0x04
 353 #define MSK_MO0     0x03
 354
 355 /* MP3CON bits */
 356 #define MSK_MPEN    0x80
 357 #define MSK_MPBBST  0x40
 358 #define MSK_CRCEN   0x20
 359 #define MSK_MSKANC  0x10
 360 #define MSK_MSKREQ  0x08
 361 #define MSK_MSKLAY  0x04
 362 #define MSK_MSKSYN  0x02
 363 #define MSK_MSKCRC  0x01
 364
 365 /* MP3STA1 bits */
 366 #define MSK_MPFREQ  0x10
 367 #define MSK_MPBREQ  0x08
 368
 369 /* MP3VOL bits */
 370 #define MSK_VOL     0x1F
 371
 372 /* MP3VOR bits */
 373 #define MSK_VOR     0x1F
 374
 375 /* MP3BAS bits */
 376 #define MSK_BAS     0x1F
 377
 378 /* MP3MED bits */
 379 #define MSK_MED     0x1F
 380
 381 /* MP3TRE bits */
 382 #define MSK_TRE     0x1F
 383
 384 /* MP3CLK bits */
 385 #define MSK_MPCD    0x1F
 386
 387 /* MP3DBG bits */
 388 #define MSK_MPFULL  0x08
 389
 390 /* AUDCON0 bits */
 391 #define MSK_JUST    0xF8
 392 #define MSK_POL     0x04
 393 #define MSK_DSIZ    0x02
 394 #define MSK_HLR     0x01
 395
 396 /* AUDCON1 bits */
 397 #define MSK_SRC     0x80
 398 #define MSK_DRQEN   0x40
 399 #define MSK_MSREQ   0x20
 400 #define MSK_MUDRN   0x10
 401 #define MSK_DUP     0x06
 402 #define MSK_AUDEN   0x01
 403
 404 /* AUDSTA bits */
 405 #define MSK_SREQ    0x80
 406 #define MSK_UDRN    0x40
 407 #define MSK_AUBUSY  0x20
 408
 409 /* AUDCLK bits */
 410 #define MSK_AUCD    0x1F
 411
 412 /* USBCON bits */
 413 #define MSK_USBE    0x80
 414 #define MSK_SUSPCLK 0x40
 415 #define MSK_SDRMWUP 0x20
 416 #define MSK_UPRSM   0x08
 417 #define MSK_RMWUPE  0x04
 418 #define MSK_CONFG   0x02
 419 #define MSK_FADDEN  0x01
 420
 421 /* USBADDR bits */
 422 #define MSK_FEN     0x80
 423 #define MSK_UADD    0x7F
 424
 425 /* USBINT bits */
 426 #define MSK_WUPCPU  0x20
 427 #define MSK_EORINT  0x10
 428 #define MSK_SOFINT  0x08
 429 #define MSK_SPINT   0x01
 430
 431 /* USBIEN bits */
 432 #define MSK_EWUPCPU 0x20
 433 #define MSK_EEORINT 0x10
 434 #define MSK_ESOFINT 0x08
 435 #define MSK_ESPINT  0x01
 436
 437 /* UEPNUM bits */
 438 #define MSK_EPNUM   0x03
 439
 440 /* UEPCONX bits */
 441 #define MSK_EPEN    0x80
 442 #define MSK_NAKIEN  0x40
 443 #define MSK_NAKOUT  0x20
 444 #define MSK_NAKIN   0x10
 445 #define MSK_DTGL    0x08
 446 #define MSK_EPDIR   0x04
 447 #define MSK_EPTYPE  0x03
 448
 449 /* UEPSTAX bits */
 450 #define MSK_DIR     0x80
 451 #define MSK_RXOUTB1 0x40
 452 #define MSK_STALLRQ 0x20
 453 #define MSK_TXRDY   0x10
 454 #define MSK_STLCRC  0x08
 455 #define MSK_RXSETUP 0x04
 456 #define MSK_RXOUTB0 0x02
 457 #define MSK_TXCMP   0x01
 458
 459 /* UEPRST bits */
 460 #define MSK_EPRST   0x07
 461 #define MSK_EP2RST  0x04
 462 #define MSK_EP1RST  0x02
 463 #define MSK_EP0RST  0x01
 464
 465 #define MSK_EPINT   0x07
 466 #define MSK_EP2INT  0x04
 467 #define MSK_EP1INT  0x02
 468 #define MSK_EP0INT  0x01
 469
 470 /* UEPIEN bits */
 471 #define MSK_EPINTE  0x07
 472 #define MSK_EP2INTE 0x04
 473 #define MSK_EP1INTE 0x02
 474 #define MSK_EP0INTE 0x01
 475
 476 /* UBYCTX bits */
 477 #define MSK_BYCT    0x7F
 478
 479 /* UFNUMH bits */
 480 #define MSK_CRCOK   0x20
 481 #define MSK_CRCERR  0x10
 482 #define MSK_FNUM    0x07
 483
 484 /* USBCLK bits */
 485 #define MSK_USBCD   0x03
 486
 487 /* MMCON0 bits */
 488 #define MSK_DRPTR   0x80
 489 #define MSK_DTPTR   0x40
 490 #define MSK_CRPTR   0x20
 491 #define MSK_CTPTR   0x10
 492 #define MSK_MBLOCK  0x08
 493 #define MSK_DFMT    0x04
 494 #define MSK_RFMT    0x02
 495 #define MSK_CRCDIS  0x01
 496
 497 /* MMCON1 bits */
 498 #define MSK_BLEN    0xf0
 499 #define MSK_DATDIR  0x08
 500 #define MSK_DATEN   0x04
 501 #define MSK_RESPEN  0x02
 502 #define MSK_CMDEN   0x01
 503
 504 /* MMCON2 bits */
 505 #define MSK_MMCEN   0x80
 506 #define MSK_DCR     0x40
 507 #define MSK_CCR     0x20
 508 #define MSK_DATD    0x06
 509 #define MSK_FLOWC   0x01
 510
 511 /* MMSTA bits */
 512 #define MSK_CBUSY   0x20
 513 #define MSK_CRC16S  0x10
 514 #define MSK_DATFS   0x08
 515 #define MSK_CRC7S   0x04
 516 #define MSK_RESPFS  0x02
 517 #define MSK_CFLCK   0x01
 518
 519 /* MMINT bits */
 520 #define MSK_MCBI    0x80
 521 #define MSK_EORI    0x40
 522 #define MSK_EOCI    0x20
 523 #define MSK_EOFI    0x10
 524 #define MSK_F2FI    0x08
 525 #define MSK_F1FI    0x04
 526 #define MSK_F2EI    0x02
 527 #define MSK_F1EI    0x01
 528
 529 /* MMMSK bits */
 530 #define MSK_MCBM    0x80
 531 #define MSK_EORM    0x40
 532 #define MSK_EOCM    0x20
 533 #define MSK_EOFM    0x10
 534 #define MSK_F2FM    0x08
 535 #define MSK_F1FM    0x04
 536 #define MSK_F2EM    0x02
 537 #define MSK_F1EM    0x01
 538
 539 /* BDRCON bits */
 540 #define MSK_BRR     0x10
 541 #define MSK_TBCK    0x08
 542 #define MSK_RBCK    0x04
 543 #define MSK_SPD     0x02
 544 #define MSK_M0SRC   0x01
 545
 546 /* SPCON bits */
 547 #define MSK_SPR     0x83
 548 #define MSK_SPEN    0x40
 549 #define MSK_SSDIS   0x20
 550 #define MSK_MSTR    0x10
 551 #define MSK_MODE    0x0C
 552 #define MSK_CPOL    0x08
 553 #define MSK_CPHA    0x04
 554
 555 /* SPSTA bits */
 556 #define MSK_SPIF    0x80
 557 #define MSK_WCOL    0x40
 558 #define MSK_MODF    0x10
 559
 560 /* SSCON bits */
 561 #define MSK_SSCR    0x83
 562 #define MSK_SSPE    0x40
 563 #define MSK_SSSTA   0x20
 564 #define MSK_SSSTO   0x10
 565 #define MSK_SSI     0x08
 566 #define MSK_SSAA    0x04
 567
 568 /* SSSTA bits */
 569 #define MSK_SSC     0xf8
 570
 571 /* SSADR bits */
 572 #define MSK_SSA     0xfe
 573 #define MSK_SSGC    0x01
 574
 575 /* KBCON bits */
 576 #define MSK_KINL    0xf0
 577 #define MSK_KINM    0x0f
 578
 579 /* BKSTA bits */
 580 #define MSK_KPDE    0x80
 581 #define MSK_KINF    0x0f
 582
 583 /* ADCON bits */
 584 #define MSK_ADIDL   0x40
 585 #define MSK_ADEN    0x20
 586 #define MSK_ADEOC   0x10
 587 #define MSK_ADSST   0x80
 588 #define MSK_ADCS    0x01
 589
 590 /* ADCLK bits */
 591 #define MSK_ADCD    0x1f
 592
 593 /* ADDL bits */
 594 #define MSK_ADAT    0x03
 595
 596 /* Interrupt numbers: address = (number * 8) + 3 */
 597 #define IE0_VECTOR      0   /* 0x03 External Interrupt 0 */
 598 #define TF0_VECTOR      1   /* 0x0b Timer 0 */
 599 #define IE1_VECTOR      2   /* 0x13 External Interrupt 1 */
 600 #define TF1_VECTOR      3   /* 0x1b Timer 1 */
 601 #define SIO_VECTOR      4   /* 0x23 Serial port */
 602 #define MP3_VECTOR      5   /* 0x2b MP3 Decoder */
 603 #define AUDIO_VECTOR    6   /* 0x33 Audio Interface */
 604 #define MMC_VECTOR      7   /* 0x3b MMC Interface */
 605 #define TWI_VECTOR      8   /* 0x43 Two Wire Controller */
 606 #define SPI_VECTOR      9   /* 0x4b SPI Controller */
 607 #define ADC_VECTOR      10  /* 0x53 A to D Contverter */
 608 #define KBD_VECTOR      11  /* 0x5b Keyboard */
 609                             /* 0x63 Reserved */
 610 #define USB_VECTOR      13  /* 0x6b USB */
 611                             /* 0x73 Reserved */
 612
 613 #endif