sdcc/device/include/mcs51/at89s8253.h

   1 /*-------------------------------------------------------------------------
   2    at89s8253.h - register Declarations for ATMEL 89S8253 Processors
   3
   4    Copyright (C) 2006, Krzysztof Polomka <del_p AT op.pl>
   5      based on at89S8252.h By - Dipl.-Ing. (FH) Michael Schmitt
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef AT89S8253_H
  31 #define AT89S8253_H
  32
  33 /* BYTE addressable registers */
  34 __sfr __at (0x80) P0          ;
  35 __sfr __at (0x81) SP          ;
  36 __sfr __at (0x82) DPL         ;
  37 __sfr __at (0x82) DP0L        ; /* as called by Atmel */
  38 __sfr __at (0x83) DPH         ;
  39 __sfr __at (0x83) DP0H        ; /* as called by Atmel */
  40 __sfr __at (0x84) DP1L        ; /* at89S8253 specific register */
  41 __sfr __at (0x85) DP1H        ; /* at89S8253 specific register */
  42 __sfr __at (0x86) SPDR        ; /* at89S8253 specific register */
  43 __sfr __at (0x87) PCON        ;
  44 __sfr __at (0x88) TCON        ;
  45 __sfr __at (0x89) TMOD        ;
  46 __sfr __at (0x8A) TL0         ;
  47 __sfr __at (0x8B) TL1         ;
  48 __sfr __at (0x8C) TH0         ;
  49 __sfr __at (0x8D) TH1         ;
  50 __sfr __at (0x8E) AUXR        ; /* at89S8253 specific register */
  51 __sfr __at (0x8F) CLKREG      ; /* at89S8253 specific register */
  52 __sfr __at (0x90) P1          ;
  53 __sfr __at (0x96) EECON       ; /* at89S8253 specific register */
  54 __sfr __at (0x98) SCON        ;
  55 __sfr __at (0x99) SBUF        ;
  56 __sfr __at (0xA0) P2          ;
  57 __sfr __at (0xA6) WDTRST      ; /* at89S8253 specific register */
  58 __sfr __at (0xA7) WDTCON      ; /* at89S8253 specific register */
  59 __sfr __at (0xA8) IE          ;
  60 __sfr __at (0xA9) SADDR       ; /* at89S8253 specific register */
  61 __sfr __at (0xAA) SPSR        ; /* at89S8253 specific register */
  62 __sfr __at (0xB0) P3          ;
  63 __sfr __at (0xB7) IPH         ; /* at89S8253 specific register */
  64 __sfr __at (0xB8) IP          ;
  65 __sfr __at (0xB9) SADEN       ; /* at89S8253 specific register */
  66 __sfr __at (0xC8) T2CON       ;
  67 __sfr __at (0xC9) T2MOD       ;
  68 __sfr __at (0xCA) RCAP2L      ;
  69 __sfr __at (0xCB) RCAP2H      ;
  70 __sfr __at (0xCC) TL2         ;
  71 __sfr __at (0xCD) TH2         ;
  72 __sfr __at (0xD0) PSW         ;
  73 __sfr __at (0xD5) SPCR        ; /* at89S8253 specific register */
  74 __sfr __at (0xE0) ACC         ;
  75 __sfr __at (0xE0) A           ;
  76 __sfr __at (0xF0) B           ;
  77
  78
  79 /* BIT addressable registers */
  80 /* P0 */
  81 __sbit __at (0x80) P0_0       ;
  82 __sbit __at (0x81) P0_1       ;
  83 __sbit __at (0x82) P0_2       ;
  84 __sbit __at (0x83) P0_3       ;
  85 __sbit __at (0x84) P0_4       ;
  86 __sbit __at (0x85) P0_5       ;
  87 __sbit __at (0x86) P0_6       ;
  88 __sbit __at (0x87) P0_7       ;
  89
  90 /* TCON */
  91 __sbit __at (0x88) IT0        ;
  92 __sbit __at (0x89) IE0        ;
  93 __sbit __at (0x8A) IT1        ;
  94 __sbit __at (0x8B) IE1        ;
  95 __sbit __at (0x8C) TR0        ;
  96 __sbit __at (0x8D) TF0        ;
  97 __sbit __at (0x8E) TR1        ;
  98 __sbit __at (0x8F) TF1        ;
  99
 100 /* P1 */
 101 __sbit __at (0x90) P1_0       ;
 102 __sbit __at (0x91) P1_1       ;
 103 __sbit __at (0x92) P1_2       ;
 104 __sbit __at (0x93) P1_3       ;
 105 __sbit __at (0x94) P1_4       ;
 106 __sbit __at (0x95) P1_5       ;
 107 __sbit __at (0x96) P1_6       ;
 108 __sbit __at (0x97) P1_7       ;
 109
 110 __sbit __at (0x90) T2         ;
 111 __sbit __at (0x91) T2EX       ;
 112
 113 /* P1 SPI portpins */
 114 __sbit __at (0x94) SS         ; /* SPI: SS - Slave port select input */
 115 __sbit __at (0x95) MOSI       ; /* SPI: MOSI - Master data output, slave data input */
 116 __sbit __at (0x96) MISO       ; /* SPI: MISO - Master data input, slave data output */
 117 __sbit __at (0x97) SCK        ; /* SPI: SCK - Master clock output, slave clock input */
 118
 119
 120 /* SCON */
 121 __sbit __at (0x98) RI         ;
 122 __sbit __at (0x99) TI         ;
 123 __sbit __at (0x9A) RB8        ;
 124 __sbit __at (0x9B) TB8        ;
 125 __sbit __at (0x9C) REN        ;
 126 __sbit __at (0x9D) SM2        ;
 127 __sbit __at (0x9E) SM1        ;
 128 __sbit __at (0x9F) SM0        ;
 129
 130 /* P2 */
 131 __sbit __at (0xA0) P2_0       ;
 132 __sbit __at (0xA1) P2_1       ;
 133 __sbit __at (0xA2) P2_2       ;
 134 __sbit __at (0xA3) P2_3       ;
 135 __sbit __at (0xA4) P2_4       ;
 136 __sbit __at (0xA5) P2_5       ;
 137 __sbit __at (0xA6) P2_6       ;
 138 __sbit __at (0xA7) P2_7       ;
 139
 140 /* IE */
 141 __sbit __at (0xA8) EX0        ;
 142 __sbit __at (0xA9) ET0        ;
 143 __sbit __at (0xAA) EX1        ;
 144 __sbit __at (0xAB) ET1        ;
 145 __sbit __at (0xAC) ES         ;
 146 __sbit __at (0xAD) ET2        ;
 147 __sbit __at (0xAF) EA         ;
 148
 149 /* P3 */
 150 __sbit __at (0xB0) P3_0       ;
 151 __sbit __at (0xB1) P3_1       ;
 152 __sbit __at (0xB2) P3_2       ;
 153 __sbit __at (0xB3) P3_3       ;
 154 __sbit __at (0xB4) P3_4       ;
 155 __sbit __at (0xB5) P3_5       ;
 156 __sbit __at (0xB6) P3_6       ;
 157 __sbit __at (0xB7) P3_7       ;
 158
 159 __sbit __at (0xB0) RXD        ;
 160 __sbit __at (0xB1) TXD        ;
 161 __sbit __at (0xB2) INT0       ;
 162 __sbit __at (0xB3) INT1       ;
 163 __sbit __at (0xB4) T0         ;
 164 __sbit __at (0xB5) T1         ;
 165 __sbit __at (0xB6) WR         ;
 166 __sbit __at (0xB7) RD         ;
 167
 168 /* IP */
 169 __sbit __at (0xB8) PX0        ;
 170 __sbit __at (0xB9) PT0        ;
 171 __sbit __at (0xBA) PX1        ;
 172 __sbit __at (0xBB) PT1        ;
 173 __sbit __at (0xBC) PS         ;
 174 __sbit __at (0xBD) PT2        ;
 175
 176 /* T2CON */
 177 __sbit __at (0xC8) T2CON_0    ;
 178 __sbit __at (0xC9) T2CON_1    ;
 179 __sbit __at (0xCA) T2CON_2    ;
 180 __sbit __at (0xCB) T2CON_3    ;
 181 __sbit __at (0xCC) T2CON_4    ;
 182 __sbit __at (0xCD) T2CON_5    ;
 183 __sbit __at (0xCE) T2CON_6    ;
 184 __sbit __at (0xCF) T2CON_7    ;
 185
 186 __sbit __at (0xC8) CP_RL2     ;
 187 __sbit __at (0xC9) C_T2       ;
 188 __sbit __at (0xCA) TR2        ;
 189 __sbit __at (0xCB) EXEN2      ;
 190 __sbit __at (0xCC) TCLK       ;
 191 __sbit __at (0xCD) RCLK       ;
 192 __sbit __at (0xCE) EXF2       ;
 193 __sbit __at (0xCF) TF2        ;
 194
 195 /* PSW */
 196 __sbit __at (0xD0) P          ;
 197 __sbit __at (0xD1) FL         ;
 198 __sbit __at (0xD2) OV         ;
 199 __sbit __at (0xD3) RS0        ;
 200 __sbit __at (0xD4) RS1        ;
 201 __sbit __at (0xD5) F0         ;
 202 __sbit __at (0xD6) AC         ;
 203 __sbit __at (0xD7) CY         ;
 204
 205 /* B */
 206 __sbit __at (0xF0) BREG_F0    ;
 207 __sbit __at (0xF1) BREG_F1    ;
 208 __sbit __at (0xF2) BREG_F2    ;
 209 __sbit __at (0xF3) BREG_F3    ;
 210 __sbit __at (0xF4) BREG_F4    ;
 211 __sbit __at (0xF5) BREG_F5    ;
 212 __sbit __at (0xF6) BREG_F6    ;
 213 __sbit __at (0xF7) BREG_F7    ;
 214
 215
 216 /* BIT definitions for bits that are not directly accessible */
 217 /* PCON bits */
 218 #define IDL             0x01
 219 #define PD              0x02
 220 #define GF0             0x04
 221 #define GF1             0x08
 222 #define SMOD            0x80
 223
 224 #define IDL_            0x01
 225 #define PD_             0x02
 226 #define GF0_            0x04
 227 #define GF1_            0x08
 228 #define SMOD_           0x80
 229
 230 /* TMOD bits */
 231 #define M0_0            0x01
 232 #define M1_0            0x02
 233 #define C_T0            0x04
 234 #define GATE0           0x08
 235 #define M0_1            0x10
 236 #define M1_1            0x20
 237 #define C_T1            0x40
 238 #define GATE1           0x80
 239
 240 #define M0_0_           0x01
 241 #define M1_0_           0x02
 242 #define C_T0_           0x04
 243 #define GATE0_          0x08
 244 #define M0_1_           0x10
 245 #define M1_1_           0x20
 246 #define C_T1_           0x40
 247 #define GATE1_          0x80
 248
 249 #define T0_M0           0x01
 250 #define T0_M1           0x02
 251 #define T0_CT           0x04
 252 #define T0_GATE         0x08
 253 #define T1_M0           0x10
 254 #define T1_M1           0x20
 255 #define T1_CT           0x40
 256 #define T1_GATE         0x80
 257
 258 #define T0_M0_          0x01
 259 #define T0_M1_          0x02
 260 #define T0_CT_          0x04
 261 #define T0_GATE_        0x08
 262 #define T1_M0_          0x10
 263 #define T1_M1_          0x20
 264 #define T1_CT_          0x40
 265 #define T1_GATE_        0x80
 266
 267 #define T0_MASK         0x0F
 268 #define T1_MASK         0xF0
 269
 270 #define T0_MASK_        0x0F
 271 #define T1_MASK_        0xF0
 272
 273 /* T2MOD bits */
 274 #define DCEN            0x01
 275 #define T2OE            0x02
 276
 277 #define DCEN_           0x01
 278 #define T2OE_           0x02
 279
 280 /* EECON bits */
 281 #define EECON_WRTINH    0x01
 282 #define EECON_RDY       0x02
 283 #define EECON_DPS       0x04
 284 #define EECON_EEMEN     0x08
 285 #define EECON_EEMWE     0x10
 286 #define EECON_EELD      0x20
 287
 288 /* WDTCON bits */
 289 #define WDTCON_WDTEN    0x01
 290 #define WDTCON_WSWRST   0x02
 291 #define WDTCON_HWDT     0x04
 292 #define WDTCON_DISRTO   0x08
 293 #define WDTCON_WDIDLE   0x10
 294 #define WDTCON_PS0      0x20
 295 #define WDTCON_PS1      0x40
 296 #define WDTCON_PS2      0x80
 297
 298 /* SPCR-SPI bits */
 299 #define SPCR_SPR0       0x01
 300 #define SPCR_SPR1       0x02
 301 #define SPCR_CPHA       0x04
 302 #define SPCR_CPOL       0x08
 303 #define SPCR_MSTR       0x10
 304 #define SPCR_DORD       0x20
 305 #define SPCR_SPE        0x40
 306 #define SPCR_SPIE       0x80
 307
 308 /* SPSR-SPI bits */
 309 #define SPSR_ENH        0x01
 310 #define SPSR_DISSO      0x02
 311 #define SPSR_LDEN       0x20
 312 #define SPSR_WCOL       0x40
 313 #define SPSR_SPIF       0x80
 314
 315 /* SPDR-SPI bits */
 316 #define SPDR_SPD0       0x01
 317 #define SPDR_SPD1       0x02
 318 #define SPDR_SPD2       0x04
 319 #define SPDR_SPD3       0x08
 320 #define SPDR_SPD4       0x10
 321 #define SPDR_SPD5       0x20
 322 #define SPDR_SPD6       0x40
 323 #define SPDR_SPD7       0x80
 324
 325 /* IPH bits */
 326 #define IPH_PX0H        0x01
 327 #define IPH_PT0H        0x02
 328 #define IPH_PX1H        0x04
 329 #define IPH_PT1H        0x08
 330 #define IPH_PSH         0x10
 331 #define IPH_PT2H        0x20
 332
 333 /* Interrupt numbers: address = (number * 8) + 3 */
 334 #define IE0_VECTOR      0       /* 0x03 external interrupt 0 */
 335 #define EX0_VECTOR      0       /* 0x03 external interrupt 0 */
 336 #define TF0_VECTOR      1       /* 0x0b timer 0 */
 337 #define IE1_VECTOR      2       /* 0x13 external interrupt 1 */
 338 #define EX1_VECTOR      2       /* 0x13 external interrupt 1 */
 339 #define TF1_VECTOR      3       /* 0x1b timer 1 */
 340 #define SI0_VECTOR      4       /* 0x23 serial port 0 */
 341 #define TF2_VECTOR      5       /* 0x2B timer 2 */
 342 #define EX2_VECTOR      5       /* 0x2B external interrupt 2 */
 343
 344 /* AUXR bits */
 345 #define AUXR_DISALE          0x01
 346 #define AUXR_INTEL_PWD_EXIT  0x02
 347
 348 /* CLKREG bits */
 349 #define CLKREG_X2         0x01
 350
 351 /* This is one of the addons coming from Bernd Krueger-Knauber   */
 352
 353 /* ALE (0x8E) Bit Values */
 354 __sfr __at (0x8E) ALE;      /* at89S8252 specific register */
 355
 356 /* Macro to enable and disable the toggling of the ALE-pin (EMV) */
 357
 358 /* Explanation : Original Intel 8051 Cores (Atmel has to use the */
 359 /* Intel Core) have a feature that ALE is only active during     */
 360 /* MOVX or MOVC instruction. Otherwise the ALE-Pin is weakly     */
 361 /* pulled high. This can be used to force some external devices  */
 362 /* into standby mode and reduced EMI noise                       */
 363
 364 #define ALE_OFF  ALE = ALE | 0x01
 365 #define ALE_ON   ALE = ALE & 0xFE
 366
 367 #endif