sdcc/device/include/mcs51/at89x51.h

   1 /*-------------------------------------------------------------------------
   2    at89x51.h - register declarations for ATMEL 89x51 processors
   3
   4    Copyright (C) 1999, Bernd Bartmann <bernd.bartmann AT gmail.com>
   5
   6    Based on reg51.h by Sandeep Dutta sandeep.dutta AT usa.net
   7    KEIL C compatible definitions are included
   8
   9    This library is free software; you can redistribute it and/or modify it
  10    under the terms of the GNU General Public License as published by the
  11    Free Software Foundation; either version 2, or (at your option) any
  12    later version.
  13
  14    This library is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with this library; see the file COPYING. If not, write to the
  21    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  22    MA 02110-1301, USA.
  23
  24    As a special exception, if you link this library with other files,
  25    some of which are compiled with SDCC, to produce an executable,
  26    this library does not by itself cause the resulting executable to
  27    be covered by the GNU General Public License. This exception does
  28    not however invalidate any other reasons why the executable file
  29    might be covered by the GNU General Public License.
  30 -------------------------------------------------------------------------*/
  31
  32 #ifndef AT89x51_H
  33 #define AT89x51_H
  34
  35 #include <compiler.h>
  36
  37 /* BYTE addressable registers */
  38 SFR(P0,         0x80);
  39 SFR(SP,         0x81);
  40 SFR(DPL,        0x82);
  41 SFR(DPH,        0x83);
  42 SFR(PCON,       0x87);
  43 SFR(TCON,       0x88);
  44 SFR(TMOD,       0x89);
  45 SFR(TL0,        0x8A);
  46 SFR(TL1,        0x8B);
  47 SFR(TH0,        0x8C);
  48 SFR(TH1,        0x8D);
  49 SFR(P1,         0x90);
  50 SFR(SCON,       0x98);
  51 SFR(SBUF,       0x99);
  52 SFR(P2,         0xA0);
  53 SFR(IE,         0xA8);
  54 SFR(P3,         0xB0);
  55 SFR(IP,         0xB8);
  56 SFR(PSW,        0xD0);
  57 SFR(ACC,        0xE0);
  58 SFR(A,          0xE0);
  59 SFR(B,          0xF0);
  60
  61
  62 /* BIT addressable registers */
  63 /* P0 */
  64 SBIT(P0_0,      0x80,   0);
  65 SBIT(P0_1,      0x80,   1);
  66 SBIT(P0_2,      0x80,   2);
  67 SBIT(P0_3,      0x80,   3);
  68 SBIT(P0_4,      0x80,   4);
  69 SBIT(P0_5,      0x80,   5);
  70 SBIT(P0_6,      0x80,   6);
  71 SBIT(P0_7,      0x80,   7);
  72
  73 /* TCON */
  74 SBIT(IT0,       0x88,   0);
  75 SBIT(IE0,       0x88,   1);
  76 SBIT(IT1,       0x88,   2);
  77 SBIT(IE1,       0x88,   3);
  78 SBIT(TR0,       0x88,   4);
  79 SBIT(TF0,       0x88,   5);
  80 SBIT(TR1,       0x88,   E);
  81 SBIT(TF1,       0x88,   7);
  82
  83 /* P1 */
  84 SBIT(P1_0,      0x90,   0);
  85 SBIT(P1_1,      0x90,   1);
  86 SBIT(P1_2,      0x90,   2);
  87 SBIT(P1_3,      0x90,   3);
  88 SBIT(P1_4,      0x90,   4);
  89 SBIT(P1_5,      0x90,   5);
  90 SBIT(P1_6,      0x90,   6);
  91 SBIT(P1_7,      0x90,   7);
  92
  93 /* SCON */
  94 SBIT(RI,        0x98,   0);
  95 SBIT(TI,        0x98,   1);
  96 SBIT(RB8,       0x98,   2);
  97 SBIT(TB8,       0x98,   3);
  98 SBIT(REN,       0x98,   4);
  99 SBIT(SM2,       0x98,   5);
 100 SBIT(SM1,       0x98,   6);
 101 SBIT(SM0,       0x98,   7);
 102
 103 /* P2 */
 104 SBIT(P2_0,      0xA0,   0);
 105 SBIT(P2_1,      0xA0,   1);
 106 SBIT(P2_2,      0xA0,   2);
 107 SBIT(P2_3,      0xA0,   3);
 108 SBIT(P2_4,      0xA0,   4);
 109 SBIT(P2_5,      0xA0,   5);
 110 SBIT(P2_6,      0xA0,   6);
 111 SBIT(P2_7,      0xA0,   7);
 112
 113 /* IE */
 114 SBIT(EX0,       0xA8,   0);
 115 SBIT(ET0,       0xA8,   1);
 116 SBIT(EX1,       0xA8,   2);
 117 SBIT(ET1,       0xA8,   3);
 118 SBIT(ES,        0xA8,   4);
 119 SBIT(EA,        0xA8,   7);
 120
 121 /* P3 */
 122 SBIT(P3_0,      0xB0,   0);
 123 SBIT(P3_1,      0xB0,   1);
 124 SBIT(P3_2,      0xB0,   2);
 125 SBIT(P3_3,      0xB0,   3);
 126 SBIT(P3_4,      0xB0,   4);
 127 SBIT(P3_5,      0xB0,   5);
 128 SBIT(P3_6,      0xB0,   6);
 129 SBIT(P3_7,      0xB0,   7);
 130
 131 SBIT(RXD,       0xB0,   0);
 132 SBIT(TXD,       0xB0,   1);
 133 SBIT(INT0,      0xB0,   2);
 134 SBIT(INT1,      0xB0,   3);
 135 SBIT(T0,        0xB0,   4);
 136 SBIT(T1,        0xB0,   5);
 137 SBIT(WR,        0xB0,   6);
 138 SBIT(RD,        0xB0,   7);
 139
 140 /* IP */
 141 SBIT(PX0,       0xB8,   0);
 142 SBIT(PT0,       0xB8,   1);
 143 SBIT(PX1,       0xB8,   2);
 144 SBIT(PT1,       0xB8,   3);
 145 SBIT(PS,        0xB8,   4);
 146
 147 /* PSW */
 148 SBIT(P,         0xD0,   0);
 149 SBIT(FL,        0xD0,   1);
 150 SBIT(OV,        0xD0,   2);
 151 SBIT(RS0,       0xD0,   3);
 152 SBIT(RS1,       0xD0,   4);
 153 SBIT(F0,        0xD0,   5);
 154 SBIT(AC,        0xD0,   6);
 155 SBIT(CY,        0xD0,   7);
 156
 157
 158 /* BIT definitions for bits that are not directly accessible */
 159 /* PCON bits */
 160 #define IDL             0x01
 161 #define PD              0x02
 162 #define GF0             0x04
 163 #define GF1             0x08
 164 #define SMOD            0x80
 165
 166 #define IDL_            0x01
 167 #define PD_             0x02
 168 #define GF0_            0x04
 169 #define GF1_            0x08
 170 #define SMOD_           0x80
 171
 172 /* TMOD bits */
 173 #define M0_0            0x01
 174 #define M1_0            0x02
 175 #define C_T0            0x04
 176 #define GATE0           0x08
 177 #define M0_1            0x10
 178 #define M1_1            0x20
 179 #define C_T1            0x40
 180 #define GATE1           0x80
 181
 182 #define M0_0_           0x01
 183 #define M1_0_           0x02
 184 #define C_T0_           0x04
 185 #define GATE0_          0x08
 186 #define M0_1_           0x10
 187 #define M1_1_           0x20
 188 #define C_T1_           0x40
 189 #define GATE1_          0x80
 190
 191 #define T0_M0           0x01
 192 #define T0_M1           0x02
 193 #define T0_CT           0x04
 194 #define T0_GATE         0x08
 195 #define T1_M0           0x10
 196 #define T1_M1           0x20
 197 #define T1_CT           0x40
 198 #define T1_GATE         0x80
 199
 200 #define T0_M0_          0x01
 201 #define T0_M1_          0x02
 202 #define T0_CT_          0x04
 203 #define T0_GATE_        0x08
 204 #define T1_M0_          0x10
 205 #define T1_M1_          0x20
 206 #define T1_CT_          0x40
 207 #define T1_GATE_        0x80
 208
 209 #define T0_MASK         0x0F
 210 #define T1_MASK         0xF0
 211
 212 #define T0_MASK_        0x0F
 213 #define T1_MASK_        0xF0
 214
 215
 216 /* Interrupt numbers: address = (number * 8) + 3 */
 217 #define IE0_VECTOR      0       /* 0x03 external interrupt 0 */
 218 #define TF0_VECTOR      1       /* 0x0b timer 0 */
 219 #define IE1_VECTOR      2       /* 0x13 external interrupt 1 */
 220 #define TF1_VECTOR      3       /* 0x1b timer 1 */
 221 #define SI0_VECTOR      4       /* 0x23 serial port 0 */
 222
 223 #endif