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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / ax8052f142.h
blob3a2ee0060f22c182043947e6bae79136b4e62aa7
1 /*-------------------------------------------------------------------------
2 AX8052F142.h - Register Declarations for the Axsem Microfoot Processor Range
3
4 Copyright (C) 2010, 2011, Axsem AG
5 Author: Thomas Sailer, thomas.sailer@axsem.com
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2.1, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30
31 #ifndef AX8052F142_H
32 #define AX8052F142_H
33
34 #include <compiler.h>
35
36 /* SFR Address Space */
37
38 SFR(ACC, 0xE0); /* Accumulator */
39 SBIT(ACC_0, 0xE0, 0); /* Accumulator bit 0 */
40 SBIT(ACC_1, 0xE0, 1); /* Accumulator bit 1 */
41 SBIT(ACC_2, 0xE0, 2); /* Accumulator bit 2 */
42 SBIT(ACC_3, 0xE0, 3); /* Accumulator bit 3 */
43 SBIT(ACC_4, 0xE0, 4); /* Accumulator bit 4 */
44 SBIT(ACC_5, 0xE0, 5); /* Accumulator bit 5 */
45 SBIT(ACC_6, 0xE0, 6); /* Accumulator bit 6 */
46 SBIT(ACC_7, 0xE0, 7); /* Accumulator bit 7 */
47 SFR(B, 0xF0); /* B Register */
48 SBIT(B_0, 0xF0, 0); /* Register B bit 0 */
49 SBIT(B_1, 0xF0, 1); /* Register B bit 1 */
50 SBIT(B_2, 0xF0, 2); /* Register B bit 2 */
51 SBIT(B_3, 0xF0, 3); /* Register B bit 3 */
52 SBIT(B_4, 0xF0, 4); /* Register B bit 4 */
53 SBIT(B_5, 0xF0, 5); /* Register B bit 5 */
54 SBIT(B_6, 0xF0, 6); /* Register B bit 6 */
55 SBIT(B_7, 0xF0, 7); /* Register B bit 7 */
56 SFR(DPH, 0x83); /* Data Pointer 0 High Byte */
57 SFR(DPH1, 0x85); /* Data Pointer 1 High Byte */
58 SFR(DPL, 0x82); /* Data Pointer 0 Low Byte */
59 SFR(DPL1, 0x84); /* Data Pointer 1 Low Byte */
60 SFR16(DPTR0, 0x82); /* Data Pointer 0 */
61 SFR16(DPTR1, 0x84); /* Data Pointer 1 */
62 SFR(DPS, 0x86); /* Data Pointer Select */
63 SFR(E2IE, 0xA0); /* 2nd Extended Interrupt Enable */
64 SBIT(E2IE_0, 0xA0, 0); /* Output Compare 0 Interrupt Enable */
65 SBIT(E2IE_1, 0xA0, 1); /* Output Compare 1 Interrupt Enable */
66 SBIT(E2IE_2, 0xA0, 2); /* Input Capture 0 Interrupt Enable */
67 SBIT(E2IE_3, 0xA0, 3); /* Input Capture 1 Interrupt Enable */
68 SBIT(E2IE_4, 0xA0, 4); /* Random Number Generator Interrupt Enable */
69 SBIT(E2IE_5, 0xA0, 5); /* AES Interrupt Enable */
70 SBIT(E2IE_6, 0xA0, 6); /* DebugLink Interrupt Enable */
71 SBIT(E2IE_7, 0xA0, 7); /* */
72 SFR(E2IP, 0xC0); /* 2nd Extended Interrupt Priority */
73 SBIT(E2IP_0, 0xC0, 0); /* Output Compare 0 Interrupt Priority */
74 SBIT(E2IP_1, 0xC0, 1); /* Output Compare 1 Interrupt Priority */
75 SBIT(E2IP_2, 0xC0, 2); /* Input Capture 0 Interrupt Priority */
76 SBIT(E2IP_3, 0xC0, 3); /* Input Capture 1 Interrupt Priority */
77 SBIT(E2IP_4, 0xC0, 4); /* Random Number Generator Interrupt Priority */
78 SBIT(E2IP_5, 0xC0, 5); /* AES Interrupt Priority */
79 SBIT(E2IP_6, 0xC0, 6); /* DebugLink Interrupt Priority */
80 SBIT(E2IP_7, 0xC0, 7); /* */
81 SFR(EIE, 0x98); /* Extended Interrupt Enable */
82 SBIT(EIE_0, 0x98, 0); /* Timer 0 Interrupt Enable */
83 SBIT(EIE_1, 0x98, 1); /* Timer 1 Interrupt Enable */
84 SBIT(EIE_2, 0x98, 2); /* Timer 2 Interrupt Enable */
85 SBIT(EIE_3, 0x98, 3); /* SPI 0 Interrupt Enable */
86 SBIT(EIE_4, 0x98, 4); /* UART 0 Interrupt Enable */
87 SBIT(EIE_5, 0x98, 5); /* UART 1 Interrupt Enable */
88 SBIT(EIE_6, 0x98, 6); /* GPADC Interrupt Enable */
89 SBIT(EIE_7, 0x98, 7); /* DMA Interrupt Enable */
90 SFR(EIP, 0xB0); /* Extended Interrupt Priority */
91 SBIT(EIP_0, 0xB0, 0); /* Timer 0 Interrupt Priority */
92 SBIT(EIP_1, 0xB0, 1); /* Timer 1 Interrupt Priority */
93 SBIT(EIP_2, 0xB0, 2); /* Timer 2 Interrupt Priority */
94 SBIT(EIP_3, 0xB0, 3); /* SPI 0 Interrupt Priority */
95 SBIT(EIP_4, 0xB0, 4); /* UART 0 Interrupt Priority */
96 SBIT(EIP_5, 0xB0, 5); /* UART 1 Interrupt Priority */
97 SBIT(EIP_6, 0xB0, 6); /* GPADC Interrupt Priority */
98 SBIT(EIP_7, 0xB0, 7); /* DMA Interrupt Priority */
99 SFR(IE, 0xA8); /* Interrupt Enable */
100 SBIT(IE_0, 0xA8, 0); /* External 0 Interrupt Enable */
101 SBIT(IE_1, 0xA8, 1); /* Wakeup Timer Interrupt Enable */
102 SBIT(IE_2, 0xA8, 2); /* External 1 Interrupt Enable */
103 SBIT(IE_3, 0xA8, 3); /* GPIO Interrupt Enable */
104 SBIT(IE_4, 0xA8, 4); /* Radio Interrupt Enable */
105 SBIT(IE_5, 0xA8, 5); /* Clock Management Interrupt Enable */
106 SBIT(IE_6, 0xA8, 6); /* Power Management Interrupt Enable */
107 SBIT(IE_7, 0xA8, 7); /* Global Interrupt Enable */
108 SBIT(EA, 0xA8, 7); /* Global Interrupt Enable */
109 SFR(IP, 0xB8); /* Interrupt Priority */
110 SBIT(IP_0, 0xB8, 0); /* External 0 Interrupt Priority */
111 SBIT(IP_1, 0xB8, 1); /* Wakeup Timer Interrupt Priority */
112 SBIT(IP_2, 0xB8, 2); /* External 1 Interrupt Priority */
113 SBIT(IP_3, 0xB8, 3); /* GPIO Interrupt Priority */
114 SBIT(IP_4, 0xB8, 4); /* Radio Interrupt Priority */
115 SBIT(IP_5, 0xB8, 5); /* Clock Management Interrupt Priority */
116 SBIT(IP_6, 0xB8, 6); /* Power Management Interrupt Priority */
117 SBIT(IP_7, 0xB8, 7); /* */
118 SFR(PCON, 0x87); /* Power Mode Control */
119 SFR(PSW, 0xD0); /* Program Status Word */
120 SBIT(P, 0xD0, 0); /* Parity Flag */
121 SBIT(F1, 0xD0, 1); /* User-Defined Flag */
122 SBIT(OV, 0xD0, 2); /* Overflow Flag */
123 SBIT(RS0, 0xD0, 3); /* Register Bank Select 0 */
124 SBIT(RS1, 0xD0, 4); /* Register Bank Select 1 */
125 SBIT(F0, 0xD0, 5); /* User-Defined Flag */
126 SBIT(AC, 0xD0, 6); /* Auxiliary Carry Flag */
127 SBIT(CY, 0xD0, 7); /* Carry Flag */
128 SFR(SP, 0x81); /* Stack Pointer */
129 SFR(WBTEST, 0x8F); /* Debug Breakpoint Register */
130 SFR(XPAGE, 0xD9); /* Memory Page Select */
131 SFR(_XPAGE, 0xD9); /* Memory Page Select, SDCC name */
132 SFR(ADCCH0CONFIG, 0xCA); /* ADC Channel 0 Configuration */
133 SFR(ADCCH1CONFIG, 0xCB); /* ADC Channel 1 Configuration */
134 SFR(ADCCH2CONFIG, 0xD2); /* ADC Channel 2 Configuration */
135 SFR(ADCCH3CONFIG, 0xD3); /* ADC Channel 3 Configuration */
136 SFR(ADCCLKSRC, 0xD1); /* ADC Clock Source */
137 SFR(ADCCONV, 0xC9); /* ADC Conversion Source */
138 SFR(ANALOGCOMP, 0xE1); /* Analog Comparators */
139 SFR(CLKCON, 0xC6); /* Clock Control */
140 SFR(CLKSTAT, 0xC7); /* Clock Status */
141 SFR(CODECONFIG, 0x97); /* Code Space Configuration */
142 SFR(DBGLNKBUF, 0xE3); /* Debug Link Buffer */
143 SFR(DBGLNKSTAT, 0xE2); /* Debug Link Status */
144 SFR(DIRA, 0x89); /* Port A Direction */
145 SFR(DIRB, 0x8A); /* Port B Direction */
146 SFR(DIRC, 0x8B); /* Port C Direction */
147 SFR(DIRR, 0x8E); /* Port R Direction */
148 SFR(PINA, 0xC8); /* Port A Input */
149 SBIT(PINA_0, 0xC8, 0); /* */
150 SBIT(PINA_1, 0xC8, 1); /* */
151 SBIT(PINA_2, 0xC8, 2); /* */
152 SBIT(PINA_3, 0xC8, 3); /* */
153 SBIT(PINA_4, 0xC8, 4); /* */
154 SBIT(PINA_5, 0xC8, 5); /* */
155 SBIT(PINA_6, 0xC8, 6); /* */
156 SBIT(PINA_7, 0xC8, 7); /* */
157 SFR(PINB, 0xE8); /* Port B Input */
158 SBIT(PINB_0, 0xE8, 0); /* */
159 SBIT(PINB_1, 0xE8, 1); /* */
160 SBIT(PINB_2, 0xE8, 2); /* */
161 SBIT(PINB_3, 0xE8, 3); /* */
162 SBIT(PINB_4, 0xE8, 4); /* */
163 SBIT(PINB_5, 0xE8, 5); /* */
164 SBIT(PINB_6, 0xE8, 6); /* */
165 SBIT(PINB_7, 0xE8, 7); /* */
166 SFR(PINC, 0xF8); /* Port C Input */
167 SBIT(PINC_0, 0xF8, 0); /* */
168 SBIT(PINC_1, 0xF8, 1); /* */
169 SBIT(PINC_2, 0xF8, 2); /* */
170 SBIT(PINC_3, 0xF8, 3); /* */
171 SBIT(PINC_4, 0xF8, 4); /* */
172 SBIT(PINC_5, 0xF8, 5); /* */
173 SBIT(PINC_6, 0xF8, 6); /* */
174 SBIT(PINC_7, 0xF8, 7); /* */
175 SFR(PINR, 0x8D); /* Port R Input */
176 SFR(PORTA, 0x80); /* Port A Output */
177 SBIT(PORTA_0, 0x80, 0); /* */
178 SBIT(PORTA_1, 0x80, 1); /* */
179 SBIT(PORTA_2, 0x80, 2); /* */
180 SBIT(PORTA_3, 0x80, 3); /* */
181 SBIT(PORTA_4, 0x80, 4); /* */
182 SBIT(PORTA_5, 0x80, 5); /* */
183 SBIT(PORTA_6, 0x80, 6); /* */
184 SBIT(PORTA_7, 0x80, 7); /* */
185 SFR(PORTB, 0x88); /* Port B Output */
186 SBIT(PORTB_0, 0x88, 0); /* */
187 SBIT(PORTB_1, 0x88, 1); /* */
188 SBIT(PORTB_2, 0x88, 2); /* */
189 SBIT(PORTB_3, 0x88, 3); /* */
190 SBIT(PORTB_4, 0x88, 4); /* */
191 SBIT(PORTB_5, 0x88, 5); /* */
192 SBIT(PORTB_6, 0x88, 6); /* */
193 SBIT(PORTB_7, 0x88, 7); /* */
194 SFR(PORTC, 0x90); /* Port C Output */
195 SBIT(PORTC_0, 0x90, 0); /* */
196 SBIT(PORTC_1, 0x90, 1); /* */
197 SBIT(PORTC_2, 0x90, 2); /* */
198 SBIT(PORTC_3, 0x90, 3); /* */
199 SBIT(PORTC_4, 0x90, 4); /* */
200 SBIT(PORTC_5, 0x90, 5); /* */
201 SBIT(PORTC_6, 0x90, 6); /* */
202 SBIT(PORTC_7, 0x90, 7); /* */
203 SFR(PORTR, 0x8C); /* Port R Output */
204 SFR(IC0CAPT0, 0xCE); /* Input Capture 0 Low Byte */
205 SFR(IC0CAPT1, 0xCF); /* Input Capture 0 High Byte */
206 SFR16(IC0CAPT, 0xCE); /* Input Capture 0 */
207 SFR(IC0MODE, 0xCC); /* Input Capture 0 Mode */
208 SFR(IC0STATUS, 0xCD); /* Input Capture 0 Status */
209 SFR(IC1CAPT0, 0xD6); /* Input Capture 1 Low Byte */
210 SFR(IC1CAPT1, 0xD7); /* Input Capture 1 High Byte */
211 SFR16(IC1CAPT, 0xD6); /* Input Capture 1 */
212 SFR(IC1MODE, 0xD4); /* Input Capture 1 Mode */
213 SFR(IC1STATUS, 0xD5); /* Input Capture 1 Status */
214 SFR(NVADDR0, 0x92); /* Non-Volatile Memory Address Low Byte */
215 SFR(NVADDR1, 0x93); /* Non-Volatile Memory Address High Byte */
216 SFR16(NVADDR, 0x92); /* Non-Volatile Memory Address */
217 SFR(NVDATA0, 0x94); /* Non-Volatile Memory Data Low Byte */
218 SFR(NVDATA1, 0x95); /* Non-Volatile Memory Data High Byte */
219 SFR16(NVDATA, 0x94); /* Non-Volatile Memory Data */
220 SFR(NVKEY, 0x96); /* Non-Volatile Memory Write/Erase Key */
221 SFR(NVSTATUS, 0x91); /* Non-Volatile Memory Command / Status */
222 SFR(OC0COMP0, 0xBC); /* Output Compare 0 Low Byte */
223 SFR(OC0COMP1, 0xBD); /* Output Compare 0 High Byte */
224 SFR16(OC0COMP, 0xBC); /* Output Compare 0 */
225 SFR(OC0MODE, 0xB9); /* Output Compare 0 Mode */
226 SFR(OC0PIN, 0xBA); /* Output Compare 0 Pin Configuration */
227 SFR(OC0STATUS, 0xBB); /* Output Compare 0 Status */
228 SFR(OC1COMP0, 0xC4); /* Output Compare 1 Low Byte */
229 SFR(OC1COMP1, 0xC5); /* Output Compare 1 High Byte */
230 SFR16(OC1COMP, 0xC4); /* Output Compare 1 */
231 SFR(OC1MODE, 0xC1); /* Output Compare 1 Mode */
232 SFR(OC1PIN, 0xC2); /* Output Compare 1 Pin Configuration */
233 SFR(OC1STATUS, 0xC3); /* Output Compare 1 Status */
234 SFR(RADIOACC, 0xB1); /* Radio Controller Access Mode */
235 SFR(RADIOADDR0, 0xB3); /* Radio Register Address Low Byte */
236 SFR(RADIOADDR1, 0xB2); /* Radio Register Address High Byte */
237 SFR16E(RADIOADDR, 0xB2B3); /* Radio Register Address */
238 SFR(RADIODATA0, 0xB7); /* Radio Register Data 0 */
239 SFR(RADIODATA1, 0xB6); /* Radio Register Data 1 */
240 SFR(RADIODATA2, 0xB5); /* Radio Register Data 2 */
241 SFR(RADIODATA3, 0xB4); /* Radio Register Data 3 */
242 SFR32E(RADIODATA, 0xB4B5B6B7); /* Radio Register Data */
243 SFR(RADIOSTAT0, 0xBE); /* Radio Access Status Low Byte */
244 SFR(RADIOSTAT1, 0xBF); /* Radio Access Status High Byte */
245 SFR16(RADIOSTAT, 0xBE); /* Radio Access Status */
246 SFR(SPCLKSRC, 0xDF); /* SPI Clock Source */
247 SFR(SPMODE, 0xDC); /* SPI Mode */
248 SFR(SPSHREG, 0xDE); /* SPI Shift Register */
249 SFR(SPSTATUS, 0xDD); /* SPI Status */
250 SFR(T0CLKSRC, 0x9A); /* Timer 0 Clock Source */
251 SFR(T0CNT0, 0x9C); /* Timer 0 Count Low Byte */
252 SFR(T0CNT1, 0x9D); /* Timer 0 Count High Byte */
253 SFR16(T0CNT, 0x9C); /* Timer 0 Count */
254 SFR(T0MODE, 0x99); /* Timer 0 Mode */
255 SFR(T0PERIOD0, 0x9E); /* Timer 0 Period Low Byte */
256 SFR(T0PERIOD1, 0x9F); /* Timer 0 Period High Byte */
257 SFR16(T0PERIOD, 0x9E); /* Timer 0 Period */
258 SFR(T0STATUS, 0x9B); /* Timer 0 Status */
259 SFR(T1CLKSRC, 0xA2); /* Timer 1 Clock Source */
260 SFR(T1CNT0, 0xA4); /* Timer 1 Count Low Byte */
261 SFR(T1CNT1, 0xA5); /* Timer 1 Count High Byte */
262 SFR16(T1CNT, 0xA4); /* Timer 1 Count */
263 SFR(T1MODE, 0xA1); /* Timer 1 Mode */
264 SFR(T1PERIOD0, 0xA6); /* Timer 1 Period Low Byte */
265 SFR(T1PERIOD1, 0xA7); /* Timer 1 Period High Byte */
266 SFR16(T1PERIOD, 0xA6); /* Timer 1 Period */
267 SFR(T1STATUS, 0xA3); /* Timer 1 Status */
268 SFR(T2CLKSRC, 0xAA); /* Timer 2 Clock Source */
269 SFR(T2CNT0, 0xAC); /* Timer 2 Count Low Byte */
270 SFR(T2CNT1, 0xAD); /* Timer 2 Count High Byte */
271 SFR16(T2CNT, 0xAC); /* Timer 2 Count */
272 SFR(T2MODE, 0xA9); /* Timer 2 Mode */
273 SFR(T2PERIOD0, 0xAE); /* Timer 2 Period Low Byte */
274 SFR(T2PERIOD1, 0xAF); /* Timer 2 Period High Byte */
275 SFR16(T2PERIOD, 0xAE); /* Timer 2 Period */
276 SFR(T2STATUS, 0xAB); /* Timer 2 Status */
277 SFR(U0CTRL, 0xE4); /* UART 0 Control */
278 SFR(U0MODE, 0xE7); /* UART 0 Mode */
279 SFR(U0SHREG, 0xE6); /* UART 0 Shift Register */
280 SFR(U0STATUS, 0xE5); /* UART 0 Status */
281 SFR(U1CTRL, 0xEC); /* UART 1 Control */
282 SFR(U1MODE, 0xEF); /* UART 1 Mode */
283 SFR(U1SHREG, 0xEE); /* UART 1 Shift Register */
284 SFR(U1STATUS, 0xED); /* UART 1 Status */
285 SFR(WDTCFG, 0xDA); /* Watchdog Configuration */
286 SFR(WDTRESET, 0xDB); /* Watchdog Reset */
287 SFR(WTCFGA, 0xF1); /* Wakeup Timer A Configuration */
288 SFR(WTCFGB, 0xF9); /* Wakeup Timer B Configuration */
289 SFR(WTCNTA0, 0xF2); /* Wakeup Counter A Low Byte */
290 SFR(WTCNTA1, 0xF3); /* Wakeup Counter A High Byte */
291 SFR16(WTCNTA, 0xF2); /* Wakeup Counter A */
292 SFR(WTCNTB0, 0xFA); /* Wakeup Counter B Low Byte */
293 SFR(WTCNTB1, 0xFB); /* Wakeup Counter B High Byte */
294 SFR16(WTCNTB, 0xFA); /* Wakeup Counter B */
295 SFR(WTCNTR1, 0xEB); /* Wakeup Counter High Byte Latch */
296 SFR(WTEVTA0, 0xF4); /* Wakeup Event A Low Byte */
297 SFR(WTEVTA1, 0xF5); /* Wakeup Event A High Byte */
298 SFR16(WTEVTA, 0xF4); /* Wakeup Event A */
299 SFR(WTEVTB0, 0xF6); /* Wakeup Event B Low Byte */
300 SFR(WTEVTB1, 0xF7); /* Wakeup Event B High Byte */
301 SFR16(WTEVTB, 0xF6); /* Wakeup Event B */
302 SFR(WTEVTC0, 0xFC); /* Wakeup Event C Low Byte */
303 SFR(WTEVTC1, 0xFD); /* Wakeup Event C High Byte */
304 SFR16(WTEVTC, 0xFC); /* Wakeup Event C */
305 SFR(WTEVTD0, 0xFE); /* Wakeup Event D Low Byte */
306 SFR(WTEVTD1, 0xFF); /* Wakeup Event D High Byte */
307 SFR16(WTEVTD, 0xFE); /* Wakeup Event D */
308 SFR(WTIRQEN, 0xE9); /* Wakeup Timer Interrupt Enable */
309 SFR(WTSTAT, 0xEA); /* Wakeup Timer Status */
310
311 /* X Address Space */
312
313 #define AX8052_RADIOBASE 0x4000
314 #define AX8052_RADIOBASENB 0x5000
315
316 SFRX(ADCCALG00GAIN0, 0x7030); /* ADC Calibration Range 00 Gain Low Byte */
317 SFRX(ADCCALG00GAIN1, 0x7031); /* ADC Calibration Range 00 Gain High Byte */
318 SFR16LEX(ADCCALG00GAIN, 0x7030); /* ADC Calibration Range 00 Gain */
319 SFRX(ADCCALG01GAIN0, 0x7032); /* ADC Calibration Range 01 Gain Low Byte */
320 SFRX(ADCCALG01GAIN1, 0x7033); /* ADC Calibration Range 01 Gain High Byte */
321 SFR16LEX(ADCCALG01GAIN, 0x7032); /* ADC Calibration Range 01 Gain */
322 SFRX(ADCCALG10GAIN0, 0x7034); /* ADC Calibration Range 10 Gain Low Byte */
323 SFRX(ADCCALG10GAIN1, 0x7035); /* ADC Calibration Range 10 Gain High Byte */
324 SFR16LEX(ADCCALG10GAIN, 0x7034); /* ADC Calibration Range 10 Gain */
325 SFRX(ADCCALTEMPGAIN0, 0x7038); /* ADC Calibration Temperature Gain Low Byte */
326 SFRX(ADCCALTEMPGAIN1, 0x7039); /* ADC Calibration Temperature Gain High Byte */
327 SFR16LEX(ADCCALTEMPGAIN, 0x7038); /* ADC Calibration Temperature Gain */
328 SFRX(ADCCALTEMPOFFS0, 0x703A); /* ADC Calibration Temperature Offset Low Byte */
329 SFRX(ADCCALTEMPOFFS1, 0x703B); /* ADC Calibration Temperature Offset High Byte */
330 SFR16LEX(ADCCALTEMPOFFS, 0x703A); /* ADC Calibration Temperature Offset */
331 SFRX(ADCCH0VAL0, 0x7020); /* ADC Channel 0 Low Byte */
332 SFRX(ADCCH0VAL1, 0x7021); /* ADC Channel 0 High Byte */
333 SFR16LEX(ADCCH0VAL, 0x7020); /* ADC Channel 0 */
334 SFRX(ADCCH1VAL0, 0x7022); /* ADC Channel 1 Low Byte */
335 SFRX(ADCCH1VAL1, 0x7023); /* ADC Channel 1 High Byte */
336 SFR16LEX(ADCCH1VAL, 0x7022); /* ADC Channel 1 */
337 SFRX(ADCCH2VAL0, 0x7024); /* ADC Channel 2 Low Byte */
338 SFRX(ADCCH2VAL1, 0x7025); /* ADC Channel 2 High Byte */
339 SFR16LEX(ADCCH2VAL, 0x7024); /* ADC Channel 2 */
340 SFRX(ADCCH3VAL0, 0x7026); /* ADC Channel 3 Low Byte */
341 SFRX(ADCCH3VAL1, 0x7027); /* ADC Channel 3 High Byte */
342 SFR16LEX(ADCCH3VAL, 0x7026); /* ADC Channel 3 */
343 SFRX(ADCTUNE0, 0x7028); /* ADC Tuning 0 */
344 SFRX(ADCTUNE1, 0x7029); /* ADC Tuning 1 */
345 SFRX(ADCTUNE2, 0x702A); /* ADC Tuning 2 */
346 SFRX(AESCONFIG, 0x7091); /* AES Configuration */
347 SFRX(AESCURBLOCK, 0x7098); /* AES Current Block Number */
348 SFRX(AESINADDR0, 0x7094); /* AES Input Address Low Byte */
349 SFRX(AESINADDR1, 0x7095); /* AES Input Address High Byte */
350 SFR16LEX(AESINADDR, 0x7094); /* AES Input Address */
351 SFRX(AESKEYADDR0, 0x7092); /* AES Keystream Address Low Byte */
352 SFRX(AESKEYADDR1, 0x7093); /* AES Keystream Address High Byte */
353 SFR16LEX(AESKEYADDR, 0x7092); /* AES Keystream Address */
354 SFRX(AESMODE, 0x7090); /* AES Mode */
355 SFRX(AESOUTADDR0, 0x7096); /* AES Output Address Low Byte */
356 SFRX(AESOUTADDR1, 0x7097); /* AES Output Address High Byte */
357 SFR16LEX(AESOUTADDR, 0x7096); /* AES Output Address */
358 SFRX(CLOCKGATE, 0x7F1B); /* Clock Gating */
359 SFRX(DMA0ADDR0, 0x7010); /* DMA Channel 0 Address Low Byte */
360 SFRX(DMA0ADDR1, 0x7011); /* DMA Channel 0 Address High Byte */
361 SFR16LEX(DMA0ADDR, 0x7010); /* DMA Channel 0 Address */
362 SFRX(DMA0CONFIG, 0x7014); /* DMA Channel 0 Configuration */
363 SFRX(DMA1ADDR0, 0x7012); /* DMA Channel 1 Address Low Byte */
364 SFRX(DMA1ADDR1, 0x7013); /* DMA Channel 1 Address High Byte */
365 SFR16LEX(DMA1ADDR, 0x7012); /* DMA Channel 1 Address */
366 SFRX(DMA1CONFIG, 0x7015); /* DMA Channel 1 Configuration */
367 SFRX(FRCOSCCONFIG, 0x7070); /* Fast RC Oscillator Calibration Configuration */
368 SFRX(FRCOSCCTRL, 0x7071); /* Fast RC Oscillator Control */
369 SFRX(FRCOSCFREQ0, 0x7076); /* Fast RC Oscillator Frequency Tuning Low Byte */
370 SFRX(FRCOSCFREQ1, 0x7077); /* Fast RC Oscillator Frequency Tuning High Byte */
371 SFR16LEX(FRCOSCFREQ, 0x7076); /* Fast RC Oscillator Frequency Tuning */
372 SFRX(FRCOSCKFILT0, 0x7072); /* Fast RC Oscillator Calibration Filter Constant Low Byte */
373 SFRX(FRCOSCKFILT1, 0x7073); /* Fast RC Oscillator Calibration Filter Constant High Byte */
374 SFR16LEX(FRCOSCKFILT, 0x7072); /* Fast RC Oscillator Calibration Filter Constant */
375 SFRX(FRCOSCPER0, 0x7078); /* Fast RC Oscillator Period Low Byte */
376 SFRX(FRCOSCPER1, 0x7079); /* Fast RC Oscillator Period High Byte */
377 SFR16LEX(FRCOSCPER, 0x7078); /* Fast RC Oscillator Period */
378 SFRX(FRCOSCREF0, 0x7074); /* Fast RC Oscillator Reference Frequency Low Byte */
379 SFRX(FRCOSCREF1, 0x7075); /* Fast RC Oscillator Reference Frequency High Byte */
380 SFR16LEX(FRCOSCREF, 0x7074); /* Fast RC Oscillator Reference Frequency */
381 SFRX(ANALOGA, 0x7007); /* Port A Analog Mode */
382 SFRX(GPIOENABLE, 0x700C); /* GPIO Port Enable */
383 SFRX(EXTIRQ, 0x7003); /* External IRQ Configuration */
384 SFRX(INTCHGA, 0x7000); /* Port A Interrupt on Change */
385 SFRX(INTCHGB, 0x7001); /* Port B Interrupt on Change */
386 SFRX(INTCHGC, 0x7002); /* Port C Interrupt on Change */
387 SFRX(PALTA, 0x7008); /* Port A Alternate Function */
388 SFRX(PALTB, 0x7009); /* Port B Alternate Function */
389 SFRX(PALTC, 0x700A); /* Port C Alternate Function */
390 SFRX(PINCHGA, 0x7004); /* Port A Level Change */
391 SFRX(PINCHGB, 0x7005); /* Port B Level Change */
392 SFRX(PINCHGC, 0x7006); /* Port C Level Change */
393 SFRX(PINSEL, 0x700B); /* Port Input Selection */
394 SFRX(LPOSCCONFIG, 0x7060); /* Low Power Oscillator Calibration Configuration */
395 SFRX(LPOSCFREQ0, 0x7066); /* Low Power Oscillator Frequency Tuning Low Byte */
396 SFRX(LPOSCFREQ1, 0x7067); /* Low Power Oscillator Frequency Tuning High Byte */
397 SFR16LEX(LPOSCFREQ, 0x7066); /* Low Power Oscillator Frequency Tuning */
398 SFRX(LPOSCKFILT0, 0x7062); /* Low Power Oscillator Calibration Filter Constant Low Byte */
399 SFRX(LPOSCKFILT1, 0x7063); /* Low Power Oscillator Calibration Filter Constant High Byte */
400 SFR16LEX(LPOSCKFILT, 0x7062); /* Low Power Oscillator Calibration Filter Constant */
401 SFRX(LPOSCPER0, 0x7068); /* Low Power Oscillator Period Low Byte */
402 SFRX(LPOSCPER1, 0x7069); /* Low Power Oscillator Period High Byte */
403 SFR16LEX(LPOSCPER, 0x7068); /* Low Power Oscillator Period */
404 SFRX(LPOSCREF0, 0x7064); /* Low Power Oscillator Reference Frequency Low Byte */
405 SFRX(LPOSCREF1, 0x7065); /* Low Power Oscillator Reference Frequency High Byte */
406 SFR16LEX(LPOSCREF, 0x7064); /* Low Power Oscillator Reference Frequency */
407 SFRX(LPXOSCGM, 0x7054); /* Low Power Crystal Oscillator Transconductance */
408 SFRX(OSCCALIB, 0x7053); /* Oscillator Calibration Interrupt / Status */
409 SFRX(OSCFORCERUN, 0x7050); /* Oscillator Run Force */
410 SFRX(OSCREADY, 0x7052); /* Oscillator Ready Status */
411 SFRX(OSCRUN, 0x7051); /* Oscillator Run Status */
412 SFRX(POWCTRL0, 0x7F10); /* Power Control 0 */
413 SFRX(POWCTRL1, 0x7F11); /* Power Control 1 */
414 SFRX(POWCTRL2, 0x7F12); /* Power Control 2 */
415 SFRX(RADIOFDATAADDR0, 0x7040); /* Radio FIFO Data Register Address Low Byte */
416 SFRX(RADIOFDATAADDR1, 0x7041); /* Radio FIFO Data Register Address High Byte */
417 SFR16LEX(RADIOFDATAADDR, 0x7040); /* Radio FIFO Data Register Address */
418 SFRX(RADIOFSTATADDR0, 0x7042); /* Radio FIFO Status Register Address Low Byte */
419 SFRX(RADIOFSTATADDR1, 0x7043); /* Radio FIFO Status Register Address High Byte */
420 SFR16LEX(RADIOFSTATADDR, 0x7042); /* Radio FIFO Status Register Address */
421 SFRX(RADIOMUX, 0x7044); /* Radio Multiplexer Control */
422 SFRX(RNGBYTE, 0x7081); /* True Random Byte */
423 SFRX(RNGCLKSRC0, 0x7082); /* True Random Number Generator Clock Source 0 */
424 SFRX(RNGCLKSRC1, 0x7083); /* True Random Number Generator Clock Source 1 */
425 SFRX(RNGMODE, 0x7080); /* True Random Number Generator Mode */
426 SFRX(SCRATCH0, 0x7084); /* Scratch Register 0 */
427 SFRX(SCRATCH1, 0x7085); /* Scratch Register 1 */
428 SFRX(SCRATCH2, 0x7086); /* Scratch Register 2 */
429 SFRX(SCRATCH3, 0x7087); /* Scratch Register 3 */
430 SFRX(SILICONREV, 0x7F00); /* Silicon Revision */
431 SFRX(XTALAMPL, 0x7F19); /* Crystal Oscillator Amplitude Control */
432 SFRX(XTALOSC, 0x7F18); /* Crystal Oscillator Configuration */
433 SFRX(XTALREADY, 0x7F1A); /* Crystal Oscillator Ready Mode */
434
435 /* X Address Space aliases of SFR Address Space Registers */
436
437 SFR16LEX(XDPTR0, 0x3F82); /* Data Pointer 0 */
438 SFR16LEX(XDPTR1, 0x3F84); /* Data Pointer 1 */
439 SFRX(XIE, 0x3FA8); /* Interrupt Enable */
440 SFRX(XIP, 0x3FB8); /* Interrupt Priority */
441 SFRX(XPCON, 0x3F87); /* Power Mode Control */
442 SFRX(XADCCH0CONFIG, 0x3FCA); /* ADC Channel 0 Configuration */
443 SFRX(XADCCH1CONFIG, 0x3FCB); /* ADC Channel 1 Configuration */
444 SFRX(XADCCH2CONFIG, 0x3FD2); /* ADC Channel 2 Configuration */
445 SFRX(XADCCH3CONFIG, 0x3FD3); /* ADC Channel 3 Configuration */
446 SFRX(XADCCLKSRC, 0x3FD1); /* ADC Clock Source */
447 SFRX(XADCCONV, 0x3FC9); /* ADC Conversion Source */
448 SFRX(XANALOGCOMP, 0x3FE1); /* Analog Comparators */
449 SFRX(XCLKCON, 0x3FC6); /* Clock Control */
450 SFRX(XCLKSTAT, 0x3FC7); /* Clock Status */
451 SFRX(XCODECONFIG, 0x3F97); /* Code Space Configuration */
452 SFRX(XDBGLNKBUF, 0x3FE3); /* Debug Link Buffer */
453 SFRX(XDBGLNKSTAT, 0x3FE2); /* Debug Link Status */
454 SFRX(XDIRA, 0x3F89); /* Port A Direction */
455 SFRX(XDIRB, 0x3F8A); /* Port B Direction */
456 SFRX(XDIRC, 0x3F8B); /* Port C Direction */
457 SFRX(XDIRR, 0x3F8E); /* Port R Direction */
458 SFRX(XPINA, 0x3FC8); /* Port A Input */
459 SFRX(XPINB, 0x3FE8); /* Port B Input */
460 SFRX(XPINC, 0x3FF8); /* Port C Input */
461 SFRX(XPINR, 0x3F8D); /* Port R Input */
462 SFRX(XPORTA, 0x3F80); /* Port A Output */
463 SFRX(XPORTB, 0x3F88); /* Port B Output */
464 SFRX(XPORTC, 0x3F90); /* Port C Output */
465 SFRX(XPORTR, 0x3F8C); /* Port R Output */
466 SFRX(XIC0CAPT0, 0x3FCE); /* Input Capture 0 Low Byte */
467 SFRX(XIC0CAPT1, 0x3FCF); /* Input Capture 0 High Byte */
468 SFR16LEX(XIC0CAPT, 0x3FCE); /* Input Capture 0 */
469 SFRX(XIC0MODE, 0x3FCC); /* Input Capture 0 Mode */
470 SFRX(XIC0STATUS, 0x3FCD); /* Input Capture 0 Status */
471 SFRX(XIC1CAPT0, 0x3FD6); /* Input Capture 1 Low Byte */
472 SFRX(XIC1CAPT1, 0x3FD7); /* Input Capture 1 High Byte */
473 SFR16LEX(XIC1CAPT, 0x3FD6); /* Input Capture 1 */
474 SFRX(XIC1MODE, 0x3FD4); /* Input Capture 1 Mode */
475 SFRX(XIC1STATUS, 0x3FD5); /* Input Capture 1 Status */
476 SFRX(XNVADDR0, 0x3F92); /* Non-Volatile Memory Address Low Byte */
477 SFRX(XNVADDR1, 0x3F93); /* Non-Volatile Memory Address High Byte */
478 SFR16LEX(XNVADDR, 0x3F92); /* Non-Volatile Memory Address */
479 SFRX(XNVDATA0, 0x3F94); /* Non-Volatile Memory Data Low Byte */
480 SFRX(XNVDATA1, 0x3F95); /* Non-Volatile Memory Data High Byte */
481 SFR16LEX(XNVDATA, 0x3F94); /* Non-Volatile Memory Data */
482 SFRX(XNVKEY, 0x3F96); /* Non-Volatile Memory Write/Erase Key */
483 SFRX(XNVSTATUS, 0x3F91); /* Non-Volatile Memory Command / Status */
484 SFRX(XOC0COMP0, 0x3FBC); /* Output Compare 0 Low Byte */
485 SFRX(XOC0COMP1, 0x3FBD); /* Output Compare 0 High Byte */
486 SFR16LEX(XOC0COMP, 0x3FBC); /* Output Compare 0 */
487 SFRX(XOC0MODE, 0x3FB9); /* Output Compare 0 Mode */
488 SFRX(XOC0PIN, 0x3FBA); /* Output Compare 0 Pin Configuration */
489 SFRX(XOC0STATUS, 0x3FBB); /* Output Compare 0 Status */
490 SFRX(XOC1COMP0, 0x3FC4); /* Output Compare 1 Low Byte */
491 SFRX(XOC1COMP1, 0x3FC5); /* Output Compare 1 High Byte */
492 SFR16LEX(XOC1COMP, 0x3FC4); /* Output Compare 1 */
493 SFRX(XOC1MODE, 0x3FC1); /* Output Compare 1 Mode */
494 SFRX(XOC1PIN, 0x3FC2); /* Output Compare 1 Pin Configuration */
495 SFRX(XOC1STATUS, 0x3FC3); /* Output Compare 1 Status */
496 SFRX(XRADIOACC, 0x3FB1); /* Radio Controller Access Mode */
497 SFRX(XRADIOADDR0, 0x3FB3); /* Radio Register Address Low Byte */
498 SFRX(XRADIOADDR1, 0x3FB2); /* Radio Register Address High Byte */
499 SFRX(XRADIODATA0, 0x3FB7); /* Radio Register Data 0 */
500 SFRX(XRADIODATA1, 0x3FB6); /* Radio Register Data 1 */
501 SFRX(XRADIODATA2, 0x3FB5); /* Radio Register Data 2 */
502 SFRX(XRADIODATA3, 0x3FB4); /* Radio Register Data 3 */
503 SFRX(XRADIOSTAT0, 0x3FBE); /* Radio Access Status Low Byte */
504 SFRX(XRADIOSTAT1, 0x3FBF); /* Radio Access Status High Byte */
505 SFR16LEX(XRADIOSTAT, 0x3FBE); /* Radio Access Status */
506 SFRX(XSPCLKSRC, 0x3FDF); /* SPI Clock Source */
507 SFRX(XSPMODE, 0x3FDC); /* SPI Mode */
508 SFRX(XSPSHREG, 0x3FDE); /* SPI Shift Register */
509 SFRX(XSPSTATUS, 0x3FDD); /* SPI Status */
510 SFRX(XT0CLKSRC, 0x3F9A); /* Timer 0 Clock Source */
511 SFRX(XT0CNT0, 0x3F9C); /* Timer 0 Count Low Byte */
512 SFRX(XT0CNT1, 0x3F9D); /* Timer 0 Count High Byte */
513 SFR16LEX(XT0CNT, 0x3F9C); /* Timer 0 Count */
514 SFRX(XT0MODE, 0x3F99); /* Timer 0 Mode */
515 SFRX(XT0PERIOD0, 0x3F9E); /* Timer 0 Period Low Byte */
516 SFRX(XT0PERIOD1, 0x3F9F); /* Timer 0 Period High Byte */
517 SFR16LEX(XT0PERIOD, 0x3F9E); /* Timer 0 Period */
518 SFRX(XT0STATUS, 0x3F9B); /* Timer 0 Status */
519 SFRX(XT1CLKSRC, 0x3FA2); /* Timer 1 Clock Source */
520 SFRX(XT1CNT0, 0x3FA4); /* Timer 1 Count Low Byte */
521 SFRX(XT1CNT1, 0x3FA5); /* Timer 1 Count High Byte */
522 SFR16LEX(XT1CNT, 0x3FA4); /* Timer 1 Count */
523 SFRX(XT1MODE, 0x3FA1); /* Timer 1 Mode */
524 SFRX(XT1PERIOD0, 0x3FA6); /* Timer 1 Period Low Byte */
525 SFRX(XT1PERIOD1, 0x3FA7); /* Timer 1 Period High Byte */
526 SFR16LEX(XT1PERIOD, 0x3FA6); /* Timer 1 Period */
527 SFRX(XT1STATUS, 0x3FA3); /* Timer 1 Status */
528 SFRX(XT2CLKSRC, 0x3FAA); /* Timer 2 Clock Source */
529 SFRX(XT2CNT0, 0x3FAC); /* Timer 2 Count Low Byte */
530 SFRX(XT2CNT1, 0x3FAD); /* Timer 2 Count High Byte */
531 SFR16LEX(XT2CNT, 0x3FAC); /* Timer 2 Count */
532 SFRX(XT2MODE, 0x3FA9); /* Timer 2 Mode */
533 SFRX(XT2PERIOD0, 0x3FAE); /* Timer 2 Period Low Byte */
534 SFRX(XT2PERIOD1, 0x3FAF); /* Timer 2 Period High Byte */
535 SFR16LEX(XT2PERIOD, 0x3FAE); /* Timer 2 Period */
536 SFRX(XT2STATUS, 0x3FAB); /* Timer 2 Status */
537 SFRX(XU0CTRL, 0x3FE4); /* UART 0 Control */
538 SFRX(XU0MODE, 0x3FE7); /* UART 0 Mode */
539 SFRX(XU0SHREG, 0x3FE6); /* UART 0 Shift Register */
540 SFRX(XU0STATUS, 0x3FE5); /* UART 0 Status */
541 SFRX(XU1CTRL, 0x3FEC); /* UART 1 Control */
542 SFRX(XU1MODE, 0x3FEF); /* UART 1 Mode */
543 SFRX(XU1SHREG, 0x3FEE); /* UART 1 Shift Register */
544 SFRX(XU1STATUS, 0x3FED); /* UART 1 Status */
545 SFRX(XWDTCFG, 0x3FDA); /* Watchdog Configuration */
546 SFRX(XWDTRESET, 0x3FDB); /* Watchdog Reset */
547 SFRX(XWTCFGA, 0x3FF1); /* Wakeup Timer A Configuration */
548 SFRX(XWTCFGB, 0x3FF9); /* Wakeup Timer B Configuration */
549 SFRX(XWTCNTA0, 0x3FF2); /* Wakeup Counter A Low Byte */
550 SFRX(XWTCNTA1, 0x3FF3); /* Wakeup Counter A High Byte */
551 SFR16LEX(XWTCNTA, 0x3FF2); /* Wakeup Counter A */
552 SFRX(XWTCNTB0, 0x3FFA); /* Wakeup Counter B Low Byte */
553 SFRX(XWTCNTB1, 0x3FFB); /* Wakeup Counter B High Byte */
554 SFR16LEX(XWTCNTB, 0x3FFA); /* Wakeup Counter B */
555 SFRX(XWTCNTR1, 0x3FEB); /* Wakeup Counter High Byte Latch */
556 SFRX(XWTEVTA0, 0x3FF4); /* Wakeup Event A Low Byte */
557 SFRX(XWTEVTA1, 0x3FF5); /* Wakeup Event A High Byte */
558 SFR16LEX(XWTEVTA, 0x3FF4); /* Wakeup Event A */
559 SFRX(XWTEVTB0, 0x3FF6); /* Wakeup Event B Low Byte */
560 SFRX(XWTEVTB1, 0x3FF7); /* Wakeup Event B High Byte */
561 SFR16LEX(XWTEVTB, 0x3FF6); /* Wakeup Event B */
562 SFRX(XWTEVTC0, 0x3FFC); /* Wakeup Event C Low Byte */
563 SFRX(XWTEVTC1, 0x3FFD); /* Wakeup Event C High Byte */
564 SFR16LEX(XWTEVTC, 0x3FFC); /* Wakeup Event C */
565 SFRX(XWTEVTD0, 0x3FFE); /* Wakeup Event D Low Byte */
566 SFRX(XWTEVTD1, 0x3FFF); /* Wakeup Event D High Byte */
567 SFR16LEX(XWTEVTD, 0x3FFE); /* Wakeup Event D */
568 SFRX(XWTIRQEN, 0x3FE9); /* Wakeup Timer Interrupt Enable */
569 SFRX(XWTSTAT, 0x3FEA); /* Wakeup Timer Status */
570
571
572 /* Radio Registers, X Address Space */
573
574 SFRX(AX5042_ADCMISC, 0x4038); /* ADC Miscellaneous Control */
575 SFRX(AX5042_AGCATTACK, 0x403A); /* AGC Attack Speed */
576 SFRX(AX5042_AGCCOUNTER, 0x403C); /* AGC Counter */
577 SFRX(AX5042_AGCDECAY, 0x403B); /* AGC Decay Speed */
578 SFRX(AX5042_AGCTARGET, 0x4039); /* AGC Target Value */
579 SFRX(AX5042_AMPLITUDEGAIN, 0x4047); /* Amplitude Estimator Bandwidth */
580 SFRX(AX5042_APEOVERRIDE, 0x4070); /* APE Override */
581 SFRX(AX5042_CICDECHI, 0x403E); /* Decimation Factor High */
582 SFRX(AX5042_CICDECLO, 0x403F); /* Decimation Factor Low */
583 SFRX(AX5042_CICSHIFT, 0x403D); /* Decimation Filter Attenuation */
584 SFRX(AX5042_CRCINIT0, 0x4017); /* CRC Initial Value 0 */
585 SFRX(AX5042_CRCINIT1, 0x4016); /* CRC Initial Value 1 */
586 SFRX(AX5042_CRCINIT2, 0x4015); /* CRC Initial Value 2 */
587 SFRX(AX5042_CRCINIT3, 0x4014); /* CRC Initial Value 3 */
588 SFRX(AX5042_DATARATEHI, 0x4040); /* Datarate High */
589 SFRX(AX5042_DATARATELO, 0x4041); /* Datarate Low */
590 SFRX(AX5042_DSPMODE, 0x4009); /* DSP Mode Interface Control */
591 SFRX(AX5042_ENCODING, 0x4011); /* Encoding */
592 SFRX(AX5042_FEC, 0x4018); /* Forward Error Correction */
593 SFRX(AX5042_FECSTATUS, 0x401A); /* Forward Error Correction Status */
594 SFRX(AX5042_FECSYNC, 0x4019); /* Forward Error Correction Sync Threshold */
595 SFRX(AX5042_FIFOCONTROL, 0x4004); /* FIFO Control */
596 SFRX(AX5042_FIFODATA, 0x4005); /* FIFO Data */
597 SFRX(AX5042_FRAMING, 0x4012); /* Framing Mode */
598 SFRX(AX5042_FREQ0, 0x4023); /* Frequency 0 */
599 SFRX(AX5042_FREQ1, 0x4022); /* Frequency 1 */
600 SFRX(AX5042_FREQ2, 0x4021); /* Frequency 2 */
601 SFRX(AX5042_FREQ3, 0x4020); /* Frequency 3 */
602 SFRX(AX5042_FREQUENCYGAIN, 0x4045); /* Frequency Estimator Bandwidth */
603 SFRX(AX5042_FREQUENCYGAIN2, 0x4046); /* Frequency Estimator Bandwidth 2 */
604 SFRX(AX5042_FSKDEV0, 0x4027); /* FSK Deviation 0 */
605 SFRX(AX5042_FSKDEV1, 0x4026); /* FSK Deviation 1 */
606 SFRX(AX5042_FSKDEV2, 0x4025); /* FSK Deviation 2 */
607 SFRX(AX5042_IFFREQHI, 0x4028); /* IF Frequency Low */
608 SFRX(AX5042_IFFREQLO, 0x4029); /* IF Frequency High */
609 SFRX(AX5042_IFMODE, 0x4008); /* Interface Mode */
610 SFRX(AX5042_IRQINVERSION, 0x400F); /* IRQ Inversion */
611 SFRX(AX5042_IRQMASK, 0x4006); /* IRQ Mask */
612 SFRX(AX5042_IRQREQUEST, 0x4007); /* IRQ Request */
613 SFRX(AX5042_MODULATION, 0x4010); /* Modulation */
614 SFRX(AX5042_MODULATORMISC, 0x4034); /* Modulator Miscellaneous Control */
615 SFRX(AX5042_PHASEGAIN, 0x4044); /* Phase Estimator Bandwidth */
616 SFRX(AX5042_PINCFG1, 0x400C); /* Pin Configuration 1 */
617 SFRX(AX5042_PINCFG2, 0x400D); /* Pin Configuration 2 */
618 SFRX(AX5042_PINCFG3, 0x400E); /* Pin Configuration 3 */
619 SFRX(AX5042_PLLLOOP, 0x402C); /* PLL Loop Filter */
620 SFRX(AX5042_PLLRANGING, 0x402D); /* PLL Autoranging Control */
621 SFRX(AX5042_PLLRNGCLK, 0x402E); /* PLL Autoranging Clock */
622 SFRX(AX5042_PLLRNGMISC, 0x4074); /* PLL Autoranging Miscellaneous */
623 SFRX(AX5042_PLLVCOI, 0x4072); /* PLL VCO Current */
624 SFRX(AX5042_PWRMODE, 0x4002); /* Power Mode */
625 SFRX(AX5042_REF, 0x407C); /* Reference */
626 SFRX(AX5042_RXMISC, 0x407D); /* Receiver Miscellaneous Control */
627 SFRX(AX5042_SCRATCH, 0x4001); /* Scratch */
628 SFRX(AX5042_SILICONREVISION, 0x4000); /* Silicon Revision */
629 SFRX(AX5042_TIMINGGAINHI, 0x4042); /* Timing Estimator Bandwidth High */
630 SFRX(AX5042_TIMINGGAINLO, 0x4043); /* Timing Estimator Bandwidth Low */
631 SFRX(AX5042_TRKAMPLITUDEHI, 0x4048); /* Amplitude Tracking High */
632 SFRX(AX5042_TRKAMPLITUDELO, 0x4049); /* Amplitude Tracking Low */
633 SFRX(AX5042_TRKFREQHI, 0x404C); /* Frequency Tracking High */
634 SFRX(AX5042_TRKFREQLO, 0x404D); /* Frequency Tracking Low */
635 SFRX(AX5042_TRKPHASEHI, 0x404A); /* Phase Tracking High */
636 SFRX(AX5042_TRKPHASELO, 0x404B); /* Phase Tracking Low */
637 SFRX(AX5042_TXBITRATEHI, 0x4031); /* Transmitter Bitrate High */
638 SFRX(AX5042_TXBITRATELO, 0x4033); /* Transmitter Bitrate Low */
639 SFRX(AX5042_TXBITRATEMID, 0x4032); /* Transmitter Bitrate Middle */
640 SFRX(AX5042_TXDSPMODE, 0x400A); /* Transmit DSP Mode */
641 SFRX(AX5042_TXPWR, 0x4030); /* Transmit Power */
642 SFRX(AX5042_XTALOSC, 0x4003); /* Crystal Oscillator Control */
643
644 /* Radio Registers, X Address Space, Non-Blocking Version */
645
646 SFRX(AX5042_ADCMISCNB, 0x5038); /* ADC Miscellaneous Control, Non-Blocking */
647 SFRX(AX5042_AGCATTACKNB, 0x503A); /* AGC Attack Speed, Non-Blocking */
648 SFRX(AX5042_AGCCOUNTERNB, 0x503C); /* AGC Counter, Non-Blocking */
649 SFRX(AX5042_AGCDECAYNB, 0x503B); /* AGC Decay Speed, Non-Blocking */
650 SFRX(AX5042_AGCTARGETNB, 0x5039); /* AGC Target Value, Non-Blocking */
651 SFRX(AX5042_AMPLITUDEGAINNB, 0x5047); /* Amplitude Estimator Bandwidth, Non-Blocking */
652 SFRX(AX5042_APEOVERRIDENB, 0x5070); /* APE Override, Non-Blocking */
653 SFRX(AX5042_CICDECHINB, 0x503E); /* Decimation Factor High, Non-Blocking */
654 SFRX(AX5042_CICDECLONB, 0x503F); /* Decimation Factor Low, Non-Blocking */
655 SFRX(AX5042_CICSHIFTNB, 0x503D); /* Decimation Filter Attenuation, Non-Blocking */
656 SFRX(AX5042_CRCINIT0NB, 0x5017); /* CRC Initial Value 0, Non-Blocking */
657 SFRX(AX5042_CRCINIT1NB, 0x5016); /* CRC Initial Value 1, Non-Blocking */
658 SFRX(AX5042_CRCINIT2NB, 0x5015); /* CRC Initial Value 2, Non-Blocking */
659 SFRX(AX5042_CRCINIT3NB, 0x5014); /* CRC Initial Value 3, Non-Blocking */
660 SFRX(AX5042_DATARATEHINB, 0x5040); /* Datarate High, Non-Blocking */
661 SFRX(AX5042_DATARATELONB, 0x5041); /* Datarate Low, Non-Blocking */
662 SFRX(AX5042_DSPMODENB, 0x5009); /* DSP Mode Interface Control, Non-Blocking */
663 SFRX(AX5042_ENCODINGNB, 0x5011); /* Encoding, Non-Blocking */
664 SFRX(AX5042_FECNB, 0x5018); /* Forward Error Correction, Non-Blocking */
665 SFRX(AX5042_FECSTATUSNB, 0x501A); /* Forward Error Correction Status, Non-Blocking */
666 SFRX(AX5042_FECSYNCNB, 0x5019); /* Forward Error Correction Sync Threshold, Non-Blocking */
667 SFRX(AX5042_FIFOCONTROLNB, 0x5004); /* FIFO Control, Non-Blocking */
668 SFRX(AX5042_FIFODATANB, 0x5005); /* FIFO Data, Non-Blocking */
669 SFRX(AX5042_FRAMINGNB, 0x5012); /* Framing Mode, Non-Blocking */
670 SFRX(AX5042_FREQ0NB, 0x5023); /* Frequency 0, Non-Blocking */
671 SFRX(AX5042_FREQ1NB, 0x5022); /* Frequency 1, Non-Blocking */
672 SFRX(AX5042_FREQ2NB, 0x5021); /* Frequency 2, Non-Blocking */
673 SFRX(AX5042_FREQ3NB, 0x5020); /* Frequency 3, Non-Blocking */
674 SFRX(AX5042_FREQUENCYGAINNB, 0x5045); /* Frequency Estimator Bandwidth, Non-Blocking */
675 SFRX(AX5042_FREQUENCYGAIN2NB, 0x5046); /* Frequency Estimator Bandwidth 2, Non-Blocking */
676 SFRX(AX5042_FSKDEV0NB, 0x5027); /* FSK Deviation 0, Non-Blocking */
677 SFRX(AX5042_FSKDEV1NB, 0x5026); /* FSK Deviation 1, Non-Blocking */
678 SFRX(AX5042_FSKDEV2NB, 0x5025); /* FSK Deviation 2, Non-Blocking */
679 SFRX(AX5042_IFFREQHINB, 0x5028); /* IF Frequency Low, Non-Blocking */
680 SFRX(AX5042_IFFREQLONB, 0x5029); /* IF Frequency High, Non-Blocking */
681 SFRX(AX5042_IFMODENB, 0x5008); /* Interface Mode, Non-Blocking */
682 SFRX(AX5042_IRQINVERSIONNB, 0x500F); /* IRQ Inversion, Non-Blocking */
683 SFRX(AX5042_IRQMASKNB, 0x5006); /* IRQ Mask, Non-Blocking */
684 SFRX(AX5042_IRQREQUESTNB, 0x5007); /* IRQ Request, Non-Blocking */
685 SFRX(AX5042_MODULATIONNB, 0x5010); /* Modulation, Non-Blocking */
686 SFRX(AX5042_MODULATORMISCNB, 0x5034); /* Modulator Miscellaneous Control, Non-Blocking */
687 SFRX(AX5042_PHASEGAINNB, 0x5044); /* Phase Estimator Bandwidth, Non-Blocking */
688 SFRX(AX5042_PINCFG1NB, 0x500C); /* Pin Configuration 1, Non-Blocking */
689 SFRX(AX5042_PINCFG2NB, 0x500D); /* Pin Configuration 2, Non-Blocking */
690 SFRX(AX5042_PINCFG3NB, 0x500E); /* Pin Configuration 3, Non-Blocking */
691 SFRX(AX5042_PLLLOOPNB, 0x502C); /* PLL Loop Filter, Non-Blocking */
692 SFRX(AX5042_PLLRANGINGNB, 0x502D); /* PLL Autoranging Control, Non-Blocking */
693 SFRX(AX5042_PLLRNGCLKNB, 0x502E); /* PLL Autoranging Clock, Non-Blocking */
694 SFRX(AX5042_PLLRNGMISCNB, 0x5074); /* PLL Autoranging Miscellaneous, Non-Blocking */
695 SFRX(AX5042_PLLVCOINB, 0x5072); /* PLL VCO Current, Non-Blocking */
696 SFRX(AX5042_PWRMODENB, 0x5002); /* Power Mode, Non-Blocking */
697 SFRX(AX5042_REFNB, 0x507C); /* Reference, Non-Blocking */
698 SFRX(AX5042_RXMISCNB, 0x507D); /* Receiver Miscellaneous Control, Non-Blocking */
699 SFRX(AX5042_SCRATCHNB, 0x5001); /* Scratch, Non-Blocking */
700 SFRX(AX5042_SILICONREVISIONNB, 0x5000); /* Silicon Revision, Non-Blocking */
701 SFRX(AX5042_TIMINGGAINHINB, 0x5042); /* Timing Estimator Bandwidth High, Non-Blocking */
702 SFRX(AX5042_TIMINGGAINLONB, 0x5043); /* Timing Estimator Bandwidth Low, Non-Blocking */
703 SFRX(AX5042_TRKAMPLITUDEHINB, 0x5048); /* Amplitude Tracking High, Non-Blocking */
704 SFRX(AX5042_TRKAMPLITUDELONB, 0x5049); /* Amplitude Tracking Low, Non-Blocking */
705 SFRX(AX5042_TRKFREQHINB, 0x504C); /* Frequency Tracking High, Non-Blocking */
706 SFRX(AX5042_TRKFREQLONB, 0x504D); /* Frequency Tracking Low, Non-Blocking */
707 SFRX(AX5042_TRKPHASEHINB, 0x504A); /* Phase Tracking High, Non-Blocking */
708 SFRX(AX5042_TRKPHASELONB, 0x504B); /* Phase Tracking Low, Non-Blocking */
709 SFRX(AX5042_TXBITRATEHINB, 0x5031); /* Transmitter Bitrate High, Non-Blocking */
710 SFRX(AX5042_TXBITRATELONB, 0x5033); /* Transmitter Bitrate Low, Non-Blocking */
711 SFRX(AX5042_TXBITRATEMIDNB, 0x5032); /* Transmitter Bitrate Middle, Non-Blocking */
712 SFRX(AX5042_TXDSPMODENB, 0x500A); /* Transmit DSP Mode, Non-Blocking */
713 SFRX(AX5042_TXPWRNB, 0x5030); /* Transmit Power, Non-Blocking */
714 SFRX(AX5042_XTALOSCNB, 0x5003); /* Crystal Oscillator Control, Non-Blocking */
715
716 /* Interrupt Numbers */
717
718 #define INT_EXTERNAL0 0
719 #define INT_WAKEUPTIMER 1
720 #define INT_EXTERNAL1 2
721 #define INT_GPIO 3
722 #define INT_RADIO 4
723 #define INT_CLOCKMGMT 5
724 #define INT_POWERMGMT 6
725 #define INT_TIMER0 7
726 #define INT_TIMER1 8
727 #define INT_TIMER2 9
728 #define INT_SPI0 10
729 #define INT_UART0 11
730 #define INT_UART1 12
731 #define INT_GPADC 13
732 #define INT_DMA 14
733 #define INT_OUTPUTCOMP0 15
734 #define INT_OUTPUTCOMP1 16
735 #define INT_INPUTCAPT0 17
736 #define INT_INPUTCAPT1 18
737 #define INT_RNG 19
738 #define INT_AES 20
739 #define INT_DEBUGLINK 21
740
741 /* DMA Sources */
742
743 #define DMASOURCE_XRAMTOOTHER 0x00
744 #define DMASOURCE_SPITX 0x01
745 #define DMASOURCE_UART0TX 0x02
746 #define DMASOURCE_UART1TX 0x03
747 #define DMASOURCE_TIMER0 0x04
748 #define DMASOURCE_TIMER1 0x05
749 #define DMASOURCE_TIMER2 0x06
750 #define DMASOURCE_RADIOTX 0x07
751 #define DMASOURCE_OC0 0x08
752 #define DMASOURCE_OC1 0x09
753 #define DMASOURCE_OTHERTOXRAM 0x10
754 #define DMASOURCE_SPIRX 0x11
755 #define DMASOURCE_UART0RX 0x12
756 #define DMASOURCE_UART1RX 0x13
757 #define DMASOURCE_ADC 0x14
758 #define DMASOURCE_RADIORX 0x17
759 #define DMASOURCE_IC0 0x18
760 #define DMASOURCE_IC1 0x19
761
762
763 #endif /* AX8052F142_H */
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