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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / cc1110.h
blob02ccf9a1e58144e1b7a77e35898db28541158cad
1 /*-------------------------------------------------------------------------
2 Register Declarations for Chipcon CC1110
3
4 Written By - Pravin Angolkar (February 2008)
5 (Based on CC1110 PRELIMINARY Data Sheet (rev. F) )
6
7 This library is free software; you can redistribute it and/or
8 modify it under the terms of the GNU Lesser General Public
9 License as published by the Free Software Foundation; either
10 version 2.1 of the License, or (at your option) any later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 Lesser General Public License for more details.
16
17 You should have received a copy of the GNU Lesser General Public
18 License along with this library; if not, write to the Free Software
19 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20
21 In other words, you are welcome to use, share and improve this program.
22 You are forbidden to forbid anyone else to use, share and improve
23 what you give them. Help stamp out software-hoarding!
24 -------------------------------------------------------------------------*/
25
26 #ifndef REG_CC1110_H
27 #define REG_CC1110_H
28
29 #include<compiler.h>
30 /* ------------------------------------------------------------------------------------------------
31 * Interrupt Vectors
32 * ------------------------------------------------------------------------------------------------
33 */
34 #define RFTXRX_VECTOR 0 /* RF TX done / RX ready */
35 #define ADC_VECTOR 1 /* ADC End of Conversion */
36 #define URX0_VECTOR 2 /* USART0 RX Complete */
37 #define URX1_VECTOR 3 /* USART1 RX Complete */
38 #define ENC_VECTOR 4 /* AES Encryption/Decryption Complete */
39 #define ST_VECTOR 5 /* Sleep Timer Compare */
40 #define P2INT_VECTOR 6 /* Port 2 Inputs */
41 #define UTX0_VECTOR 7 /* USART0 TX Complete */
42 #define DMA_VECTOR 8 /* DMA Transfer Complete */
43 #define T1_VECTOR 9 /* Timer 1 (16-bit) Capture/Compare/Overflow */
44 #define T2_VECTOR 10 /* Timer 2 (MAC Timer) Overflow */
45 #define T3_VECTOR 11 /* Timer 3 (8-bit) Capture/Compare/Overflow */
46 #define T4_VECTOR 12 /* Timer 4 (8-bit) Capture/Compare/Overflow */
47 #define P0INT_VECTOR 13 /* Port 0 Inputs */
48 #define UTX1_VECTOR 14 /* USART1 TX Complete */
49 #define P1INT_VECTOR 15 /* Port 1 Inputs */
50 #define RF_VECTOR 16 /* RF General Interrupts */
51 #define WDT_VECTOR 17 /* Watchdog Overflow in Timer Mode */
52
53 SFR(P0, 0x80); // Port 0
54 SBIT(P0_0, 0x80, 0); // Port 0 bit 0
55 SBIT(P0_1, 0x80, 1); // Port 0 bit 1
56 SBIT(P0_2, 0x80, 2); // Port 0 bit 2
57 SBIT(P0_3, 0x80, 3); // Port 0 bit 3
58 SBIT(P0_4, 0x80, 4); // Port 0 bit 4
59 SBIT(P0_5, 0x80, 5); // Port 0 bit 5
60 SBIT(P0_6, 0x80, 6); // Port 0 bit 6
61 SBIT(P0_7, 0x80, 7); // Port 0 bit 7
62
63 SFR(SP, 0x81); // Stack Pointer
64 SFR(DPL0, 0x82); // Data Pointer 0 Low Byte
65 SFR(DPH0, 0x83); // Data Pointer 0 High Byte
66 SFR(DPL1, 0x84); // Data Pointer 1 Low Byte
67 SFR(DPH1, 0x85); // Data Pointer 1 High Byte
68 SFR(U0CSR, 0x86); // USART 0 Control and Status
69 SFR(PCON, 0x87); // Power Mode Control
70
71 SFR(TCON, 0x88); // Interrupt Flags
72 SBIT(IT0, 0x88, 0); // reserved (must always be set to 1)
73 SBIT(RFTXRXIF, 0x88, 1); // RFERR - RF TX/RX FIFO interrupt flag
74 SBIT(IT1, 0x88, 2); // reserved (must always be set to 1)
75 SBIT(URX0IF, 0x88, 3); // USART0 RX Interrupt Flag
76 SBIT(ADCIF, 0x88, 5); // ADC Interrupt Flag
77 SBIT(URX1IF, 0x88, 7); // USART1 RX Interrupt Flag
78
79 SFR(P0IFG, 0x89); // Port 0 Interrupt Status Flag
80 SFR(P1IFG, 0x8A); // Port 1 Interrupt Status Flag
81 SFR(P2IFG, 0x8B); // Port 2 Interrupt Status Flag
82 SFR(PICTL, 0x8C); // Port Interrupt Control
83 SFR(P1IEN, 0x8D); // Port 1 Interrupt Mask
84 SFR(_SFR8E, 0x8E); // not used
85 SFR(P0INP, 0x8F); // Port 0 Input Mode
86
87 SFR(P1, 0x90); // Port 1
88 SBIT(P1_0, 0x90, 0); // Port 1 bit 0
89 SBIT(P1_1, 0x90, 1); // Port 1 bit 1
90 SBIT(P1_2, 0x90, 2); // Port 1 bit 2
91 SBIT(P1_3, 0x90, 3); // Port 1 bit 3
92 SBIT(P1_4, 0x90, 4); // Port 1 bit 4
93 SBIT(P1_5, 0x90, 5); // Port 1 bit 5
94 SBIT(P1_6, 0x90, 6); // Port 1 bit 6
95 SBIT(P1_7, 0x90, 7); // Port 1 bit 7
96
97 SFR(RFIM, 0x91); // RF Interrupt Mask
98 SFR(DPS, 0x92); // Data Pointer Select
99 SFR(MPAGE, 0x93); // Memory Page Select
100 SFR(_XPAGE, 0x93); // Memory Page Select under the name SDCC needs it
101 SFR(_SFR94, 0x94); // not used
102 SFR(_SFR95, 0x95); // not used
103 SFR(_SFR96, 0x96); // not used
104 SFR(_SFR97, 0x97); // not used
105
106 SFR(S0CON, 0x98); // Interrupt Flags 2
107 SBIT(ENCIF_0, 0x98, 0); // AES Interrupt Flag 0
108 SBIT(ENCIF_1, 0x98, 1); // AES Interrupt Flag 1
109
110 SFR(_SFR99, 0x99); // not used
111 SFR(IEN2, 0x9A); // Interrupt Enable 2
112 SFR(S1CON, 0x9B); // CPU Interrupt Flag 3
113 SFR(T2CT, 0x9C); // Timer 2 Count
114 SFR(T2PR, 0x9D); // Timer 2 Prescaler
115 SFR(T2CTL, 0x9E); // Timer 2 Control
116 SFR(_SFR9F, 0x9F); // not used
117
118 SFR(P2, 0xA0); // Port 2
119 SBIT(P2_0, 0xA0, 0); // Port 2 bit 0
120 SBIT(P2_1, 0xA0, 1); // Port 2 bit 1
121 SBIT(P2_2, 0xA0, 2); // Port 2 bit 2
122 SBIT(P2_3, 0xA0, 3); // Port 2 bit 3
123 SBIT(P2_4, 0xA0, 4); // Port 2 bit 4
124 SBIT(P2_5, 0xA0, 5); // Port 2 bit 5
125 SBIT(P2_6, 0xA0, 6); // Port 2 bit 6
126 SBIT(P2_7, 0xA0, 7); // Port 2 bit 7
127
128 SFR(WORIRQ, 0xA1); // Sleep Timer Interrupt Control
129 SFR(WORCTRL, 0xA2); // Sleep Timer Control
130 SFR(WOREVT0, 0xA3); // Sleep Timer Event0 Timeout Low
131 SFR(WOREVT1, 0xA4); // Sleep Timer Event0 Timeout High
132 SFR(WORTIME0, 0xA5); // Sleep Timer Low Byte
133 SFR(WORTIME1, 0xA6); // Sleep Timer High Byte
134 SFR(_SFRA7, 0xA7); // not used
135
136 SFR(IEN0, 0xA8); // Interrupt Enable 0
137 SBIT(RFTXRXIE, 0xA8, 0); // RF TX/RX FIFO interrupt enable
138 SBIT(ADCIE, 0xA8, 1); // ADC Interrupt Enable
139 SBIT(URX0IE, 0xA8, 2); // USART0 RX Interrupt Enable
140 SBIT(URX1IE, 0xA8, 3); // USART1 RX Interrupt Enable
141 SBIT(ENCIE, 0xA8, 4); // AES Encryption/Decryption Interrupt Enable
142 SBIT(STIE, 0xA8, 5); // Sleep Timer Interrupt Enable
143 SBIT(EA, 0xA8, 7); // Global Interrupt Enable
144
145 SFR(IP0, 0xA9); // Interrupt Priority 0
146 SFR(_SFRAA, 0xAA); // not used
147 SFR(FWT, 0xAB); // Flash Write Timing
148 SFR(FADDRL, 0xAC); // Flash Address Low Byte
149 SFR(FADDRH, 0xAD); // Flash Address High Byte
150 SFR(FCTL, 0xAE); // Flash Control
151 SFR(FWDATA, 0xAF); // Flash Write Data
152
153 SFR(_SFRB0, 0xB0); // not used
154 SFR(ENCDI, 0xB1); // Encryption Input Data
155 SFR(ENCDO, 0xB2); // Encryption Output Data
156 SFR(ENCCS, 0xB3); // Encryption Control and Status
157 SFR(ADCCON1, 0xB4); // ADC Control 1
158 SFR(ADCCON2, 0xB5); // ADC Control 2
159 SFR(ADCCON3, 0xB6); // ADC Control 3
160 SFR(_SFRB7, 0xB7); // not used
161
162 SFR(IEN1, 0xB8); // Interrupt Enable 1
163 SBIT(DMAIE, 0xB8, 0); // DMA Transfer Interrupt Enable
164 SBIT(T1IE, 0xB8, 1); // Timer 1 Interrupt Enable
165 SBIT(T2IE, 0xB8, 2); // Timer 2 Interrupt Enable
166 SBIT(T3IE, 0xB8, 3); // Timer 3 Interrupt Enable
167 SBIT(T4IE, 0xB8, 4); // Timer 4 Interrupt Enable
168 SBIT(P0IE, 0xB8, 5); // Port 0 Interrupt Enable
169
170 SFR(IP1, 0xB9); // Interrupt Priority 1
171 SFR(ADCL, 0xBA); // ADC Data Low
172 SFR(ADCH, 0xBB); // ADC Data High
173 SFR(RNDL, 0xBC); // Random Number Generator Data Low Byte
174 SFR(RNDH, 0xBD); // Random Number Generator Data High Byte
175 SFR(SLEEP, 0xBE); // Sleep Mode Control
176 SFR(_SFRBF, 0xBF); // not used
177
178 SFR(IRCON, 0xC0); // Interrupt Flags 4
179 SBIT(DMAIF, 0xC0, 0); // DMA Complete Interrupt Flag
180 SBIT(T1IF, 0xC0, 1); // Timer 1 Interrupt Flag
181 SBIT(T2IF, 0xC0, 2); // Timer 2 Interrupt Flag
182 SBIT(T3IF, 0xC0, 3); // Timer 3 Interrupt Flag
183 SBIT(T4IF, 0xC0, 4); // Timer 4 Interrupt Flag
184 SBIT(P0IF, 0xC0, 5); // Port 0 Interrupt Flag
185 SBIT(STIF, 0xC0, 7); // Sleep Timer Interrupt Flag
186
187 SFR(U0DBUF, 0xC1); // USART 0 Receive/Transmit Data Buffer
188 SFR(U0BAUD, 0xC2); // USART 0 Baud Rate Control
189 SFR(_SFRC3, 0xC3); // not in use
190 SFR(U0UCR, 0xC4); // USART 0 UART Control
191 SFR(U0GCR, 0xC5); // USART 0 Generic Control
192 SFR(CLKCON, 0xC6); // Clock Control
193 SFR(MEMCTR, 0xC7); // Memory Arbiter Control
194
195 SFR(_SFRC8, 0xC8); // not in use
196 SFR(WDCTL, 0xC9); // Watchdog Timer Control
197 SFR(T3CNT, 0xCA); // Timer 3 Counter
198 SFR(T3CTL, 0xCB); // Timer 3 Control
199 SFR(T3CCTL0, 0xCC); // Timer 3 Channel 0 Capture/Compare Control
200 SFR(T3CC0, 0xCD); // Timer 3 Channel 0 Capture/Compare Value
201 SFR(T3CCTL1, 0xCE); // Timer 3 Channel 1 Capture/Compare Control
202 SFR(T3CC1, 0xCF); // Timer 3 Channel 1 Capture/Compare Value
203
204 SFR(PSW, 0xD0); // Program Status Word
205 SBIT(P, 0xD0, 0); // Parity Flag
206 SBIT(F1, 0xD0, 1); // User-Defined Flag
207 SBIT(OV, 0xD0, 2); // Overflow Flag
208 SBIT(RS0, 0xD0, 3); // Register Bank Select 0
209 SBIT(RS1, 0xD0, 4); // Register Bank Select 1
210 SBIT(F0, 0xD0, 5); // User-Defined Flag
211 SBIT(AC, 0xD0, 6); // Auxiliary Carry Flag
212 SBIT(CY, 0xD0, 7); // Carry Flag
213
214 SFR(DMAIRQ, 0xD1); // DMA Interrupt Flag
215 SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte
216 SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte
217 SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte
218 SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte
219 SFR(DMAARM, 0xD6); // DMA Channel Arm
220 SFR(DMAREQ, 0xD7); // DMA Channel Start Request and Status
221
222 SFR(TIMIF, 0xD8); // Timers 1/3/4 Interrupt Mask/Flag
223 SBIT(T3OVFIF, 0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending
224 SBIT(T3CH0IF, 0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending
225 SBIT(T3CH1IF, 0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending
226 SBIT(T4OVFIF, 0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending
227 SBIT(T4CH0IF, 0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending
228 SBIT(T4CH1IF, 0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending
229 SBIT(OVFIM, 0xD8, 6); // Timer 1 overflow interrupt mask
230
231 SFR(RFD, 0xD9); // RF Data
232 SFR(T1CC0L, 0xDA); // Timer 1 Channel 0 Capture/Compare Value Low Byte
233 SFR(T1CC0H, 0xDB); // Timer 1 Channel 0 Capture/Compare Value High Byte
234 SFR(T1CC1L, 0xDC); // Timer 1 Channel 1 Capture/Compare Value Low Byte
235 SFR(T1CC1H, 0xDD); // Timer 1 Channel 1 Capture/Compare Value High Byte
236 SFR(T1CC2L, 0xDE); // Timer 1 Channel 2 Capture/Compare Value Low Byte
237 SFR(T1CC2H, 0xDF); // Timer 1 Channel 2 Capture/Compare Value High Byte
238
239 SFR(ACC, 0xE0); // Accumulator
240 SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0
241 SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1
242 SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2
243 SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3
244 SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4
245 SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5
246 SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6
247 SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7
248
249 SFR(RFST, 0xE1); // RF Strobe Commands
250 SFR(T1CNTL, 0xE2); // Timer 1 Counter Low
251 SFR(T1CNTH, 0xE3); // Timer 1 Counter High
252 SFR(T1CTL, 0xE4); // Timer 1 Control and Status
253 SFR(T1CCTL0, 0xE5); // Timer 1 Channel 0 Capture/Compare Control
254 SFR(T1CCTL1, 0xE6); // Timer 1 Channel 1 Capture/Compare Control
255 SFR(T1CCTL2, 0xE7); // Timer 1 Channel 2 Capture/Compare Control
256
257 SFR(IRCON2, 0xE8); // Interrupt Flags 5
258 SBIT(P2IF, 0xE8, 0); // Port 2 Interrupt Flag
259 SBIT(UTX0IF, 0xE8, 1); // USART0 TX Interrupt Flag
260 SBIT(UTX1IF, 0xE8, 2); // USART1 TX Interrupt Flag
261 SBIT(P1IF, 0xE8, 3); // Port 1 Interrupt Flag
262 SBIT(WDTIF, 0xE8, 4); // Watchdog Timer Interrupt Flag
263
264 SFR(RFIF, 0xE9); // RF Interrupt Flags
265 SFR(T4CNT, 0xEA); // Timer 4 Counter
266 SFR(T4CTL, 0xEB); // Timer 4 Control
267 SFR(T4CCTL0, 0xEC); // Timer 4 Channel 0 Capture/Compare Control
268 SFR(T4CC0, 0xED); // Timer 4 Channel 0 Capture/Compare Value
269 SFR(T4CCTL1, 0xEE); // Timer 4 Channel 1 Capture/Compare Control
270 SFR(T4CC1, 0xEF); // Timer 4 Channel 1 Capture/Compare Value
271
272 SFR(B, 0xF0); // B Register
273 SBIT(B_0, 0xF0, 0); // Register B bit 0
274 SBIT(B_1, 0xF0, 1); // Register B bit 1
275 SBIT(B_2, 0xF0, 2); // Register B bit 2
276 SBIT(B_3, 0xF0, 3); // Register B bit 3
277 SBIT(B_4, 0xF0, 4); // Register B bit 4
278 SBIT(B_5, 0xF0, 5); // Register B bit 5
279 SBIT(B_6, 0xF0, 6); // Register B bit 6
280 SBIT(B_7, 0xF0, 7); // Register B bit 7
281
282 SFR(PERCFG, 0xF1); // Peripheral Control
283 SFR(ADCCFG, 0xF2); // ADC Input Configuration
284 SFR(P0SEL, 0xF3); // Port 0 Function Select
285 SFR(P1SEL, 0xF4); // Port 1 Function Select
286 SFR(P2SEL, 0xF5); // Port 2 Function Select
287 SFR(P1INP, 0xF6); // Port 1 Input Mode
288 SFR(P2INP, 0xF7); // Port 2 Input Mode
289
290 SFR(U1CSR, 0xF8); // USART 1 Control and Status
291 SBIT(ACTIVE, 0xF8, 0); // USART transmit/receive active status 0:idle 1:busy
292 SBIT(TX_BYTE, 0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted
293 SBIT(RX_BYTE, 0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready
294 SBIT(ERR, 0xF8, 3); // UART parity error status 0:No error 1:parity error
295 SBIT(FE, 0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level
296 SBIT(SLAVE, 0xF8, 5); // SPI master or slave mode select 0:master 1:slave
297 SBIT(RE, 0xF8, 6); // UART receiver enable 0:disabled 1:enabled
298 SBIT(MODE, 0xF8, 7); // USART mode select 0:SPI 1:UART
299
300 SFR(U1DBUF, 0xF9); // USART 1 Receive/Transmit Data Buffer
301 SFR(U1BAUD, 0xFA); // USART 1 Baud Rate Control
302 SFR(U1UCR, 0xFB); // USART 1 UART Control
303 SFR(U1GCR, 0xFC); // USART 1 Generic Control
304 SFR(P0DIR, 0xFD); // Port 0 Direction
305 SFR(P1DIR, 0xFE); // Port 1 Direction
306 SFR(P2DIR, 0xFF); // Port 2 Direction
307
308 /* ------------------------------------------------------------------------------------------------
309 * Xdata Radio Registers
310 * ------------------------------------------------------------------------------------------------
311 */
312
313 SFRX(MDMCTRL0H, 0xDF02);
314
315 SFRX(SYNC1, 0xDF00); /* Sync word, high byte */
316 SFRX(SYNC0, 0xDF01); /* Sync word, low byte */
317 SFRX(PKTLEN, 0xDF02); /* Packet length */
318 SFRX(PKTCTRL1, 0xDF03); /* Packet automation control */
319 SFRX(PKTCTRL0, 0xDF04); /* Packet automation control */
320 SFRX(ADDR, 0xDF05); /* Device address */
321 SFRX(CHANNR, 0xDF06); /* Channel number */
322 SFRX(FSCTRL1, 0xDF07); /* Frequency synthesizer control */
323 SFRX(FSCTRL0, 0xDF08); /* Frequency synthesizer control */
324 SFRX(FREQ2, 0xDF09); /* Frequency control word, high byte */
325 SFRX(FREQ1, 0xDF0A); /* Frequency control word, middle byte */
326 SFRX(FREQ0, 0xDF0B); /* Frequency control word, low byte */
327 SFRX(MDMCFG4, 0xDF0C); /* Modem configuration */
328 SFRX(MDMCFG3, 0xDF0D); /* Modem configuration */
329 SFRX(MDMCFG2, 0xDF0E); /* Modem configuration */
330 SFRX(MDMCFG1, 0xDF0F); /* Modem configuration */
331 SFRX(MDMCFG0, 0xDF10); /* Modem configuration */
332 SFRX(DEVIATN, 0xDF11); /* Modem deviation setting */
333 SFRX(MCSM2, 0xDF12); /* Main Radio Control State Machine configuration */
334 SFRX(MCSM1, 0xDF13); /* Main Radio Control State Machine configuration */
335 SFRX(MCSM0, 0xDF14); /* Main Radio Control State Machine configuration */
336 SFRX(FOCCFG, 0xDF15); /* Frequency Offset Compensation configuration */
337 SFRX(BSCFG, 0xDF16); /* Bit Synchronization configuration */
338 SFRX(AGCCTRL2, 0xDF17); /* AGC control */
339 SFRX(AGCCTRL1, 0xDF18); /* AGC control */
340 SFRX(AGCCTRL0, 0xDF19); /* AGC control */
341 SFRX(FREND1, 0xDF1A); /* Front end RX configuration */
342 SFRX(FREND0, 0xDF1B); /* Front end TX configuration */
343 SFRX(FSCAL3, 0xDF1C); /* Frequency synthesizer calibration */
344 SFRX(FSCAL2, 0xDF1D); /* Frequency synthesizer calibration */
345 SFRX(FSCAL1, 0xDF1E); /* Frequency synthesizer calibration */
346 SFRX(FSCAL0, 0xDF1F); /* Frequency synthesizer calibration */
347 SFRX(_XREGDF20, 0xDF20); /* reserved */
348 SFRX(_XREGDF21, 0xDF21); /* reserved */
349 SFRX(_XREGDF22, 0xDF22); /* reserved */
350 SFRX(TEST2, 0xDF23); /* Various test settings */
351 SFRX(TEST1, 0xDF24); /* Various test settings */
352 SFRX(TEST0, 0xDF25); /* Various test settings */
353 SFRX(_XREGDF26, 0xDF26); /* reserved */
354 SFRX(PA_TABLE7, 0xDF27); /* PA power setting 7 */
355 SFRX(PA_TABLE6, 0xDF28); /* PA power setting 6 */
356 SFRX(PA_TABLE5, 0xDF29); /* PA power setting 5 */
357 SFRX(PA_TABLE4, 0xDF2A); /* PA power setting 4 */
358 SFRX(PA_TABLE3, 0xDF2B); /* PA power setting 3 */
359 SFRX(PA_TABLE2, 0xDF2C); /* PA power setting 2 */
360 SFRX(PA_TABLE1, 0xDF2D); /* PA power setting 1 */
361 SFRX(PA_TABLE0, 0xDF2E); /* PA power setting 0 */
362 SFRX(IOCFG2, 0xDF2F); /* Radio Test Signal Configuration (P1_7) */
363 SFRX(IOCFG1, 0xDF30); /* Radio Test Signal Configuration (P1_6) */
364 SFRX(IOCFG0, 0xDF31); /* Radio Test Signal Configuration (P1_5) */
365 SFRX(_XREGDF32, 0xDF32); /* reserved */
366 SFRX(_XREGDF33, 0xDF33); /* reserved */
367 SFRX(_XREGDF34, 0xDF34); /* reserved */
368 SFRX(_XREGDF35, 0xDF35); /* reserved */
369 SFRX(PARTNUM, 0xDF36); /* Chip ID [15:8] */
370 SFRX(VERSION, 0xDF37); /* Chip ID [7:0] */
371 SFRX(FREQEST, 0xDF38); /* Frequency Offset Estimate */
372 SFRX(LQI, 0xDF39); /* Link Quality Indicator */
373 SFRX(RSSI, 0xDF3A); /* Received Signal Strength Indication */
374 SFRX(MARCSTATE, 0xDF3B); /* Main Radio Control State */
375 SFRX(PKTSTATUS, 0xDF3C); /* Packet status */
376 SFRX(VCO_VC_DAC, 0xDF3D); /* PLL calibration current */
377
378 /* ------------------------------------------------------------------------------------------------
379 * Xdata I2S Registers
380 * ------------------------------------------------------------------------------------------------
381 */
382 SFRX(I2SCFG0, 0xDF40); /* I2S Configuration Register 0 */
383 SFRX(I2SCFG1, 0xDF41); /* I2S Configuration Register 1 */
384 SFRX(I2SDATL, 0xDF42); /* I2S Data Low Byte */
385 SFRX(I2SDATH, 0xDF43); /* I2S Data High Byte */
386 SFRX(I2SWCNT, 0xDF44); /* I2S Word Count Register */
387 SFRX(I2SSTAT, 0xDF45); /* I2S Status Register */
388 SFRX(I2SCLKF0, 0xDF46); /* I2S Clock Configuration Register 0 */
389 SFRX(I2SCLKF1, 0xDF47); /* I2S Clock Configuration Register 1 */
390 SFRX(I2SCLKF2, 0xDF48); /* I2S Clock Configuration Register 2 */
391
392 /* ------------------------------------------------------------------------------------------------
393 * Xdata Mapped SFRs
394 * ------------------------------------------------------------------------------------------------
395 */
396
397 /*
398 * Most SFRs are also accessible through XDATA address space. The register definitions for
399 * this type of access are listed below. The register names are identical to the SFR names
400 * but with the prefix X_ to denote an XDATA register.
401 *
402 * Some SFRs are not accessible through XDATA space. For clarity, entries are included for these
403 * registers. They have a prefix of _NA to denote "not available."
404 *
405 * The SFRs prefixed with _X_ are not in use, but are listed for a better overview.
406 *
407 * For register descriptions, refer to the actual SFR declarations elsewhere in this file.
408 */
409
410 SFRX(_NA_P0, 0xDF80);
411 SFRX(_NA_SP, 0xDF81);
412 SFRX(_NA_DPL0, 0xDF82);
413 SFRX(_NA_DPH0, 0xDF83);
414 SFRX(_NA_DPL1, 0xDF84);
415 SFRX(_NA_DPH1, 0xDF85);
416 SFRX(X_U0CSR, 0xDF86);
417 SFRX(_NA_PCON, 0xDF87);
418
419 SFRX(_NA_TCON, 0xDF88);
420 SFRX(X_P0IFG, 0xDF89);
421 SFRX(X_P1IFG, 0xDF8A);
422 SFRX(X_P2IFG, 0xDF8B);
423 SFRX(X_PICTL, 0xDF8C);
424 SFRX(X_P1IEN, 0xDF8D);
425 SFRX(_X_SFR8E, 0xDF8E);
426 SFRX(X_P0INP, 0xDF8F);
427
428 SFRX(_NA_P1, 0xDF90);
429 SFRX(X_RFIM, 0xDF91);
430 SFRX(_NA_DPS, 0xDF92);
431 SFRX(X_MPAGE, 0xDF93);
432 SFRX(_X_SFR94, 0xDF94);
433 SFRX(_X_SFR95, 0xDF95);
434 SFRX(_X_SFR96, 0xDF96);
435 SFRX(_X_SFR97, 0xDF97);
436
437 SFRX(_NA_S0CON, 0xDF98);
438 SFRX(_X_SFR99, 0xDF99);
439 SFRX(_NA_IEN2, 0xDF9A);
440 SFRX(_NA_S1CON, 0xDF9B);
441 SFRX(X_T2CT, 0xDF9C);
442 SFRX(X_T2PR, 0xDF9D);
443 SFRX(X_T2CTL, 0xDF9E);
444 SFRX(_X_SFR9F, 0xDF9F);
445
446 SFRX(_NA_P2, 0xDFA0);
447 SFRX(X_WORIRQ, 0xDFA1);
448 SFRX(X_WORCTRL, 0xDFA2);
449 SFRX(X_WOREVT0, 0xDFA3);
450 SFRX(X_WOREVT1, 0xDFA4);
451 SFRX(X_WORTIME0, 0xDFA5);
452 SFRX(X_WORTIME1, 0xDFA6);
453 SFRX(_X_SFRA7, 0xDFA7);
454
455 SFRX(_NA_IEN0, 0xDFA8);
456 SFRX(_NA_IP0, 0xDFA9);
457 SFRX(_X_SFRAA, 0xDFAA);
458 SFRX(X_FWT, 0xDFAB);
459 SFRX(X_FADDRL, 0xDFAC);
460 SFRX(X_FADDRH, 0xDFAD);
461 SFRX(X_FCTL, 0xDFAE);
462 SFRX(X_FWDATA, 0xDFAF);
463
464 SFRX(_X_SFRB0, 0xDFB0);
465 SFRX(X_ENCDI, 0xDFB1);
466 SFRX(X_ENCDO, 0xDFB2);
467 SFRX(X_ENCCS, 0xDFB3);
468 SFRX(X_ADCCON1, 0xDFB4);
469 SFRX(X_ADCCON2, 0xDFB5);
470 SFRX(X_ADCCON3, 0xDFB6);
471 SFRX(_X_SFRB7, 0xDFB7);
472
473 SFRX(_NA_IEN1, 0xDFB8);
474 SFRX(_NA_IP1, 0xDFB9);
475 SFRX(X_ADCL, 0xDFBA);
476 SFRX(X_ADCH, 0xDFBB);
477 SFRX(X_RNDL, 0xDFBC);
478 SFRX(X_RNDH, 0xDFBD);
479 SFRX(X_SLEEP, 0xDFBE);
480 SFRX(_X_SFRBF, 0xDFBF);
481
482 SFRX(_NA_IRCON, 0xDFC0);
483 SFRX(X_U0DBUF, 0xDFC1);
484 SFRX(X_U0BAUD, 0xDFC2);
485 SFRX(_X_SFRC3, 0xDFC3);
486 SFRX(X_U0UCR, 0xDFC4);
487 SFRX(X_U0GCR, 0xDFC5);
488 SFRX(X_CLKCON, 0xDFC6);
489 SFRX(X_MEMCTR, 0xDFC7);
490
491 SFRX(_X_SFRC8, 0xDFC8);
492 SFRX(X_WDCTL, 0xDFC9);
493 SFRX(X_T3CNT, 0xDFCA);
494 SFRX(X_T3CTL, 0xDFCB);
495 SFRX(X_T3CCTL0, 0xDFCC);
496 SFRX(X_T3CC0, 0xDFCD);
497 SFRX(X_T3CCTL1, 0xDFCE);
498 SFRX(X_T3CC1, 0xDFCF);
499
500 SFRX(_NA_PSW, 0xDFD0);
501 SFRX(X_DMAIRQ, 0xDFD1);
502 SFRX(X_DMA1CFGL, 0xDFD2);
503 SFRX(X_DMA1CFGH, 0xDFD3);
504 SFRX(X_DMA0CFGL, 0xDFD4);
505 SFRX(X_DMA0CFGH, 0xDFD5);
506 SFRX(X_DMAARM, 0xDFD6);
507 SFRX(X_DMAREQ, 0xDFD7);
508
509 SFRX(X_TIMIF, 0xDFD8);
510 SFRX(X_RFD, 0xDFD9);
511 SFRX(X_T1CC0L, 0xDFDA);
512 SFRX(X_T1CC0H, 0xDFDB);
513 SFRX(X_T1CC1L, 0xDFDC);
514 SFRX(X_T1CC1H, 0xDFDD);
515 SFRX(X_T1CC2L, 0xDFDE);
516 SFRX(X_T1CC2H, 0xDFDF);
517
518 SFRX(_NA_ACC, 0xDFE0);
519 SFRX(X_RFST, 0xDFE1);
520 SFRX(X_T1CNTL, 0xDFE2);
521 SFRX(X_T1CNTH, 0xDFE3);
522 SFRX(X_T1CTL, 0xDFE4);
523 SFRX(X_T1CCTL0, 0xDFE5);
524 SFRX(X_T1CCTL1, 0xDFE6);
525 SFRX(X_T1CCTL2, 0xDFE7);
526
527 SFRX(_NA_IRCON2, 0xDFE8);
528 SFRX(X_RFIF, 0xDFE9);
529 SFRX(X_T4CNT, 0xDFEA);
530 SFRX(X_T4CTL, 0xDFEB);
531 SFRX(X_T4CCTL0, 0xDFEC);
532 SFRX(X_T4CC0, 0xDFED);
533 SFRX(X_T4CCTL1, 0xDFEE);
534 SFRX(X_T4CC1, 0xDFEF);
535
536 SFRX(_NA_B, 0xDFF0);
537 SFRX(X_PERCFG, 0xDFF1);
538 SFRX(X_ADCCFG, 0xDFF2);
539 SFRX(X_P0SEL, 0xDFF3);
540 SFRX(X_P1SEL, 0xDFF4);
541 SFRX(X_P2SEL, 0xDFF5);
542 SFRX(X_P1INP, 0xDFF6);
543 SFRX(X_P2INP, 0xDFF7);
544
545 SFRX(X_U1CSR, 0xDFF8);
546 SFRX(X_U1DBUF, 0xDFF9);
547 SFRX(X_U1BAUD, 0xDFFA);
548 SFRX(X_U1UCR, 0xDFFB);
549 SFRX(X_U1GCR, 0xDFFC);
550 SFRX(X_P0DIR, 0xDFFD);
551 SFRX(X_P1DIR, 0xDFFE);
552 SFRX(X_P2DIR, 0xDFFF);
553
554 /* ------------------------------------------------------------------------------------------------
555 */
556
557 #endif
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