sdcc/device/include/mcs51/cc2430.h

   1 /*-------------------------------------------------------------------------
   2    cc2430.h - Register Declarations for Chipcon CC2430
   3    (Based on CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A)
   4
   5    Copyright (C) 2006, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef REG_CC2430_H
  31 #define REG_CC2430_H
  32
  33 #include <compiler.h>
  34
  35 // Interrupt Vectors
  36
  37 #define RFERR_VECTOR    0   // RF TX FIFO underflow and RX FIFO overflow.
  38 #define ADC_VECTOR      1   // ADC end of conversion
  39 #define URX0_VECTOR     2   // USART0 RX complete
  40 #define URX1_VECTOR     3   // USART1 RX complete
  41 #define ENC_VECTOR      4   // AES encryption/decryption complete
  42 #define ST_VECTOR       5   // Sleep Timer compare
  43 #define P2INT_VECTOR    6   // Port 2 inputs
  44 #define UTX0_VECTOR     7   // USART0 TX complete
  45 #define DMA_VECTOR      8   // DMA transfer complete
  46 #define T1_VECTOR       9   // Timer 1 (16-bit) capture/compare/overflow
  47 #define T2_VECTOR       10  // Timer 2 (MAC Timer)
  48 #define T3_VECTOR       11  // Timer 3 (8-bit) capture/compare/overflow
  49 #define T4_VECTOR       12  // Timer 4 (8-bit) capture/compare/overflow
  50 #define P0INT_VECTOR    13  // Port 0 inputs
  51 #define UTX1_VECTOR     14  // USART1 TX complete
  52 #define P1INT_VECTOR    15  // Port 1 inputs
  53 #define RF_VECTOR       16  // RF general interrupts
  54 #define WDT_VECTOR      17  // Watchdog overflow in timer mode
  55
  56 // SFR Registers and BITs
  57
  58 SFR(P0,       0x80); // Port 0
  59    SBIT(P0_0,     0x80, 0); // Port 0 bit 0
  60    SBIT(P0_1,     0x80, 1); // Port 0 bit 1
  61    SBIT(P0_2,     0x80, 2); // Port 0 bit 2
  62    SBIT(P0_3,     0x80, 3); // Port 0 bit 3
  63    SBIT(P0_4,     0x80, 4); // Port 0 bit 4
  64    SBIT(P0_5,     0x80, 5); // Port 0 bit 5
  65    SBIT(P0_6,     0x80, 6); // Port 0 bit 6
  66    SBIT(P0_7,     0x80, 7); // Port 0 bit 7
  67 SFR(SP,       0x81); // Stack Pointer
  68 SFR(DPL0,     0x82); // Data Pointer 0 Low Byte
  69 SFR(DPH0,     0x83); // Data Pointer 0 High Byte
  70 SFR(DPL1,     0x84); // Data Pointer 1 Low Byte
  71 SFR(DPH1,     0x85); // Data Pointer 1 High Byte
  72 SFR(U0CSR,    0x86); // USART 0 Control and Status
  73 SFR(PCON,     0x87); // Power Mode Control
  74 SFR(TCON,     0x88); // Interrupt Flags
  75    SBIT(IT0,      0x88, 0); // reserved (must always be set to 1)
  76    SBIT(RFERRIF,  0x88, 1); // RFERR - RF TX/RX FIFO interrupt flag
  77    SBIT(IT1,      0x88, 2); // reserved (must always be set to 1)
  78    SBIT(URX0IF,   0x88, 3); // USART0 RX Interrupt Flag
  79    SBIT(ADCIF,    0x88, 5); // ADC Interrupt Flag
  80    SBIT(URX1IF,   0x88, 7); // USART1 RX Interrupt Flag
  81 SFR(P0IFG,    0x89); // Port 0 Interrupt Status Flag
  82 SFR(P1IFG,    0x8A); // Port 1 Interrupt Status Flag
  83 SFR(P2IFG,    0x8B); // Port 2 Interrupt Status Flag
  84 SFR(PICTL,    0x8C); // Port Interrupt Control
  85 SFR(P1IEN,    0x8D); // Port 1 Interrupt Mask
  86 SFR(P0INP,    0x8F); // Port 0 Input Mode
  87 SFR(P1,       0x90); // Port 1
  88    SBIT(P1_0,     0x90, 0); // Port 1 bit 0
  89    SBIT(P1_1,     0x90, 1); // Port 1 bit 1
  90    SBIT(P1_2,     0x90, 2); // Port 1 bit 2
  91    SBIT(P1_3,     0x90, 3); // Port 1 bit 3
  92    SBIT(P1_4,     0x90, 4); // Port 1 bit 4
  93    SBIT(P1_5,     0x90, 5); // Port 1 bit 5
  94    SBIT(P1_6,     0x90, 6); // Port 1 bit 6
  95    SBIT(P1_7,     0x90, 7); // Port 1 bit 7
  96 SFR(RFIM,     0x91); // RF Interrupt Mask
  97 SFR(DPS,      0x92); // Data Pointer Select
  98 SFR(MPAGE,    0x93); // Memory Page Select
  99 SFR(_XPAGE,   0x93); // Memory Page Select under the name SDCC needs it
 100 SFR(T2CMP,    0x94); // Timer 2 Compare Value
 101 SFR(ST0,      0x95); // Sleep Timer 0
 102 SFR(ST1,      0x96); // Sleep Timer 1
 103 SFR(ST2,      0x97); // Sleep Timer 2
 104 SFR(S0CON,    0x98); // Interrupt Flags 2
 105    SBIT(ENCIF_0,  0x98, 0); // AES Interrupt Flag 0
 106    SBIT(ENCIF_1,  0x98, 1); // AES Interrupt Flag 1
 107 SFR(IEN2,     0x9A); // Interrupt Enable 2
 108 SFR(S1CON,    0x9B); // Interrupt Flags 3
 109 SFR(T2PEROF0, 0x9C); // Timer 2 Overflow Capture/Compare 0
 110 SFR(T2PEROF1, 0x9D); // Timer 2 Overflow Capture/Compare 1
 111 SFR(T2PEROF2, 0x9E); // Timer 2 Overflow Capture/Compare 2
 112 SFR(FMAP    , 0x9F); // Flash Bank Map
 113 SFR(P2,       0xA0); // Port 2
 114    SBIT(P2_0,     0xA0, 0); // Port 2 bit 0
 115    SBIT(P2_1,     0xA0, 1); // Port 2 bit 1
 116    SBIT(P2_2,     0xA0, 2); // Port 2 bit 2
 117    SBIT(P2_3,     0xA0, 3); // Port 2 bit 3
 118    SBIT(P2_4,     0xA0, 4); // Port 2 bit 4
 119    SBIT(P2_5,     0xA0, 5); // Port 2 bit 5
 120    SBIT(P2_6,     0xA0, 6); // Port 2 bit 6
 121    SBIT(P2_7,     0xA0, 7); // Port 2 bit 7
 122 SFR(T2OF0,    0xA1); // Timer 2 Overflow Count 0
 123 SFR(T2OF1,    0xA2); // Timer 2 Overflow Count 1
 124 SFR(T2OF2,    0xA3); // Timer 2 Overflow Count 2
 125 SFR(T2CAPLPL, 0xA4); // Timer 2 Period Low Byte
 126 SFR(T2CAPHPH, 0xA5); // Timer 2 Period High Byte
 127 SFR(T2TLD,    0xA6); // Timer 2 Timer Value Low Byte
 128 SFR(T2THD,    0xA7); // Timer 2 Timer Value High Byte
 129 SFR(IEN0,     0xA8); // Interrupt Enable 0
 130    SBIT(RFERRIE,  0xA8, 0); // RF TX/RX FIFO interrupt enable
 131    SBIT(ADCIE,    0xA8, 1); // ADC Interrupt Enable
 132    SBIT(URX0IE,   0xA8, 2); // USART0 RX Interrupt Enable
 133    SBIT(URX1IE,   0xA8, 3); // USART1 RX Interrupt Enable
 134    SBIT(ENCIE,    0xA8, 4); // AES Encryption/Decryption Interrupt Enable
 135    SBIT(STIE,     0xA8, 5); // Sleep Timer Interrupt Enable
 136    SBIT(EA,       0xA8, 7); // Global Interrupt Enable
 137 SFR(IP0,      0xA9); // Interrupt Priority 0
 138 SFR(FWT,      0xAB); // Flash Write Timing
 139 SFR(FADDRL,   0xAC); // Flash Address Low Byte
 140 SFR(FADDRH,   0xAD); // Flash Address High Byte
 141 SFR(FCTL,     0xAE); // Flash Control
 142 SFR(FWDATA,   0xAF); // Flash Write Data
 143 SFR(ENCDI,    0xB1); // Encryption Input Data
 144 SFR(ENCDO,    0xB2); // Encryption Output Data
 145 SFR(ENCCS,    0xB3); // Encryption Control and Status
 146 SFR(ADCCON1,  0xB4); // ADC Control 1
 147 SFR(ADCCON2,  0xB5); // ADC Control 2
 148 SFR(ADCCON3,  0xB6); // ADC Control 3
 149 SFR(IEN1,     0xB8); // Interrupt Enable 1
 150    SBIT(DMAIE,    0xB8, 0); // DMA Transfer Interrupt Enable
 151    SBIT(T1IE,     0xB8, 1); // Timer 1 Interrupt Enable
 152    SBIT(T2IE,     0xB8, 2); // Timer 2 Interrupt Enable
 153    SBIT(T3IE,     0xB8, 3); // Timer 3 Interrupt Enable
 154    SBIT(T4IE,     0xB8, 4); // Timer 4 Interrupt Enable
 155    SBIT(P0IE,     0xB8, 5); // Port 0 Interrupt Enable
 156 SFR(IP1,      0xB9); // Interrupt Priority 1
 157 SFR(ADCL,     0xBA); // ADC Data Low
 158 SFR(ADCH,     0xBB); // ADC Data High
 159 SFR(RNDL,     0xBC); // Random Number Generator Data Low Byte
 160 SFR(RNDH,     0xBD); // Random Number Generator Data High Byte
 161 SFR(SLEEP,    0xBE); // Sleep Mode Control
 162 SFR(IRCON,    0xC0); // Interrupt Flags 4
 163    SBIT(DMAIF,    0xC0, 0); // DMA Complete Interrupt Flag
 164    SBIT(T1IF,     0xC0, 1); // Timer 1 Interrupt Flag
 165    SBIT(T2IF,     0xC0, 2); // Timer 2 Interrupt Flag
 166    SBIT(T3IF,     0xC0, 3); // Timer 3 Interrupt Flag
 167    SBIT(T4IF,     0xC0, 4); // Timer 4 Interrupt Flag
 168    SBIT(P0IF,     0xC0, 5); // Port 0 Interrupt Flag
 169    SBIT(STIF,     0xC0, 7); // Sleep Timer Interrupt Flag
 170 SFR(U0DBUF,   0xC1); // USART 0 Receive/Transmit Data Buffer
 171 SFR(U0BAUD,   0xC2); // USART 0 Baud Rate Control
 172 SFR(T2CNF,    0xC3); // Timer 2 Configuration
 173 SFR(U0UCR,    0xC4); // USART 0 UART Control
 174 SFR(U0GCR,    0xC5); // USART 0 Generic Control
 175 SFR(CLKCON,   0xC6); // Clock Control
 176 SFR(MEMCTR,   0xC7); // Memory Arbiter Control
 177 SFR(WDCTL,    0xC9); // Watchdog Timer Control
 178 SFR(T3CNT,    0xCA); // Timer 3 Counter
 179 SFR(T3CTL,    0xCB); // Timer 3 Control
 180 SFR(T3CCTL0,  0xCC); // Timer 3 Channel 0 Capture/Compare Control
 181 SFR(T3CC0,    0xCD); // Timer 3 Channel 0 Capture/Compare Value
 182 SFR(T3CCTL1,  0xCE); // Timer 3 Channel 1 Capture/Compare Control
 183 SFR(T3CC1,    0xCF); // Timer 3 Channel 1 Capture/Compare Value
 184 SFR(PSW,      0xD0); // Program Status Word
 185    SBIT(P,        0xD0, 0); // Parity Flag
 186    SBIT(F1,       0xD0, 1); // User-Defined Flag
 187    SBIT(OV,       0xD0, 2); // Overflow Flag
 188    SBIT(RS0,      0xD0, 3); // Register Bank Select 0
 189    SBIT(RS1,      0xD0, 4); // Register Bank Select 1
 190    SBIT(F0,       0xD0, 5); // User-Defined Flag
 191    SBIT(AC,       0xD0, 6); // Auxiliary Carry Flag
 192    SBIT(CY,       0xD0, 7); // Carry Flag
 193 SFR(DMAIRQ,   0xD1); // DMA Interrupt Flag
 194 SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte
 195 SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte
 196 SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte
 197 SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte
 198 SFR(DMAARM,   0xD6); // DMA Channel Arm
 199 SFR(DMAREQ,   0xD7); // DMA Channel Start Request and Status
 200 SFR(TIMIF,    0xD8); // Timers 1/3/4 Interrupt Mask/Flag
 201    SBIT(T3OVFIF,  0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending
 202    SBIT(T3CH0IF,  0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending
 203    SBIT(T3CH1IF,  0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending
 204    SBIT(T4OVFIF,  0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending
 205    SBIT(T4CH0IF,  0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending
 206    SBIT(T4CH1IF,  0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending
 207    SBIT(OVFIM,    0xD8, 6); // Timer 1 overflow interrupt mask
 208 SFR(RFD,      0xD9); // RF Data
 209 SFR(T1CC0L,   0xDA); // Timer 1 Channel 0 Capture/Compare Value Low
 210 SFR(T1CC0H,   0xDB); // Timer 1 Channel 0 Capture/Compare Value High
 211 SFR(T1CC1L,   0xDC); // Timer 1 Channel 1 Capture/Compare Value Low
 212 SFR(T1CC1H,   0xDD); // Timer 1 Channel 1 Capture/Compare Value High
 213 SFR(T1CC2L,   0xDE); // Timer 1 Channel 2 Capture/Compare Value Low
 214 SFR(T1CC2H,   0xDF); // Timer 1 Channel 2 Capture/Compare Value High
 215 SFR(ACC,      0xE0); // Accumulator
 216    SBIT(ACC_0,    0xE0, 0); // Accumulator bit 0
 217    SBIT(ACC_1,    0xE0, 1); // Accumulator bit 1
 218    SBIT(ACC_2,    0xE0, 2); // Accumulator bit 2
 219    SBIT(ACC_3,    0xE0, 3); // Accumulator bit 3
 220    SBIT(ACC_4,    0xE0, 4); // Accumulator bit 4
 221    SBIT(ACC_5,    0xE0, 5); // Accumulator bit 5
 222    SBIT(ACC_6,    0xE0, 6); // Accumulator bit 6
 223    SBIT(ACC_7,    0xE0, 7); // Accumulator bit 7
 224 SFR(RFST,     0xE1); // RF CSMA-CA / Strobe Processor
 225 SFR(T1CNTL,   0xE2); // Timer 1 Counter Low
 226 SFR(T1CNTH,   0xE3); // Timer 1 Counter High
 227 SFR(T1CTL,    0xE4); // Timer 1 Control and Status
 228 SFR(T1CCTL0,  0xE5); // Timer 1 Channel 0 Capture/Compare Control
 229 SFR(T1CCTL1,  0xE6); // Timer 1 Channel 1 Capture/Compare Control
 230 SFR(T1CCTL2,  0xE7); // Timer 1 Channel 2 Capture/Compare Control
 231 SFR(IRCON2,   0xE8); // Interrupt Flags 5
 232    SBIT(P2IF,     0xE8, 0); // Port 2 Interrupt Flag
 233    SBIT(UTX0IF,   0xE8, 1); // USART0 TX Interrupt Flag
 234    SBIT(UTX1IF,   0xE8, 2); // USART1 TX Interrupt Flag
 235    SBIT(P1IF,     0xE8, 3); // Port 1 Interrupt Flag
 236    SBIT(WDTIF,    0xE8, 4); // Watchdog Timer Interrupt Flag
 237 SFR(RFIF,     0xE9); // RF Interrupt Flags
 238 SFR(T4CNT,    0xEA); // Timer 4 Counter
 239 SFR(T4CTL,    0xEB); // Timer 4 Control
 240 SFR(T4CCTL0,  0xEC); // Timer 4 Channel 0 Capture/Compare Control
 241 SFR(T4CC0,    0xED); // Timer 4 Channel 0 Capture/Compare Value
 242 SFR(T4CCTL1,  0xEE); // Timer 4 Channel 1 Capture/Compare Control
 243 SFR(T4CC1,    0xEF); // Timer 4 Channel 1 Capture/Compare Value
 244 SFR(B,        0xF0); // B Register
 245    SBIT(B_0,      0xF0, 0); // Register B bit 0
 246    SBIT(B_1,      0xF0, 1); // Register B bit 1
 247    SBIT(B_2,      0xF0, 2); // Register B bit 2
 248    SBIT(B_3,      0xF0, 3); // Register B bit 3
 249    SBIT(B_4,      0xF0, 4); // Register B bit 4
 250    SBIT(B_5,      0xF0, 5); // Register B bit 5
 251    SBIT(B_6,      0xF0, 6); // Register B bit 6
 252    SBIT(B_7,      0xF0, 7); // Register B bit 7
 253 SFR(PERCFG,   0xF1); // Peripheral Control
 254 SFR(ADCCFG,   0xF2); // ADC Input Configuration
 255 SFR(P0SEL,    0xF3); // Port 0 Function Select
 256 SFR(P1SEL,    0xF4); // Port 1 Function Select
 257 SFR(P2SEL,    0xF5); // Port 2 Function Select
 258 SFR(P1INP,    0xF6); // Port 1 Input Mode
 259 SFR(P2INP,    0xF7); // Port 2 Input Mode
 260 SFR(U1CSR,    0xF8); // USART 1 Control and Status
 261    SBIT(ACTIVE,   0xF8, 0); // USART transmit/receive active status 0:idle 1:busy
 262    SBIT(TX_BYTE,  0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted
 263    SBIT(RX_BYTE,  0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready
 264    SBIT(ERR,      0xF8, 3); // UART parity error status 0:No error 1:parity error
 265    SBIT(FE,       0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level
 266    SBIT(SLAVE,    0xF8, 5); // SPI master or slave mode select 0:master 1:slave
 267    SBIT(RE,       0xF8, 6); // UART receiver enable 0:disabled 1:enabled
 268    SBIT(MODE,     0xF8, 7); // USART mode select 0:SPI 1:UART
 269 SFR(U1DBUF,   0xF9); // USART 1 Receive/Transmit Data Buffer
 270 SFR(U1BAUD,   0xFA); // USART 1 Baud Rate Control
 271 SFR(U1UCR,    0xFB); // USART 1 UART Control
 272 SFR(U1GCR,    0xFC); // USART 1 Generic Control
 273 SFR(P0DIR,    0xFD); // Port 0 Direction
 274 SFR(P1DIR,    0xFE); // Port 1 Direction
 275 SFR(P2DIR,    0xFF); // Port 2 Direction
 276
 277 // From Table 45 : Overview of RF registers
 278
 279 SFRX(MDMCTRL0H,  0xDF02); // Modem Control 0,  high
 280 SFRX(MDMCTRL0L,  0xDF03); // Modem Control 0,  low
 281 SFRX(MDMCTRL1H,  0xDF04); // Modem Control 1,  high
 282 SFRX(MDMCTRL1L,  0xDF05); // Modem Control 1,  low
 283 SFRX(RSSIH,      0xDF06); // RSSI and CCA Status and Control,  high
 284 SFRX(RSSIL,      0xDF07); // RSSI and CCA Status and Control,  low
 285 SFRX(SYNCWORDH,  0xDF08); // Synchronisation Word Control,  high
 286 SFRX(SYNCWORDL,  0xDF09); // Synchronisation Word Control,  low
 287 SFRX(TXCTRLH,    0xDF0A); // Transmit Control,  high
 288 SFRX(TXCTRLL,    0xDF0B); // Transmit Control,  low
 289 SFRX(RXCTRL0H,   0xDF0C); // Receive Control 0,  high
 290 SFRX(RXCTRL0L,   0xDF0D); // Receive Control 0,  low
 291 SFRX(RXCTRL1H,   0xDF0E); // Receive Control 1,  high
 292 SFRX(RXCTRL1L,   0xDF0F); // Receive Control 1,  low
 293 SFRX(FSCTRLH,    0xDF10); // Frequency Synthesizer Control and Status,  high
 294 SFRX(FSCTRLL,    0xDF11); // Frequency Synthesizer Control and Status,  low
 295 SFRX(CSPX,       0xDF12); // CSP X Data
 296 SFRX(CSPY,       0xDF13); // CSP Y Data
 297 SFRX(CSPZ,       0xDF14); // CSP Z Data
 298 SFRX(CSPCTRL,    0xDF15); // CSP Control
 299 SFRX(CSPT,       0xDF16); // CSP T Data
 300 SFRX(RFPWR,      0xDF17); // RF Power Control
 301 SFRX(FSMTCH,     0xDF20); // Finite State Machine Time Constants,  high
 302 SFRX(FSMTCL,     0xDF21); // Finite State Machine Time Constants,  low
 303 SFRX(MANANDH,    0xDF22); // Manual AND Override,  high
 304 SFRX(MANANDL,    0xDF23); // Manual AND Override,  low
 305 SFRX(MANORH,     0xDF24); // Manual OR Override,  high
 306 SFRX(MANORL,     0xDF25); // Manual OR Override,  low
 307 SFRX(AGCCTRLH,   0xDF26); // AGC Control,  high
 308 SFRX(AGCCTRLL,   0xDF27); // AGC Control,  low
 309 SFRX(FSMSTATE,   0xDF39); // Finite State Machine State Status
 310 SFRX(ADCTSTH,    0xDF3A); // ADC Test,  high
 311 SFRX(ADCTSTL,    0xDF3B); // ADC Test,  low
 312 SFRX(DACTSTH,    0xDF3C); // DAC Test,  high
 313 SFRX(DACTSTL,    0xDF3D); // DAC Test,  low
 314 SFRX(IEEE_ADDR0, 0xDF43); // IEEE Address 0
 315 SFRX(IEEE_ADDR1, 0xDF44); // IEEE Address 1
 316 SFRX(IEEE_ADDR2, 0xDF45); // IEEE Address 2
 317 SFRX(IEEE_ADDR3, 0xDF46); // IEEE Address 3
 318 SFRX(IEEE_ADDR4, 0xDF47); // IEEE Address 4
 319 SFRX(IEEE_ADDR5, 0xDF48); // IEEE Address 5
 320 SFRX(IEEE_ADDR6, 0xDF49); // IEEE Address 6
 321 SFRX(IEEE_ADDR7, 0xDF4A); // IEEE Address 7
 322 SFRX(PANIDH,     0xDF4B); // PAN Identifier,  high
 323 SFRX(PANIDL,     0xDF4C); // PAN Identifier,  low
 324 SFRX(SHORTADDRH, 0xDF4D); // Short Address,  high
 325 SFRX(SHORTADDRL, 0xDF4E); // Short Address,  low
 326 SFRX(IOCFG0,     0xDF4F); // I/O Configuration 0
 327 SFRX(IOCFG1,     0xDF50); // I/O Configuration 1
 328 SFRX(IOCFG2,     0xDF51); // I/O Configuration 2
 329 SFRX(IOCFG3,     0xDF52); // I/O Configuration 3
 330 SFRX(RXFIFOCNT,  0xDF53); // RX FIFO Count
 331 SFRX(FSMTC1,     0xDF54); // Finite State Machine Control
 332 SFRX(CHVER,      0xDF60); // Chip Version
 333 SFRX(CHIPID,     0xDF61); // Chip Identification
 334 SFRX(RFSTATUS,   0xDF62); // RF Status
 335
 336 // SFRs also accesible through XDATA space
 337
 338 SFRX(X_U0CSR,    0xDF86); // USART 0 Control and Status
 339 SFRX(X_P0IFG,    0xDF89); // Port 0 Interrupt Status Flag
 340 SFRX(X_P1IFG,    0xDF8A); // Port 1 Interrupt Status Flag
 341 SFRX(X_P2IFG,    0xDF8B); // Port 2 Interrupt Status Flag
 342 SFRX(X_PICTL,    0xDF8C); // Port Interrupt Control
 343 SFRX(X_P1IEN,    0xDF8D); // Port 1 Interrupt Mask
 344 SFRX(X_P0INP,    0xDF8F); // Port 0 Input Mode
 345 SFRX(X_RFIM,     0xDF91); // RF Interrupt Mask
 346 SFRX(X_MPAGE,    0xDF93); // Memory Page Select
 347 SFRX(X_T2CMP,    0xDF94); // Timer 2 Compare Value
 348 SFRX(X_ST0,      0xDF95); // Sleep Timer 0
 349 SFRX(X_ST1,      0xDF96); // Sleep Timer 1
 350 SFRX(X_ST2,      0xDF97); // Sleep Timer 2
 351 SFRX(X_T2PEROF0, 0xDF9C); // Timer 2 Overflow Capture/Compare 0
 352 SFRX(X_T2PEROF1, 0xDF9D); // Timer 2 Overflow Capture/Compare 1
 353 SFRX(X_T2PEROF2, 0xDF9E); // Timer 2 Overflow Capture/Compare 2
 354 SFRX(X_T2OF0,    0xDFA1); // Timer 2 Overflow Count 0
 355 SFRX(X_T2OF1,    0xDFA2); // Timer 2 Overflow Count 1
 356 SFRX(X_T2OF2,    0xDFA3); // Timer 2 Overflow Count 2
 357 SFRX(X_T2CAPLPL, 0xDFA4); // Timer 2 Period Low Byte
 358 SFRX(X_T2CAPHPH, 0xDFA5); // Timer 2 Period High Byte
 359 SFRX(X_T2TLD,    0xDFA6); // Timer 2 Timer Value Low Byte
 360 SFRX(X_T2THD,    0xDFA7); // Timer 2 Timer Value High Byte
 361 SFRX(X_FWT,      0xDFAB); // Flash Write Timing
 362 SFRX(X_FADDRL,   0xDFAC); // Flash Address Low Byte
 363 SFRX(X_FADDRH,   0xDFAD); // Flash Address High Byte
 364 SFRX(X_FCTL,     0xDFAE); // Flash Control
 365 SFRX(X_FWDATA,   0xDFAF); // Flash Write Data
 366 SFRX(X_ENCDI,    0xDFB1); // Encryption Input Data
 367 SFRX(X_ENCDO,    0xDFB2); // Encryption Output Data
 368 SFRX(X_ENCCS,    0xDFB3); // Encryption Control and Status
 369 SFRX(X_ADCCON1,  0xDFB4); // ADC Control 1
 370 SFRX(X_ADCCON2,  0xDFB5); // ADC Control 2
 371 SFRX(X_ADCCON3,  0xDFB6); // ADC Control 3
 372 SFRX(X_ADCL,     0xDFBA); // ADC Data Low
 373 SFRX(X_ADCH,     0xDFBB); // ADC Data High
 374 SFRX(X_RNDL,     0xDFBC); // Random Number Generator Data Low Byte
 375 SFRX(X_RNDH,     0xDFBD); // Random Number Generator Data High Byte
 376 SFRX(X_SLEEP,    0xDFBE); // Sleep Mode Control
 377 SFRX(X_U0DBUF,   0xDFC1); // USART 0 Receive/Transmit Data Buffer
 378 SFRX(X_U0BAUD,   0xDFC2); // USART 0 Baud Rate Control
 379 SFRX(X_T2CNF,    0xDFC3); // Timer 2 Configuration
 380 SFRX(X_U0UCR,    0xDFC4); // USART 0 UART Control
 381 SFRX(X_U0GCR,    0xDFC5); // USART 0 Generic Control
 382 SFRX(X_CLKCON,   0xDFC6); // Clock Control
 383 SFRX(X_MEMCTR,   0xDFC7); // Memory Arbiter Control
 384 SFRX(X_WDCTL,    0xDFC9); // Watchdog Timer Control
 385 SFRX(X_T3CNT,    0xDFCA); // Timer 3 Counter
 386 SFRX(X_T3CTL,    0xDFCB); // Timer 3 Control
 387 SFRX(X_T3CCTL0,  0xDFCC); // Timer 3 Channel 0 Capture/Compare Control
 388 SFRX(X_T3CC0,    0xDFCD); // Timer 3 Channel 0 Capture/Compare Value
 389 SFRX(X_T3CCTL1,  0xDFCE); // Timer 3 Channel 1 Capture/Compare Control
 390 SFRX(X_T3CC1,    0xDFCF); // Timer 3 Channel 1 Capture/Compare Value
 391 SFRX(X_DMAIRQ,   0xDFD1); // DMA Interrupt Flag
 392 SFRX(X_DMA1CFGL, 0xDFD2); // DMA Channel 1-4 Configuration Address Low Byte
 393 SFRX(X_DMA1CFGH, 0xDFD3); // DMA Channel 1-4 Configuration Address High Byte
 394 SFRX(X_DMA0CFGL, 0xDFD4); // DMA Channel 0 Configuration Address Low Byte
 395 SFRX(X_DMA0CFGH, 0xDFD5); // DMA Channel 0 Configuration Address High Byte
 396 SFRX(X_DMAARM,   0xDFD6); // DMA Channel Arm
 397 SFRX(X_DMAREQ,   0xDFD7); // DMA Channel Start Request and Status
 398 SFRX(X_TIMIF,    0xDFD8); // Timers 1/3/4 Interrupt Mask/Flag
 399 SFRX(X_RFD,      0xDFD9); // RF Data
 400 SFRX(X_T1CC0L,   0xDFDA); // Timer 1 Channel 0 Capture/Compare Value Low
 401 SFRX(X_T1CC0H,   0xDFDB); // Timer 1 Channel 0 Capture/Compare Value High
 402 SFRX(X_T1CC1L,   0xDFDC); // Timer 1 Channel 1 Capture/Compare Value Low
 403 SFRX(X_T1CC1H,   0xDFDD); // Timer 1 Channel 1 Capture/Compare Value High
 404 SFRX(X_T1CC2L,   0xDFDE); // Timer 1 Channel 2 Capture/Compare Value Low
 405 SFRX(X_T1CC2H,   0xDFDF); // Timer 1 Channel 2 Capture/Compare Value High
 406 SFRX(X_RFST,     0xDFE1); // RF CSMA-CA / Strobe Processor
 407 SFRX(X_T1CNTL,   0xDFE2); // Timer 1 Counter Low
 408 SFRX(X_T1CNTH,   0xDFE3); // Timer 1 Counter High
 409 SFRX(X_T1CTL,    0xDFE4); // Timer 1 Control and Status
 410 SFRX(X_T1CCTL0,  0xDFE5); // Timer 1 Channel 0 Capture/Compare Control
 411 SFRX(X_T1CCTL1,  0xDFE6); // Timer 1 Channel 1 Capture/Compare Control
 412 SFRX(X_T1CCTL2,  0xDFE7); // Timer 1 Channel 2 Capture/Compare Control
 413 SFRX(X_RFIF,     0xDFE9); // RF Interrupt Flags
 414 SFRX(X_T4CNT,    0xDFEA); // Timer 4 Counter
 415 SFRX(X_T4CTL,    0xDFEB); // Timer 4 Control
 416 SFRX(X_T4CCTL0,  0xDFEC); // Timer 4 Channel 0 Capture/Compare Control
 417 SFRX(X_T4CC0,    0xDFED); // Timer 4 Channel 0 Capture/Compare Value
 418 SFRX(X_T4CCTL1,  0xDFEE); // Timer 4 Channel 1 Capture/Compare Control
 419 SFRX(X_T4CC1,    0xDFEF); // Timer 4 Channel 1 Capture/Compare Value
 420 SFRX(X_PERCFG,   0xDFF1); // Peripheral Control
 421 SFRX(X_ADCCFG,   0xDFF2); // ADC Input Configuration
 422 SFRX(X_P0SEL,    0xDFF3); // Port 0 Function Select
 423 SFRX(X_P1SEL,    0xDFF4); // Port 1 Function Select
 424 SFRX(X_P2SEL,    0xDFF5); // Port 2 Function Select
 425 SFRX(X_P1INP,    0xDFF6); // Port 1 Input Mode
 426 SFRX(X_P2INP,    0xDFF7); // Port 2 Input Mode
 427 SFRX(X_U1CSR,    0xDFF8); // USART 1 Control and Status
 428 SFRX(X_U1DBUF,   0xDFF9); // USART 1 Receive/Transmit Data Buffer
 429 SFRX(X_U1BAUD,   0xDFFA); // USART 1 Baud Rate Control
 430 SFRX(X_U1UCR,    0xDFFB); // USART 1 UART Control
 431 SFRX(X_U1GCR,    0xDFFC); // USART 1 Generic Control
 432 SFRX(X_P0DIR,    0xDFFD); // Port 0 Direction
 433 SFRX(X_P1DIR,    0xDFFE); // Port 1 Direction
 434 SFRX(X_P2DIR,    0xDFFF); // Port 2 Direction
 435
 436 #endif //REG_CC2430_H