sdcc/device/include/mcs51/cc2530.h

   1 /*-------------------------------------------------------------------------
   2    cc2530.h - Register Declarations for Chipcon/Texas Intruments CC2530
   3    (Based on CC253x User's Guide (rev. B) SWRU191B)
   4
   5    Copyright (C) 2011, Zafi Ramarosandratana / zramaro at gmail.com
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef REG_CC2530_H
  31 #define REG_CC2530_H
  32
  33 #include <compiler.h>
  34
  35 // Interrupt Vectors
  36
  37 #define RFERR_VECTOR    0   // RF TX FIFO underflow and RX FIFO overflow.
  38 #define ADC_VECTOR      1   // ADC end of conversion
  39 #define URX0_VECTOR     2   // USART0 RX complete
  40 #define URX1_VECTOR     3   // USART1 RX complete
  41 #define ENC_VECTOR      4   // AES encryption/decryption complete
  42 #define ST_VECTOR       5   // Sleep Timer compare
  43 #define P2INT_VECTOR    6   // Port 2 inputs
  44 #define UTX0_VECTOR     7   // USART0 TX complete
  45 #define DMA_VECTOR      8   // DMA transfer complete
  46 #define T1_VECTOR       9   // Timer 1 (16-bit) capture/compare/overflow
  47 #define T2_VECTOR       10  // Timer 2 (MAC Timer)
  48 #define T3_VECTOR       11  // Timer 3 (8-bit) capture/compare/overflow
  49 #define T4_VECTOR       12  // Timer 4 (8-bit) capture/compare/overflow
  50 #define P0INT_VECTOR    13  // Port 0 inputs
  51 #define UTX1_VECTOR     14  // USART1 TX complete
  52 #define P1INT_VECTOR    15  // Port 1 inputs
  53 #define RF_VECTOR       16  // RF general interrupts
  54 #define WDT_VECTOR      17  // Watchdog overflow in timer mode
  55
  56 // SFR Registers and BITs
  57
  58 SFR(P0,       0x80); // Port 0
  59    SBIT(P0_0,     0x80, 0); // Port 0 bit 0
  60    SBIT(P0_1,     0x80, 1); // Port 0 bit 1
  61    SBIT(P0_2,     0x80, 2); // Port 0 bit 2
  62    SBIT(P0_3,     0x80, 3); // Port 0 bit 3
  63    SBIT(P0_4,     0x80, 4); // Port 0 bit 4
  64    SBIT(P0_5,     0x80, 5); // Port 0 bit 5
  65    SBIT(P0_6,     0x80, 6); // Port 0 bit 6
  66    SBIT(P0_7,     0x80, 7); // Port 0 bit 7
  67 SFR(SP,       0x81); // Stack Pointer
  68 SFR(DPL0,     0x82); // Data Pointer 0 Low Byte
  69 SFR(DPH0,     0x83); // Data Pointer 0 High Byte
  70 SFR(DPL1,     0x84); // Data Pointer 1 Low Byte
  71 SFR(DPH1,     0x85); // Data Pointer 1 High Byte
  72 SFR(U0CSR,    0x86); // USART 0 Control and Status
  73 SFR(PCON,     0x87); // Power Mode Control
  74 SFR(TCON,     0x88); // Interrupt Flags
  75    SBIT(IT0,      0x88, 0); // reserved (must always be set to 1)
  76    SBIT(RFERRIF,  0x88, 1); // RF TX/RX FIFO interrupt flag
  77    SBIT(IT1,      0x88, 2); // reserved (must always be set to 1)
  78    SBIT(URX0IF,   0x88, 3); // USART0 RX Interrupt Flag
  79    SBIT(ADCIF,    0x88, 5); // ADC Interrupt Flag
  80    SBIT(URX1IF,   0x88, 7); // USART1 RX Interrupt Flag
  81 SFR(P0IFG,    0x89); // Port 0 Interrupt Status Flag
  82 SFR(P1IFG,    0x8A); // Port 1 Interrupt Status Flag
  83 SFR(P2IFG,    0x8B); // Port 2 Interrupt Status Flag
  84 SFR(PICTL,    0x8C); // Port Interrupt Control
  85 SFR(P1IEN,    0x8D); // Port 1 Interrupt Mask
  86 SFR(P0INP,    0x8F); // Port 0 Input Mode
  87 SFR(P1,       0x90); // Port 1
  88    SBIT(P1_0,     0x90, 0); // Port 1 bit 0
  89    SBIT(P1_1,     0x90, 1); // Port 1 bit 1
  90    SBIT(P1_2,     0x90, 2); // Port 1 bit 2
  91    SBIT(P1_3,     0x90, 3); // Port 1 bit 3
  92    SBIT(P1_4,     0x90, 4); // Port 1 bit 4
  93    SBIT(P1_5,     0x90, 5); // Port 1 bit 5
  94    SBIT(P1_6,     0x90, 6); // Port 1 bit 6
  95    SBIT(P1_7,     0x90, 7); // Port 1 bit 7
  96 SFR(RFIRQF1,  0x91); // RF Interrupt Flags MSB
  97 SFR(DPS,      0x92); // Data Pointer Select
  98 SFR(MPAGE,    0x93); // Memory Page Select
  99 SFR(_XPAGE,   0x93); // XDATA/PDATA page alias for SDCC
 100 SFR(T2CTRL,   0x94); // Timer 2 Control
 101 SFR(ST0,      0x95); // Sleep Timer 0
 102 SFR(ST1,      0x96); // Sleep Timer 1
 103 SFR(ST2,      0x97); // Sleep Timer 2
 104 SFR(S0CON,    0x98); // Interrupt Flags 2
 105    SBIT(ENCIF_0,  0x98, 0); // AES Interrupt Flag 0
 106    SBIT(ENCIF_1,  0x98, 1); // AES Interrupt Flag 1
 107 SFR(IEN2,     0x9A); // Interrupt Enable 2
 108 SFR(S1CON,    0x9B); // Interrupt Flags 3
 109 SFR(T2EVTCFG, 0x9C); // Timer 2 Event Configuration
 110 SFR(SLEEPSTA, 0x9D); // Sleep Mode Control Status
 111 SFR(CLKCONSTA,0x9E); // Clock Control Status
 112 SFR(PSBANK,   0x9F); // Identifier Name used by the trampoline __sdcc_banked_call
 113 SFR(FMAP,     0x9F); // Flash Memory Bank Mapping
 114 SFR(P2,       0xA0); // Port 2
 115    SBIT(P2_0,     0xA0, 0); // Port 2 bit 0
 116    SBIT(P2_1,     0xA0, 1); // Port 2 bit 1
 117    SBIT(P2_2,     0xA0, 2); // Port 2 bit 2
 118    SBIT(P2_3,     0xA0, 3); // Port 2 bit 3
 119    SBIT(P2_4,     0xA0, 4); // Port 2 bit 4
 120    SBIT(P2_5,     0xA0, 5); // Port 2 bit 5
 121    SBIT(P2_6,     0xA0, 6); // Port 2 bit 6
 122    SBIT(P2_7,     0xA0, 7); // Port 2 bit 7
 123 SFR(T2IRQF,   0xA1); // Timer 2 Interrupt Flags
 124 SFR(T2M0,     0xA2); // Timer 2 Multiplexed Register 0
 125 SFR(T2M1,     0xA3); // Timer 2 Multiplexed Rgeister 1
 126 SFR(T2MOVF0,  0xA4); // Timer 2 Multiplexed Overflow Register 0
 127 SFR(T2MOVF1,  0xA5); // Timer 2 Multiplexed Overflow Register 1
 128 SFR(T2MOVF2,  0xA6); // Timer 2 Multiplexed Overflow Register 2
 129 SFR(T2IRQM,   0xA7); // Timer 2 Interrupt Mask
 130 SFR(IEN0,     0xA8); // Interrupt Enable 0
 131    SBIT(RFERRIE,  0xA8, 0); // RF TX/RX FIFO interrupt Enable
 132    SBIT(ADCIE,    0xA8, 1); // ADC Interrupt Enable
 133    SBIT(URX0IE,   0xA8, 2); // USART0 RX Interrupt Enable
 134    SBIT(URX1IE,   0xA8, 3); // USART1 RX Interrupt Enable
 135    SBIT(ENCIE,    0xA8, 4); // AES Encryption/Decryption Interrupt Enable
 136    SBIT(STIE,     0xA8, 5); // Sleep Timer Interrupt Enable
 137    SBIT(EA,       0xA8, 7); // Global Interrupt Enable
 138 SFR(IP0,      0xA9); // Interrupt Priority 0
 139 SFR(P0IEN,    0xAB); // Port 0 Interrupt Mask
 140 SFR(P2IEN,    0xAC); // Port 2 Interrupt Mask
 141 SFR(STLOAD,   0xAD); // Sleep Timer Load Status
 142 SFR(PMUX,     0xAE); // Power Down Signal Mux
 143 SFR(T1STAT,   0xAF); // Timer 1 Status
 144 SFR(ENCDI,    0xB1); // Encryption Input Data
 145 SFR(ENCDO,    0xB2); // Encryption Output Data
 146 SFR(ENCCS,    0xB3); // Encryption Control and Status
 147 SFR(ADCCON1,  0xB4); // ADC Control 1
 148 SFR(ADCCON2,  0xB5); // ADC Control 2
 149 SFR(ADCCON3,  0xB6); // ADC Control 3
 150 SFR(IEN1,     0xB8); // Interrupt Enable 1
 151    SBIT(DMAIE,    0xB8, 0); // DMA Transfer Interrupt Enable
 152    SBIT(T1IE,     0xB8, 1); // Timer 1 Interrupt Enable
 153    SBIT(T2IE,     0xB8, 2); // Timer 2 Interrupt Enable
 154    SBIT(T3IE,     0xB8, 3); // Timer 3 Interrupt Enable
 155    SBIT(T4IE,     0xB8, 4); // Timer 4 Interrupt Enable
 156    SBIT(P0IE,     0xB8, 5); // Port 0 Interrupt Enable
 157 SFR(IP1,      0xB9); // Interrupt Priority 1
 158 SFR(ADCL,     0xBA); // ADC Data Low
 159 SFR(ADCH,     0xBB); // ADC Data High
 160 SFR(RNDL,     0xBC); // Random Number Generator Data Low Byte
 161 SFR(RNDH,     0xBD); // Random Number Generator Data High Byte
 162 SFR(SLEEPCMD, 0xBE); // Sleep Mode Control Command
 163 SFR(RFERRF,   0xBF); // RF Error Interrupt Flags
 164 SFR(IRCON,    0xC0); // Interrupt Flags 4
 165    SBIT(DMAIF,    0xC0, 0); // DMA Complete Interrupt Flag
 166    SBIT(T1IF,     0xC0, 1); // Timer 1 Interrupt Flag
 167    SBIT(T2IF,     0xC0, 2); // Timer 2 Interrupt Flag
 168    SBIT(T3IF,     0xC0, 3); // Timer 3 Interrupt Flag
 169    SBIT(T4IF,     0xC0, 4); // Timer 4 Interrupt Flag
 170    SBIT(P0IF,     0xC0, 5); // Port 0 Interrupt Flag
 171    SBIT(STIF,     0xC0, 7); // Sleep Timer Interrupt Flag
 172 SFR(U0DBUF,   0xC1); // USART 0 Receive/Transmit Data Buffer
 173 SFR(U0BAUD,   0xC2); // USART 0 Baud Rate Control
 174 SFR(T2MSEL,   0xC3); // Timer 2 Multiplex Select
 175 SFR(U0UCR,    0xC4); // USART 0 UART Control
 176 SFR(U0GCR,    0xC5); // USART 0 Generic Control
 177 SFR(CLKCONCMD,0xC6); // Clock Control Command
 178 SFR(MEMCTR,   0xC7); // Memory Arbitrer Control
 179 SFR(WDCTL,    0xC9); // Watchdog Timer Control
 180 SFR(T3CNT,    0xCA); // Timer 3 Counter
 181 SFR(T3CTL,    0xCB); // Timer 3 Control
 182 SFR(T3CCTL0,  0xCC); // Timer 3 Channel 0 Capture/Compare Control
 183 SFR(T3CC0,    0xCD); // Timer 3 Channel 0 Capture/Compare Value
 184 SFR(T3CCTL1,  0xCE); // Timer 3 Channel 1 Capture/Compare Control
 185 SFR(T3CC1,    0xCF); // Timer 3 Channel 1 Capture/Compare Value
 186 SFR(PSW,      0xD0); // Program Status Word
 187    SBIT(P,        0xD0, 0); // Parity Flag
 188    SBIT(F1,       0xD0, 1); // User-Defined Flag
 189    SBIT(OV,       0xD0, 2); // Overflow Flag
 190    SBIT(RS0,      0xD0, 3); // Register Bank Select 0
 191    SBIT(RS1,      0xD0, 4); // Register Bank Select 1
 192    SBIT(F0,       0xD0, 5); // User-Defined Flag
 193    SBIT(AC,       0xD0, 6); // Auxiliary Carry Flag
 194    SBIT(CY,       0xD0, 7); // Carry Flag
 195 SFR(DMAIRQ,   0xD1); // DMA Interrupt Flag
 196 SFR(DMA1CFGL, 0xD2); // DMA Channel 1-4 Configuration Address Low Byte
 197 SFR(DMA1CFGH, 0xD3); // DMA Channel 1-4 Configuration Address High Byte
 198 SFR(DMA0CFGL, 0xD4); // DMA Channel 0 Configuration Address Low Byte
 199 SFR(DMA0CFGH, 0xD5); // DMA Channel 0 Configuration Address High Byte
 200 SFR(DMAARM,   0xD6); // DMA Channel Arm
 201 SFR(DMAREQ,   0xD7); // DMA Channel Start Request and Status
 202 SFR(TIMIF,    0xD8); // Timers 1/3/4 Interrupt Mask/Flag
 203    SBIT(T3OVFIF,  0xD8, 0); // Timer 3 overflow interrupt flag 0:no pending 1:pending
 204    SBIT(T3CH0IF,  0xD8, 1); // Timer 3 channel 0 interrupt flag 0:no pending 1:pending
 205    SBIT(T3CH1IF,  0xD8, 2); // Timer 3 channel 1 interrupt flag 0:no pending 1:pending
 206    SBIT(T4OVFIF,  0xD8, 3); // Timer 4 overflow interrupt flag 0:no pending 1:pending
 207    SBIT(T4CH0IF,  0xD8, 4); // Timer 4 channel 0 interrupt flag 0:no pending 1:pending
 208    SBIT(T4CH1IF,  0xD8, 5); // Timer 4 channel 1 interrupt flag 0:no pending 1:pending
 209    SBIT(OVFIM,    0xD8, 6); // Timer 1 overflow interrupt mask
 210 SFR(RFD,      0xD9); // RF Data
 211 SFR(T1CC0L,   0xDA); // Timer 1 Channel 0 Capture/Compare Value Low
 212 SFR(T1CC0H,   0xDB); // Timer 1 Channel 0 Capture/Compare Value High
 213 SFR(T1CC1L,   0xDC); // Timer 1 Channel 1 Capture/Compare Value Low
 214 SFR(T1CC1H,   0xDD); // Timer 1 Channel 1 Capture/Compare Value High
 215 SFR(T1CC2L,   0xDE); // Timer 1 Channel 2 Capture/Compare Value Low
 216 SFR(T1CC2H,   0xDF); // Timer 1 Channel 2 Capture/Compare Value High
 217 SFR(ACC,      0xE0); // Accumulator
 218    SBIT(ACC_0,    0xE0, 0); // Accumulator bit 0
 219    SBIT(ACC_1,    0xE0, 1); // Accumulator bit 1
 220    SBIT(ACC_2,    0xE0, 2); // Accumulator bit 2
 221    SBIT(ACC_3,    0xE0, 3); // Accumulator bit 3
 222    SBIT(ACC_4,    0xE0, 4); // Accumulator bit 4
 223    SBIT(ACC_5,    0xE0, 5); // Accumulator bit 5
 224    SBIT(ACC_6,    0xE0, 6); // Accumulator bit 6
 225    SBIT(ACC_7,    0xE0, 7); // Accumulator bit 7
 226 SFR(RFST,     0xE1); // RF CSMA-CA / Strobe Processor
 227 SFR(T1CNTL,   0xE2); // Timer 1 Counter Low
 228 SFR(T1CNTH,   0xE3); // Timer 1 Counter High
 229 SFR(T1CTL,    0xE4); // Timer 1 Control and Status
 230 SFR(T1CCTL0,  0xE5); // Timer 1 Channel 0 Capture/Compare Control
 231 SFR(T1CCTL1,  0xE6); // Timer 1 Channel 1 Capture/Compare Control
 232 SFR(T1CCTL2,  0xE7); // Timer 1 Channel 2 Capture/Compare Control
 233 SFR(IRCON2,   0xE8); // Interrupt Flags 5
 234    SBIT(P2IF,     0xE8, 0); // Port 2 Interrupt Flag
 235    SBIT(UTX0IF,   0xE8, 1); // USART0 TX Interrupt Flag
 236    SBIT(UTX1IF,   0xE8, 2); // USART1 TX Interrupt Flag
 237    SBIT(P1IF,     0xE8, 3); // Port 1 Interrupt Flag
 238    SBIT(WDTIF,    0xE8, 4); // Watchdog Timer Interrupt Flag
 239 SFR(RFIRQF0,  0xE9); // RF Interrupt Flags LSB
 240 SFR(T4CNT,    0xEA); // Timer 4 Counter
 241 SFR(T4CTL,    0xEB); // Timer 4 Control
 242 SFR(T4CCTL0,  0xEC); // Timer 4 Channel 0 Capture/Compare Control
 243 SFR(T4CC0,    0xED); // Timer 4 Channel 0 Capture/Compare Value
 244 SFR(T4CCTL1,  0xEE); // Timer 4 Channel 1 Capture/Compare Control
 245 SFR(T4CC1,    0xEF); // Timer 4 Channel 1 Capture/Compare Value
 246 SFR(B,        0xF0); // B Register
 247    SBIT(B_0,      0xF0, 0); // Register B bit 0
 248    SBIT(B_1,      0xF0, 1); // Register B bit 1
 249    SBIT(B_2,      0xF0, 2); // Register B bit 2
 250    SBIT(B_3,      0xF0, 3); // Register B bit 3
 251    SBIT(B_4,      0xF0, 4); // Register B bit 4
 252    SBIT(B_5,      0xF0, 5); // Register B bit 5
 253    SBIT(B_6,      0xF0, 6); // Register B bit 6
 254    SBIT(B_7,      0xF0, 7); // Register B bit 7
 255 SFR(PERCFG,   0xF1); // Peripheral I/O Control
 256 SFR(APCFG,    0xF2); // Analog Peripheral I/O Configuration
 257 SFR(P0SEL,    0xF3); // Port 0 Function Select
 258 SFR(P1SEL,    0xF4); // Port 1 Function Select
 259 SFR(P2SEL,    0xF5); // Port 2 Function Select
 260 SFR(P1INP,    0xF6); // Port 1 Input Mode
 261 SFR(P2INP,    0xF7); // Port 2 Input Mode
 262 SFR(U1CSR,    0xF8); // USART 1 Control and Status
 263    SBIT(ACTIVE,   0xF8, 0); // USART transmit/receive active status 0:idle 1:busy
 264    SBIT(TX_BYTE,  0xF8, 1); // Transmit byte status 0:Byte not transmitted 1:Last byte transmitted
 265    SBIT(RX_BYTE,  0xF8, 2); // Receive byte status 0:No byte received 1:Received byte ready
 266    SBIT(ERR,      0xF8, 3); // UART parity error status 0:No error 1:parity error
 267    SBIT(FE,       0xF8, 4); // UART framing error status 0:No error 1:incorrect stop bit level
 268    SBIT(SLAVE,    0xF8, 5); // SPI master or slave mode select 0:master 1:slave
 269    SBIT(RE,       0xF8, 6); // UART receiver enable 0:disabled 1:enabled
 270    SBIT(MODE,     0xF8, 7); // USART mode select 0:SPI 1:UART
 271 SFR(U1DBUF,   0xF9); // USART 1 Receive/Transmit Data Buffer
 272 SFR(U1BAUD,   0xFA); // USART 1 Baud Rate Control
 273 SFR(U1UCR,    0xFB); // USART 1 UART Control
 274 SFR(U1GCR,    0xFC); // USART 1 Generic Control
 275 SFR(P0DIR,    0xFD); // Port 0 Direction
 276 SFR(P1DIR,    0xFE); // Port 1 Direction
 277 SFR(P2DIR,    0xFF); // Port 2 Direction
 278 //
 279 //// From Table 2-2 : Overview of XREG Registers
 280 //
 281 SFRX(I2CCFG,     0x6230); // I2C control
 282 SFRX(I2CSTAT,    0x6231); // I2C status
 283 SFRX(I2CDATA,    0x6232); // I2C data
 284 SFRX(I2CADDR,    0x6233); // I2C own slave address
 285 SFRX(I2CWC,      0x6234); // Wrapper control
 286 SFRX(I2CIO,      0x6235); // GPIO
 287 SFRX(OBSSEL0,    0x6243); // Observation output control register 0
 288 SFRX(OBSSEL1,    0x6244); // Observation output control register 1
 289 SFRX(OBSSEL2,    0x6245); // Observation output control register 2
 290 SFRX(OBSSEL3,    0x6246); // Observation output control register 3
 291 SFRX(OBSSEL4,    0x6247); // Observation output control register 4
 292 SFRX(OBSSEL5,    0x6248); // Observation output control register 5
 293 SFRX(CHVER,      0x6249); // Chip version
 294 SFRX(CHIPID,     0x624A); // Chip identification
 295 SFRX(TESTREG0,   0x624B); // Test register 0, cannot use TR0 name from the datasheet due to TR0 (TCON.4) redefinition
 296 SFRX(DBGDATA,    0x6260); // Debug interface write data
 297 SFRX(SRCRC,      0x6262); // Sleep reset CRC
 298 SFRX(BATTMON,    0x6264); // Battery monitor
 299 SFRX(IVCTRL,     0x6265); // Analog control register
 300 SFRX(FCTL,       0x6270); // Flash control
 301 SFRX(FADDRL,     0x6271); // Flash address low
 302 SFRX(FADDRH,     0x6272); // Flash address high
 303 SFRX(FWDATA,     0x6273); // Flash write data
 304 SFRX(CHIPINFO0,  0x6276); // Chip information byte 0
 305 SFRX(CHIPINFO1,  0x6277); // Chip information byte 1
 306 SFRX(IRCTL,      0x6281); // Timer 1 IR generation control
 307 SFRX(CLD,        0x6290); // Clock-loss detection
 308 SFRX(X_T1CCTL0,    0x62A0); // Timer 1 channel 0 capture/compare control (additional XREG mapping of SFR register)
 309 SFRX(X_T1CCTL1,    0x62A1); // Timer 1 channel 1 capture/compare control (additional XREG mapping of SFR register)
 310 SFRX(X_T1CCTL2,    0x62A2); // Timer 1 channel 2 capture/compare control (additional XREG mapping of SFR register)
 311 SFRX(T1CCTL3,    0x62A3); // Timer 1 channel 3 capture/compare control
 312 SFRX(T1CCTL4,    0x62A4); // Timer 1 channel 4 capture/compare control
 313 SFRX(X_T1CC0L,     0x62A6); // Timer 1 channel 0 capture/compare value low (additional XREG mapping of SFR register)
 314 SFRX(X_T1CC0H,     0x62A7); // Timer 1 channel 0 capture/compare value high (additional XREG mapping of SFR register)
 315 SFRX(X_T1CC1L,     0x62A8); // Timer 1 channel 1 capture/compare value low (additional XREG mapping of SFR register)
 316 SFRX(X_T1CC1H,     0x62A9); // Timer 1 channel 1 capture/compare value high (additional XREG mapping of SFR register)
 317 SFRX(X_T1CC2L,     0x62AA); // Timer 1 channel 2 capture/compare value low (additional XREG mapping of SFR register)
 318 SFRX(X_T1CC2H,     0x62AB); // Timer 1 channel 2 capture/compare value high (additional XREG mapping of SFR register)
 319 SFRX(T1CC3L,     0x62AC); // Timer 1 channel 3 capture/compare value low
 320 SFRX(T1CC3H,     0x62AD); // Timer 1 channel 3 capture/compare value high
 321 SFRX(T1CC4L,     0x62AE); // Timer 1 channel 4 capture/compare value low
 322 SFRX(T1CC4H,     0x62AF); // Timer 1 channel 4 capture/compare value high
 323 SFRX(STCC,       0x62B0); // Sleep Timer capture control
 324 SFRX(STCS,       0x62B1); // Sleep Timer capture status
 325 SFRX(STCV0,      0x62B2); // Sleep Timer capture value byte 0
 326 SFRX(STCV1,      0x62B3); // Sleep Timer capture value byte 1
 327 SFRX(STCV2,      0x62B4); // Sleep Timer capture value byte 2
 328 SFRX(OPAMPC,     0x62C0); // Operational amplifier control
 329 SFRX(OPAMPS,     0x62C1); // Operational amplifier status
 330 SFRX(CMPCTL,     0x62D0); // Analog comparator control and status
 331 //
 332 //// From Section 21.12 : USB Registers
 333 //
 334 SFRX(USBADDR,    0x6200); // Function Address
 335 SFRX(USBPOW,     0x6201); // Power/Control Register
 336 SFRX(USBIIF,     0x6202); // IN Endpoints and EP0 Interrupt Flags
 337 SFRX(USBOIF,     0x6204); // OUT-Endpoint Interrupt Flags
 338 SFRX(USBCIF,     0x6206); // Common USB Interrupt Flags
 339 SFRX(USBIIE,     0x6207); // IN Endpoints and EP0 Interrupt-Enable Mask
 340 SFRX(USBOIE,     0x6209); // Out Endpoints Interrupt Enable Mask
 341 SFRX(USBCIE,     0x620B); // Common USB Interrupt-Enable Mask
 342 SFRX(USBFRML,    0x620C); // Current Frame Number (Low Byte)
 343 SFRX(USBFRMH,    0x620D); // Current Frame Number (High Byte)
 344 SFRX(USBINDEX,   0x620E); // Current-Endpoint Index Register
 345 SFRX(USBCTRL,    0x620F); // USB Control Register
 346 SFRX(USBMAXI,    0x6210); // Max. Packet Size for IN Endpoint{1-5}
 347 SFRX(USBCS0,     0x6211); // EP0 Control and Status (USBINDEX = 0)
 348 SFRX(USBCSIL,    0x6211); // IN EP{1-5} Control and Status, Low
 349 SFRX(USBCSIH,    0x6212); // IN EP{1-5} Control and Status, High
 350 SFRX(USBMAXO,    0x6213); // Max. Packet Size for OUT EP{1-5}
 351 SFRX(USBCSOL,    0x6214); // OUT EP{1-5} Control and Status, Low
 352 SFRX(USBCSOH,    0x6215); // OUT EP{1-5} Control and Status, High
 353 SFRX(USBCNT0,    0x6216); // Number of Received Bytes in EP0 FIFO (USBINDEX = 0)
 354 SFRX(USBCNTL,    0x6216); // Number of Bytes in EP{1-5} OUT FIFO, Low
 355 SFRX(USBCNTH,    0x6217); // Number of Bytes in EP{1-5} OUT FIFO, High
 356 SFRX(USBF0,      0x6220); // Endpoint-0 FIFO
 357 SFRX(USBF1,      0x6222); // Endpoint-1 FIFO
 358 SFRX(USBF2,      0x6224); // Endpoint-2 FIFO
 359 SFRX(USBF3,      0x6226); // Endpoint-3 FIFO
 360 SFRX(USBF4,      0x6228); // Endpoint-4 FIFO
 361 SFRX(USBF5,      0x622A); // Endpoint-5 FIFO
 362 //
 363 //// From Table 23.1 : Frame Filtering
 364 //
 365 SFRX(SHORTADDRH, 0x6174); // Short Address High Byte
 366 SFRX(SHORTADDRL, 0x6175); // Short Address Low Byte
 367 SFRX(PANIDH,     0x6172); // PAN ID High Byte
 368 SFRX(PANIDL,     0x6173); // PAN ID Low Byte
 369 SFRX(IEEE_ADDR,  0x616A); // Extended Address MSB
 370
 371 //
 372 //// From Table 23-5 : CC253x Radio Register Overview
 373 //
 374 SFRX(FRMFILT0,   0x6180); // Frame Filtering
 375 SFRX(FRMFILT1,   0x6181); // Frame Filtering
 376 SFRX(SRCMATCH,   0x6182); // Source Address Matching and Pending Bits
 377 SFRX(SRCSHORTEN0,0x6183); // Short Address Matching
 378 SFRX(SRCSHORTEN1,0x6184); // Short Address Matching
 379 SFRX(SRCSHORTEN2,0x6185); // Short Address Matching
 380 SFRX(SRCEXTEN0,  0x6186); // Extended Address Matching
 381 SFRX(SRCEXTEN1,  0x6187); // Extended Address Matching
 382 SFRX(SRCEXTEN2,  0x6188); // Extended Address Matching
 383 SFRX(FRMCTRL0,   0x6189); // Frame Handling
 384 SFRX(FRMCTRL1,   0x618A); // Frame Handling
 385 SFRX(RXENABLE,   0x618B); // RX Enabling
 386 SFRX(RXMASKSET,  0x618C); // RX Enabling
 387 SFRX(RXMASKCLR,  0x618D); // RX Disabling
 388 SFRX(FREQTUNE,   0x618E); // Crystal Oscillator Frequency Tuning
 389 SFRX(FREQCTRL,   0x618F); // Controls the RF Frequency
 390 SFRX(TXPOWER,    0x6190); // Controls the Output Power
 391 SFRX(TXCTRL,     0x6191); // Controls the TX Settings
 392 SFRX(FSMSTAT0,   0x6192); // Radio Status Register
 393 SFRX(FSMSTAT1,   0x6193); // Radio Status Register
 394 SFRX(FIFOPCTRL,  0x6194); // FIFOP Threshold
 395 SFRX(FSMCTRL,    0x6195); // FSM Options
 396 SFRX(CCACTRL0,   0x6196); // CCA Threshold
 397 SFRX(CCACTRL1,   0x6197); // Other CCA Options
 398 SFRX(RSSI,       0x6198); // RSSI Status Register
 399 SFRX(RSSISTAT,   0x6199); // RSSI Valid Status Register
 400 SFRX(RXFIRST,    0x619A); // First Byte in RXFIFO
 401 SFRX(RXFIFOCNT,  0x619B); // Number of Bytes in RXFIFO
 402 SFRX(TXFIFOCNT,  0x619C); // Number of Bytes in TXFIFO
 403 SFRX(RXFIRST_PTR,0x619D); // RXFIFO Pointer
 404 SFRX(RXLAST_PTR, 0x619E); // RXFIFO Pointer
 405 SFRX(RXP1_PTR,   0x619F); // RXFIFO Pointer
 406 SFRX(TXFIRST_PTR,0x61A1); // TXFIFO Pointer
 407 SFRX(TXLAST_PTR, 0x61A2); // TXFIFO Pointer
 408 SFRX(RFIRQM0,    0x61A3); // RF Interrupt Masks
 409 SFRX(RFIRQM1,    0x61A4); // RF Interrupt Masks
 410 SFRX(RFERRM,     0x61A5); // RF Error Interrupt Mask
 411 SFRX(OPAMPMC,    0x61A6); // Operational amplifier mode control
 412 SFRX(RFRND,      0x61A7); // Random Data
 413 SFRX(MDMCTRL0,   0x61A8); // Controls Modem
 414 SFRX(MDMCTRL1,   0x61A9); // Controls Modem
 415 SFRX(FREQEST,    0x61AA); // Estimated RF Frequency Offset
 416 SFRX(RXCTRL,     0x61AB); // Tune Receive Section
 417 SFRX(FSCTRL,     0x61AC); // Tune Frequency Synthesizer
 418 SFRX(FSCAL1,     0x61AE); // Tune Frequency Calibration
 419 SFRX(FSCAL2,     0x61AF); // Tune Frequency Calibration
 420 SFRX(FSCAL3,     0x61B0); // Tune Frequency Calibration
 421 SFRX(AGCCTRL0,   0x61B1); // AGC Dynamic Range Control
 422 SFRX(AGCCTRL1,   0x61B2); // AGC Reference Level
 423 SFRX(AGCCTRL2,   0x61B3); // AGC Gain Override
 424 SFRX(AGCCTRL3,   0x61B4); // AGC Control
 425 SFRX(ADCTEST0,   0x61B5); // ADC Tuning
 426 SFRX(ADCTEST1,   0x61B6); // ADC Tuning
 427 SFRX(ADCTEST2,   0x61B7); // ADC Tuning
 428 SFRX(MDMTEST0,   0x61B8); // Test Register for Modem
 429 SFRX(MDMTEST1,   0x61B9); // Test Register for Modem
 430 SFRX(DACTEST0,   0x61BA); // DAC Override Value
 431 SFRX(DACTEST1,   0x61BB); // DAC Override Value
 432 SFRX(DACTEST2,   0x61BC); // DAC Test Setting
 433 SFRX(ATEST,      0x61BD); // Analog Test Control
 434 SFRX(PTEST0,     0x61BE); // Override Power-Down Register
 435 SFRX(PTEST1,     0x61BF); // Override Power-Down Register
 436 SFRX(CSPPROG0,   0x61C0); // CSP Program 0
 437 SFRX(CSPPROG1,   0x61C1); // CSP Program 1
 438 SFRX(CSPPROG2,   0x61C2); // CSP Program 2
 439 SFRX(CSPPROG3,   0x61C3); // CSP Program 3
 440 SFRX(CSPPROG4,   0x61C4); // CSP Program 4
 441 SFRX(CSPPROG5,   0x61C5); // CSP Program 5
 442 SFRX(CSPPROG6,   0x61C6); // CSP Program 6
 443 SFRX(CSPPROG7,   0x61C7); // CSP Program 7
 444 SFRX(CSPPROG8,   0x61C8); // CSP Program 8
 445 SFRX(CSPPROG9,   0x61C9); // CSP Program 9
 446 SFRX(CSPPROG10,  0x61CA); // CSP Program 10
 447 SFRX(CSPPROG11,  0x61CB); // CSP Program 11
 448 SFRX(CSPPROG12,  0x61CC); // CSP Program 12
 449 SFRX(CSPPROG13,  0x61CD); // CSP Program 13
 450 SFRX(CSPPROG14,  0x61CE); // CSP Program 14
 451 SFRX(CSPPROG15,  0x61CF); // CSP Program 15
 452 SFRX(CSPPROG16,  0x61D0); // CSP Program 16
 453 SFRX(CSPPROG17,  0x61D1); // CSP Program 17
 454 SFRX(CSPPROG18,  0x61D2); // CSP Program 18
 455 SFRX(CSPPROG19,  0x61D3); // CSP Program 19
 456 SFRX(CSPPROG20,  0x61D4); // CSP Program 20
 457 SFRX(CSPPROG21,  0x61D5); // CSP Program 21
 458 SFRX(CSPPROG22,  0x61D6); // CSP Program 22
 459 SFRX(CSPPROG23,  0x61D7); // CSP Program 23
 460 SFRX(CSPCTRL,    0x61E0); // CSP Control Bit
 461 SFRX(CSPSTAT,    0x61E1); // CSP Status Register
 462 SFRX(CSPX,       0x61E2); // CSP X Register
 463 SFRX(CSPY,       0x61E3); // CSP Y Register
 464 SFRX(CSPZ,       0x61E4); // CSP Z Register
 465 SFRX(CSPT,       0x61E5); // CSP T Register
 466 SFRX(RFC_OBS_CTRL0, 0x61EB); // RF Observation Mux Control
 467 SFRX(RFC_OBS_CTRL1, 0x61EC); // RF Observation Mux Control
 468 SFRX(RFC_OBS_CTRL2, 0x61ED); // RF Observation Mux Control
 469 SFRX(TXFILTCFG,  0x61FA); // TX Filter Configuration
 470
 471 #endif //REG_CC2530_H