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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / mcs51reg.h
bloba02233d923e8f6bd26f0c485dea37c46f1b7b1af
1 /*-------------------------------------------------------------------------
2 mcs51reg.h - Register Declarations for the mcs51 compatible
3 microcontrollers
4
5 Copyright (C) 2000, Bela Torok / bela.torok@kssg.ch
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 /*-------------------------------------------------------------------------
31 History:
32 --------
33 Version 1.0 Nov 2, 2000 - B. Torok / bela.torok@kssg.ch
34 Initial release, supported microcontrollers:
35 8051, 8052, Atmel AT89C1051, AT89C2051, AT89C4051,
36 Infineon / Siemens SAB80515, SAB80535, SAB80515A
37
38 Version 1.0.1 (Nov 3, 2000)
39 SAB80515A definitions revised by Michael Schmitt / michael.schmitt@t-online.de
40
41 Version 1.0.2 (Nov 6, 2000)
42 T2CON bug corrected 8052 and SABX microcontrollers have different T2CONs
43 Support for the Atmel AT89C52, AT80LV52, AT89C55, AT80LV55
44 Support for the Dallas DS80C320 and DS80C323
45 B. Torok / bela.torok@kssg.ch
46
47 Version 1.0.3 (Nov 7, 2000)
48 SAB80517 definitions added by Michael Schmitt / michael.schmitt@t-online.de
49 Dallas AT89S53 definitions added by B. Torok / bela.torok@kssg.ch
50 Dallas DS87C520 and DS83C520 definitions added by B. Torok / bela.torok@kssg.ch
51
52 Version 1.0.4 (Nov 9, 2000)
53 To simplify the identication of registers, a large number of definitios
54 were renamed. Long register names now (hopefully) clearly define the
55 function of the registers.
56 Dallas DS89C420 definitions added by B. Torok / bela.torok@kssg.ch
57
58 Version 1.0.5 (Dec 15, 2000)
59 Definitions added: #ifdef MCS51REG_EXTERNAL_ROM
60 #ifdef MCS51REG_EXTERNAL_RAM
61 #ifndef MCS51REG_DISABLE_WARNINGS
62
63
64 Version 1.0.6 (March 10, 2001)
65 Support for the Dallas DS5000 & DS2250
66 Support for the Dallas DS5001 & DS2251
67 Support for the Dallas DS80C390
68 microcontrollers - B. Torok / bela.torok@kssg.ch
69
70 Version 1.0.7 (June 7, 2001)
71 #ifndef MCS51REG_DISABLE_WARNINGS removed
72 #ifdef MCS51REG_DISABLE_WARNINGS added - B. Torok / bela.torok@kssg.ch
73 Support for the Philips P80C552 added - Bernhard Held / Bernhard.Held@otelo-online.de
74
75 Version 1.0.8 (Feb 28, 2002)
76 Dallas DS89C420 definitions corrected by B. Torok / bela.torok@kssg.ch
77 Revised by lanius@ewetel.net
78
79 Version 1.0.9 (Sept 9, 2002)
80 Register declarations for the Atmel T89C51RD2 added by Johannes Hoelzl / johannes.hoelzl@gmx.de
81
82 Version 1.0.10 (Sept 19, 2002)
83 Register declarations for the Philips P89C668 added by Eric Limpens / Eric@limpens.net
84
85 Version 1.0.11 (Sept 19, 2004)
86 Dallas DS5000 MCON Register declarations corrected by Radek Zadera / a2i@swipnet.se
87
88 Version 1.0.12 (March 2, 2005)
89 Infineon SAB80C509 Register declarations added Thomas Boje / thomas@boje.name
90
91 Adding support for additional microcontrollers:
92 -----------------------------------------------
93
94 1. Don't modify this file!!!
95
96 2. Insert your code in a separate file e.g.: mcs51reg_update.h and include
97 this after the #define HEADER_MCS51REG statement in this file
98
99 3. The mcs51reg_update.h file should contain following definitions:
100
101 a. An entry with the inventory of the register set of the
102 microcontroller in the "Describe microcontrollers" section.
103
104 b. If necessary add entry(s) for registers not defined in this file
105
106 c. Define interrupt vectors
107
108 4. Compile a program for the microcontroller using the Preprocessor only, e.g.:,
109 sdcc -E test.c > t.txt
110 and check definitions for validity in the t.txt file.
111
112 5. If everithing seems to be OK send me the mcs51reg_update.h file. --> bela.torok@kssg.ch
113 I'm going to resolve conflicts & verify/merge new definitions to this file.
114
115
116 Microcontroller support:
117
118 Use one of the following options:
119
120 1. use #include <mcs51reg.h> in your program & define MICROCONTROLLER_XXXX in your makefile.
121
122 2. use following definitions prior the
123 #include <mcs51reg.h> line in your program:
124 e.g.:
125 #define MICROCONTROLLER_8052 -> 8052 type microcontroller
126 or
127 #define MICROCONTROLLER_AT89CX051 -> Atmel AT89C1051, AT89C2051 and AT89C4051 microcontrollers
128
129
130 Use only one of the following definitions!!!
131
132 Supported Microcontrollers:
133
134 No definition 8051
135 MICROCONTROLLER_8051 8051
136 MICROCONTROLLER_8052 8052
137 MICROCONTROLLER_AT89CX051 Atmel AT89C1051, AT89C2051 and AT89C4051
138 MICROCONTROLLER_AT89S53 Atmel AT89S53 microcontroller
139 MICROCONTROLLER_AT89X52 Atmel AT89C52 and AT80LV52 microcontrollers
140 MICROCONTROLLER_AT89X55 Atmel AT89C55 and AT80LV55 microcontrollers
141 MICROCONTROLLER_DS5000 Dallas DS5000 & DS2250 microcontroller
142 MICROCONTROLLER_DS5001 Dallas DS5001 & DS2251 microcontroller
143 MICROCONTROLLER_DS80C32X Dallas DS80C320 and DS80C323 microcontrollers
144 MICROCONTROLLER_DS80C390 Dallas DS80C390 microcontroller
145 MICROCONTROLLER_DS89C420 Dallas DS89C420 microcontroller
146 MICROCONTROLLER_DS8XC520 Dallas DS87C520 and DS83C520 microcontrollers
147 MICROCONTROLLER_P80C552 Philips P80C552
148 MICROCONTROLLER_P89C668 Philips P89C668
149 MICROCONTROLLER_SAB80C509 Infineon / Siemens SAB80C509
150 MICROCONTROLLER_SAB80515 Infineon / Siemens SAB80515 & SAB80535
151 MICROCONTROLLER_SAB80515A Infineon / Siemens SAB80515A
152 MICROCONTROLLER_SAB80517 Infineon / Siemens SAB80517
153 MICROCONTROLLER_T89C51RD2 Atmel T89C51RD2
154
155 Additional definitions (use them prior the #include mcs51reg.h statement):
156
157 Ports P0 & P2 are not available if external ROM used.
158 Use statement "#define MCS51REG_EXTERNAL_ROM" to undefine P0 & P2.
159
160 Ports P0, P2, P3_6, WR, P3_7 & RD are not available if external RAM is used.
161 Use statement "#define MCS51REG_EXTERNAL_RAM" to undefine P0, P2,
162 P3_6, WR, P3_7 & RD.
163
164 #define MCS51REG_ENABLE_WARNINGS -> enable warnings
165
166 -----------------------------------------------------------------------*/
167
168
169 #ifndef HEADER_MCS51REG
170 #define HEADER_MCS51REG
171
172 #include <compiler.h>
173
174 ///////////////////////////////////////////////////////
175 /// Insert header here (for developers only) ///
176 /// remove "//" from the begining of the next line ///
177 //#include "mcs51reg_update.h" ///
178 ///////////////////////////////////////////////////////
179
180 //////////////////////////////////
181 /// Describe microcontrollers ///
182 /// (inventory of registers) ///
183 //////////////////////////////////
184
185 // definitions for the 8051
186 #ifdef MICROCONTROLLER_8051
187 #ifdef MICROCONTROLLER_DEFINED
188 #define MCS51REG_ERROR
189 #endif
190 #ifndef MICROCONTROLLER_DEFINED
191 #define MICROCONTROLLER_DEFINED
192 #endif
193 #ifdef MCS51REG_ENABLE_WARNINGS
194 #warning Selected HW: 8051
195 #endif
196 #define P0
197 #define SP
198 #define DPL
199 #define DPH
200 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
201 #define TCON
202 #define TMOD
203 #define TL0
204 #define TL1
205 #define TH0
206 #define TH1
207 #define P1
208 #define SCON
209 #define SBUF
210 #define P2
211 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
212 #define P3
213 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
214 #define PSW
215 #define ACC
216 #define B
217 #endif
218 // end of definitions for the 8051
219
220
221 // definitions for the 8052 microcontroller
222 #ifdef MICROCONTROLLER_8052
223 #ifdef MICROCONTROLLER_DEFINED
224 #define MCS51REG_ERROR
225 #endif
226 #ifndef MICROCONTROLLER_DEFINED
227 #define MICROCONTROLLER_DEFINED
228 #endif
229 #ifdef MCS51REG_ENABLE_WARNINGS
230 #warning Selected HW: 8052
231 #endif
232 // 8051 register set
233 #define P0
234 #define SP
235 #define DPL
236 #define DPH
237 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
238 #define TCON
239 #define TMOD
240 #define TL0
241 #define TL1
242 #define TH0
243 #define TH1
244 #define P1
245 #define SCON
246 #define SBUF
247 #define P2
248 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
249 #define P3
250 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
251 #define PSW
252 #define ACC
253 #define B
254 // 8052 specific registers
255 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
256 #define RCAP2L
257 #define RCAP2H
258 #define TL2
259 #define TH2
260 #endif
261 // end of definitions for the 8052 microcontroller
262
263
264 // definitionsons for the Atmel
265 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
266 #ifdef MICROCONTROLLER_AT89CX051
267 #ifdef MICROCONTROLLER_DEFINED
268 #define MCS51REG_ERROR
269 #endif
270 #ifndef MICROCONTROLLER_DEFINED
271 #define MICROCONTROLLER_DEFINED
272 #endif
273 #ifdef MCS51REG_ENABLE_WARNINGS
274 #warning Selected HW: Atmel AT89Cx051
275 #endif
276 // 8051 register set without P0 & P2
277 #define SP
278 #define DPL
279 #define DPH
280 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
281 #define TCON
282 #define TMOD
283 #define TL0
284 #define TL1
285 #define TH0
286 #define TH1
287 #define P1
288 #define SCON
289 #define SBUF
290 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
291 #define P3
292 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
293 #define PSW
294 #define ACC
295 #define B
296 #endif
297 // end of definitionsons for the Atmel
298 // AT89C1051, AT89C2051 and AT89C4051 microcontrollers
299
300
301 // definitions for the Atmel AT89S53
302 #ifdef MICROCONTROLLER_AT89S53
303 #ifdef MICROCONTROLLER_DEFINED
304 #define MCS51REG_ERROR
305 #endif
306 #ifndef MICROCONTROLLER_DEFINED
307 #define MICROCONTROLLER_DEFINED
308 #endif
309 #ifdef MCS51REG_ENABLE_WARNINGS
310 #warning Selected HW: AT89S53
311 #endif
312 // 8051 register set
313 #define P0
314 #define SP
315 #define DPL
316 #define DPH
317 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
318 #define TCON
319 #define TMOD
320 #define TL0
321 #define TL1
322 #define TH0
323 #define TH1
324 #define P1
325 #define SCON
326 #define SBUF
327 #define P2
328 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
329 #define P3
330 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
331 #define PSW
332 #define ACC
333 #define B
334 // 8052 specific registers
335 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
336 #define RCAP2L
337 #define RCAP2H
338 #define TL2
339 #define TH2
340 // AT89S53 specific register
341 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
342 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
343 #define SPCR
344 #define SPDR
345 #define SPSR
346 #define WCOM
347 #define DPL1
348 #define DPH1
349 #endif
350 // end of definitions for the Atmel AT89S53 microcontroller
351
352
353 // definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
354 #ifdef MICROCONTROLLER_AT89X52
355 #ifdef MICROCONTROLLER_DEFINED
356 #define MCS51REG_ERROR
357 #endif
358 #ifndef MICROCONTROLLER_DEFINED
359 #define MICROCONTROLLER_DEFINED
360 #endif
361 #ifdef MCS51REG_ENABLE_WARNINGS
362 #warning Selected HW: AT89C52 or AT89LV52
363 #endif
364 // 8051 register set
365 #define P0
366 #define SP
367 #define DPL
368 #define DPH
369 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
370 #define TCON
371 #define TMOD
372 #define TL0
373 #define TL1
374 #define TH0
375 #define TH1
376 #define P1
377 #define SCON
378 #define SBUF
379 #define P2
380 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
381 #define P3
382 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
383 #define PSW
384 #define ACC
385 #define B
386 // 8052 specific registers
387 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
388 #define RCAP2L
389 #define RCAP2H
390 #define TL2
391 #define TH2
392 // AT89X55 specific register
393 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
394 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
395 #endif
396 // end of definitions for the Atmel AT89C52 and AT89LV52 microcontrollers
397
398
399 // definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
400 #ifdef MICROCONTROLLER_AT89X55
401 #ifdef MICROCONTROLLER_DEFINED
402 #define MCS51REG_ERROR
403 #endif
404 #ifndef MICROCONTROLLER_DEFINED
405 #define MICROCONTROLLER_DEFINED
406 #endif
407 #ifdef MCS51REG_ENABLE_WARNINGS
408 #warning Selected HW: AT89C55 or AT89LV55
409 #endif
410 // 8051 register set
411 #define P0
412 #define SP
413 #define DPL
414 #define DPH
415 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
416 #define TCON
417 #define TMOD
418 #define TL0
419 #define TL1
420 #define TH0
421 #define TH1
422 #define P1
423 #define SCON
424 #define SBUF
425 #define P2
426 #define IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
427 #define P3
428 #define IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
429 #define PSW
430 #define ACC
431 #define B
432 // 8052 specific registers
433 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
434 #define RCAP2L
435 #define RCAP2H
436 #define TL2
437 #define TH2
438 // AT89X55 specific register
439 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
440 #define P1_EXT__x__x__x__x__x__x__T2EX__T2
441 #endif
442 // end of definitions for the Atmel AT89C55 and AT89LV55 microcontrollers
443
444
445 // definitions for the Dallas DS5000
446 #ifdef MICROCONTROLLER_DS5000
447 #ifdef MICROCONTROLLER_DEFINED
448 #define MCS51REG_ERROR
449 #endif
450 #ifndef MICROCONTROLLER_DEFINED
451 #define MICROCONTROLLER_DEFINED
452 #endif
453 #ifdef MCS51REG_ENABLE_WARNINGS
454 #warning Selected HW: DS5000
455 #endif
456 #define P0
457 #define SP
458 #define DPL
459 #define DPH
460 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
461 #define TCON
462 #define TMOD
463 #define TL0
464 #define TL1
465 #define TH0
466 #define TH1
467 #define P1
468 #define SCON
469 #define SBUF
470 #define P2
471 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
472 #define P3
473 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
474 #define MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
475 #define TA
476 #define PSW
477 #define ACC
478 #define B
479 #endif
480 // end of definitions for the Dallas DS5000
481
482
483 // definitions for the Dallas DS5001
484 #ifdef MICROCONTROLLER_DS5001
485 #ifdef MICROCONTROLLER_DEFINED
486 #define MCS51REG_ERROR
487 #endif
488 #ifndef MICROCONTROLLER_DEFINED
489 #define MICROCONTROLLER_DEFINED
490 #endif
491 #ifdef MCS51REG_ENABLE_WARNINGS
492 #warning Selected HW: DS5001
493 #endif
494 #define P0
495 #define SP
496 #define DPL
497 #define DPH
498 #define PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
499 #define TCON
500 #define TMOD
501 #define TL0
502 #define TL1
503 #define TH0
504 #define TH1
505 #define P1
506 #define SCON
507 #define SBUF
508 #define P2
509 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
510 #define P3
511 #define IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
512 #define CRC
513 #define CRCLOW
514 #define CRCHIGH
515 #define MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
516 #define TA
517 #define RNR
518 #define PSW
519 #define RPCTL
520 #define STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
521 #define ACC
522 #define B
523 #endif
524 // end of definitions for the Dallas DS5001
525
526
527 // definitions for the Dallas DS80C320 and DS80C323 microcontrollers
528 #ifdef MICROCONTROLLER_DS80C32X
529 #ifdef MICROCONTROLLER_DEFINED
530 #define MCS51REG_ERROR
531 #endif
532 #ifndef MICROCONTROLLER_DEFINED
533 #define MICROCONTROLLER_DEFINED
534 #endif
535 #ifdef MCS51REG_ENABLE_WARNINGS
536 #warning Selected HW: Dallas DS80C320 or DS80C323
537 #endif
538 // 8051 register set
539 #define P0
540 #define SP
541 #define DPL
542 #define DPH
543 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
544 #define TCON
545 #define TMOD
546 #define TL0
547 #define TL1
548 #define TH0
549 #define TH1
550 #define P1
551 #define SCON
552 #define SCON0
553 #define SBUF
554 #define P2
555 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
556 #define P3
557 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
558 #define PSW
559 #define ACC
560 #define B
561 // 8052 specific registers
562 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
563 #define RCAP2L
564 #define RCAP2H
565 #define TL2
566 #define TH2
567 // DS80C320 specific register
568 #define DPL1
569 #define DPH1
570 #define DPS__x__x__x__x__x__x__x__SEL
571 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
572 #define EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
573 #define SADDR0
574 #define SADDR1
575 #define SADEN0
576 #define SADEN1
577 #define SCON1
578 #define SBUF1
579 #define STATUS__PIP__HIP__LIP__x__x__x__x__x
580 #define TA
581 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
582 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
583 #define WDCON
584 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
585 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
586 #endif
587 // end of definitions for the Dallas DS80C320 and DS80C323 microcontrollers
588
589
590 // definitions for the Dallas DS80C390
591 #ifdef MICROCONTROLLER_DS80C390
592 #ifdef MICROCONTROLLER_DEFINED
593 #define MCS51REG_ERROR
594 #endif
595 #ifndef MICROCONTROLLER_DEFINED
596 #define MICROCONTROLLER_DEFINED
597 #endif
598 #ifdef MCS51REG_ENABLE_WARNINGS
599 #warning Selected HW: Dallas DS80C390
600 #endif
601 // 8051 register set
602 #define P0
603 #define SP
604 #define DPL
605 #define DPH
606 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
607 #define TCON
608 #define TMOD
609 #define TL0
610 #define TL1
611 #define TH0
612 #define TH1
613 #define P1
614 #define SCON
615 #define SCON0
616 #define SBUF
617 #define P2
618 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
619 #define P3
620 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
621 #define PSW
622 #define ACC
623 #define B
624 // 8052 specific registers
625 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
626 #define RCAP2L
627 #define RCAP2H
628 #define TL2
629 #define TH2
630 // DS80C390 specific register
631 #define P4_AT_0X80
632 #define DPL1
633 #define DPH1
634 #define DPS__ID1__ID0__TSL__x__x__x__x__SEL
635 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
636 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
637 #define P4CNT
638 #define DPX
639 #define DPX1
640 #define C0RMS0
641 #define C0RMS1
642 #define ESP
643 #define AP
644 #define ACON__x__x__x__x__x__SA__AM1__AM0
645 #define C0TMA0
646 #define C0TMA1
647 #define P5_AT_0XA1
648 #define P5CNT
649 #define C0C
650 #define C0S
651 #define C0IR
652 #define C0TE
653 #define C0RE
654 #define SADDR0
655 #define SADDR1
656 #define C0M1C
657 #define C0M2C
658 #define C0M3C
659 #define C0M4C
660 #define C0M5C
661 #define C0M6C
662 #define C0M7C
663 #define C0M8C
664 #define C0M9C
665 #define C0M10C
666 #define SADEN0
667 #define SADEN1
668 #define C0M11C
669 #define C0M12C
670 #define C0M13C
671 #define C0M14C
672 #define C0M15C
673 #define SCON1
674 #define SBUF1
675 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
676 #define STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
677 #define MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
678 #define TA
679 #define T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
680 #define COR
681 #define MCNT0
682 #define MCNT1
683 #define MA
684 #define MB
685 #define MC
686 #define C1RSM0
687 #define C1RSM1
688 #define WDCON
689 #define C1TMA0
690 #define C1TMA1
691 #define C1C
692 #define C1S
693 #define C1IR
694 #define C1TE
695 #define C1RE
696 #define EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
697 #define MXMAX
698 #define C1M1C
699 #define C1M2C
700 #define C1M3C
701 #define C1M4C
702 #define C1M5C
703 #define C1M6C
704 #define C1M7C
705 #define C1M8C
706 #define C1M9C
707 #define EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
708 #define C1M10C
709 #define C1M11C
710 #define C1M12C
711 #define C1M13C
712 #define C1M14C
713 #define C1M15C
714 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
715 #endif
716 // end of definitions for the Dallas DS80C390
717
718 // definitions for the Dallas DS89C420 microcontroller
719 #ifdef MICROCONTROLLER_DS89C420
720 #ifdef MICROCONTROLLER_DEFINED
721 #define MCS51REG_ERROR
722 #endif
723 #ifndef MICROCONTROLLER_DEFINED
724 #define MICROCONTROLLER_DEFINED
725 #endif
726 #ifdef MCS51REG_ENABLE_WARNINGS
727 #warning Selected HW: Dallas DS89C420
728 #endif
729 // 8051 register set
730 #define P0
731 #define SP
732 #define DPL
733 #define DPH
734 #define PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
735 #define TCON
736 #define TMOD
737 #define TL0
738 #define TL1
739 #define TH0
740 #define TH1
741 #define P1
742 #define SCON
743 #define SCON0
744 #define SBUF
745 #define P2
746 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
747 #define P3
748 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
749 #define PSW
750 #define ACC
751 #define B
752 // 8052 specific registers
753 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
754 #define RCAP2L
755 #define RCAP2H
756 #define TL2
757 #define TH2
758 // DS8XC420 specific registers
759 #define ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
760 #define DPL1
761 #define DPH1
762 #define DPS__ID1__ID0__TSL__AID__x__x__x__SEL
763 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
764 #define CKMOD
765 #define IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
766 #define IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
767 #define EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
768 #define PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
769 #define SADDR0
770 #define SADDR1
771 #define SADEN0
772 #define SADEN1
773 #define SCON1
774 #define SBUF1
775 #define STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
776 #define TA
777 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
778 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
779 #define ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
780 #define WDCON
781 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
782 #define EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
783 #define EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
784 #define FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
785 #endif
786 // end of definitions for the Dallas DS89C420 microcontroller
787
788 // definitions for the Dallas DS87C520 and DS83C520 microcontrollers
789 #ifdef MICROCONTROLLER_DS8XC520
790 #ifdef MICROCONTROLLER_DEFINED
791 #define MCS51REG_ERROR
792 #endif
793 #ifndef MICROCONTROLLER_DEFINED
794 #define MICROCONTROLLER_DEFINED
795 #endif
796 #ifdef MCS51REG_ENABLE_WARNINGS
797 #warning Selected HW: Dallas DS87C520 or DS85C520
798 #endif
799 // 8051 register set
800 #define P0
801 #define SP
802 #define DPL
803 #define DPH
804 #define PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
805 #define TCON
806 #define TMOD
807 #define TL0
808 #define TL1
809 #define TH0
810 #define TH1
811 #define P1
812 #define SCON
813 #define SCON0
814 #define SBUF
815 #define P2
816 #define IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
817 #define P3
818 #define IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
819 #define PSW
820 #define ACC
821 #define B
822 // 8052 specific registers
823 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
824 #define RCAP2L
825 #define RCAP2H
826 #define TL2
827 #define TH2
828 // DS8XC520 specific registers
829 #define DPL1
830 #define DPH1
831 #define DPS__x__x__x__x__x__x__x__SEL
832 #define CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
833 #define EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
834 #define PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
835 #define SADDR0
836 #define SADDR1
837 #define SADEN0
838 #define SADEN1
839 #define SCON1
840 #define SBUF1
841 #define STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
842 #define TA
843 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
844 #define P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
845 #define WDCON
846 #define ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
847 #define BP2
848 #define WDCON
849 #define EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
850 #define EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
851 #endif
852 // end of definitions for the Dallas DS87C520 and DS83C520 microcontrollers
853
854
855 // definitions for the Philips P80C552 microcontroller
856 #ifdef MICROCONTROLLER_P80C552
857 #ifdef MICROCONTROLLER_DEFINED
858 #define MCS51REG_ERROR
859 #endif
860 #ifndef MICROCONTROLLER_DEFINED
861 #define MICROCONTROLLER_DEFINED
862 #endif
863 #ifdef MCS51REG_ENABLE_WARNINGS
864 #warning Selected HW: Philips P80C552
865 #endif
866 // 8051 register set
867 #define P0
868 #define SP
869 #define DPL
870 #define DPH
871 #define PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
872 #define TCON
873 #define TMOD
874 #define TL0
875 #define TL1
876 #define TH0
877 #define TH1
878 #define P1
879 #define SCON
880 #define SBUF
881 #define P2
882 #define IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
883 #define P3
884 #define IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
885 #define PSW
886 #define ACC
887 #define B
888 // P80C552 specific register-names
889 #define S0BUF // same as SBUF, set in mcs51reg.h
890 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
891 // P80C552 specific registers
892 #define ADCH_AT_0XC6
893 #define ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
894 #define CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
895 #define CTH0_AT_0XCC
896 #define CTH1_AT_0XCD
897 #define CTH2_AT_0XCE
898 #define CTH3_AT_0XCF
899 #define CMH0_AT_0XC9
900 #define CMH1_AT_0XCA
901 #define CMH2_AT_0XCB
902 #define CTL0_AT_0XAC
903 #define CTL1_AT_0XAD
904 #define CTL2_AT_0XAE
905 #define CTL3_AT_0XAF
906 #define CML0_AT_0XA9
907 #define CML1_AT_0XAA
908 #define CML2_AT_0XAB
909 #define IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
910 #define IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
911 #define PWM0_AT_0XFC
912 #define PWM1_AT_0XFD
913 #define PWMP_AT_0XFE
914 #define P1_EXT__SDA__SCL__RT2__T2__CT3I__CT2I__CT1I__CT0I
915 #define P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
916 #define P5_AT_0XC4
917 #define RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
918 #define S1ADR__x__x__x__x__x__x__x__GC
919 #define S1DAT_AT_0XDA
920 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
921 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
922 #define STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
923 #define TMH2_AT_0XED
924 #define TML2_AT_0XEC
925 #define TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
926 #define TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
927 #define T3_AT_0XFF
928 #endif
929 // end of definitions for the Philips P80C552 microcontroller
930
931
932 // definitions for the Philips P89C668
933 #ifdef MICROCONTROLLER_P89C668
934 #ifdef MICROCONTROLLER_DEFINED
935 #define MCS51REG_ERROR
936 #endif
937 #ifndef MICROCONTROLLER_DEFINED
938 #define MICROCONTROLLER_DEFINED
939 #endif
940 #ifdef MCS51REG_ENABLE_WARNINGS
941 #warning Selected HW: P89C668
942 #endif
943 #define P0
944 #define P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
945 #define P1
946 #define P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
947 #define P2
948 #define P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
949 #define P3
950 #define P3_EXT__x__x__CEX4__CEX3__x__x__x__x
951 #define SP
952 #define DPL
953 #define DPH
954 #define TCON
955 #define TMOD
956 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
957 #define TL0
958 #define TL1
959 #define TH0
960 #define TH1
961 #define SCON
962 #define S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
963 #define S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
964 #define SBUF
965 #define S0BUF SBUF
966 #define PSW
967 #define ACC
968 #define B
969 #define SADR_AT_0XA9
970 #define SADEN_AT_0XB9
971 #define S1IST_AT_0XDC
972 #define S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
973 #define S1DAT_AT_0XDA
974 #define S1ADR__x__x__x__x__x__x__x__GC
975 #define SBUF
976 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
977 #define T2MOD__x__x__x__x__x__x__T2OE__DCEN
978 #define RCAP2L
979 #define RCAP2H
980 #define TL2
981 #define TH2
982 #define IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
983 #define IEN1__x__x__x__x__x__x__x__ET2
984 #define IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
985 #define IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
986 #define CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
987 #define CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
988 #define AUXR__x__x__x__x__x__x__EXTRAM__A0
989 #define AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
990 #define WDTRST_AT_0XA6
991 #define CCAPM0_AT_0XC2
992 #define CCAPM1_AT_0XC3
993 #define CCAPM2_AT_0XC4
994 #define CCAPM3_AT_0XC5
995 #define CCAPM4_AT_0XC6
996 #define CCAP0L_AT_0XEA
997 #define CCAP1L_AT_0XEB
998 #define CCAP2L_AT_0XEC
999 #define CCAP3L_AT_0XED
1000 #define CCAP4L_AT_0XEE
1001 #define CH_AT_0XF9
1002 #define CL_AT_0XE9
1003 #define CCAP0H_AT_0XFA
1004 #define CCAP1H_AT_0XFB
1005 #define CCAP2H_AT_0XFC
1006 #define CCAP3H_AT_0XFD
1007 #define CCAP4H_AT_0XFE
1008 #endif
1009 // end of definitions for the Philips P89C668
1010
1011
1012 // definitions for the Infineon / Siemens SAB80509
1013 #ifdef MICROCONTROLLER_SAB80509
1014 #ifdef MICROCONTROLLER_DEFINED
1015 #define MCS51REG_ERROR
1016 #endif
1017 #ifndef MICROCONTROLLER_DEFINED
1018 #define MICROCONTROLLER_DEFINED
1019 #endif
1020 #ifdef MCS51REG_ENABLE_WARNINGS
1021 #warning Selected HW: Infineon / Siemens SAB80509
1022 #endif
1023 // 8051 register set without IP
1024 #define P0
1025 #define SP
1026 #define DPL
1027 #define DPH
1028 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1029 #define TCON
1030 #define TMOD
1031 #define TL0
1032 #define TL1
1033 #define TH0
1034 #define TH1
1035 #define WDTREL
1036 #define P1
1037 #define XPAGE
1038 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1039 #define IEN2__SAB80517
1040
1041 #define P2
1042 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1043 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1044
1045 #define P3
1046 #define SYSCON
1047 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1048 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1049
1050 #define IRCON
1051 #define CCEN
1052 #define CCL1
1053 #define CCH1
1054 #define CCL2
1055 #define CCH2
1056 #define CCL3
1057 #define CCH3
1058 #define CCL4
1059 #define CCH4
1060 #define CC4EN
1061 #define S0RELH
1062 #define S0RELL
1063 #define S1BUF
1064 #define S1CON_AT_0X9B
1065 #define S1RELH
1066 #define S1RELL
1067 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1068
1069 #define PSW
1070 #define CMEN
1071 #define CMH0
1072 #define CML0
1073 #define CMH1
1074 #define CML1
1075 #define CMH2
1076 #define CML2
1077 #define CMH3
1078 #define CML3
1079 #define CMH4
1080 #define CML4
1081 #define CMH5
1082 #define CML5
1083 #define CMH6
1084 #define CML6
1085 #define CMH7
1086 #define CML7
1087 #define CMSEL
1088 #define CRCL
1089 #define CRCH
1090 #define CTCOM_AT_0XE1
1091 #define CTRELH
1092 #define CTRELL
1093 #define TL2
1094 #define TH2
1095 #define ADCON0
1096 #define ADCON1
1097 #define ADDATH
1098 #define ADDATL
1099
1100 #define P4_AT_0XE8
1101 #define DPSEL
1102 #define ARCON
1103 #define MD0
1104 #define MD1
1105 #define MD2
1106 #define MD3
1107 #define MD4
1108 #define MD5
1109 #define S0BUF
1110
1111 #define ACC
1112
1113 #define B
1114
1115 #define P5_AT_0XF8
1116 #define P6_AT_0XFA
1117 #define P7
1118 #define P8
1119
1120 #define COMSETL
1121 #define COMSETH
1122 #define COMCLRL
1123 #define COMCLRH
1124 #define SETMSK
1125 #define CLRMSK
1126 #define SYSCON1
1127 #define FMODE
1128 #define PRSC
1129 #define CT1COM
1130 #define IEN3
1131 #define IRCON2
1132 #define EICC1
1133 #define CC1
1134 #define CC2
1135 #define CC3
1136 #define CC4
1137 #define CCR
1138 #define T2
1139 #define P9_AT_0XF9
1140 #endif
1141 // end of definitions for the Infineon / Siemens SAB80509
1142
1143
1144 // definitions for the Infineon / Siemens SAB80515 & SAB80535
1145 #ifdef MICROCONTROLLER_SAB80515
1146 #ifdef MICROCONTROLLER_DEFINED
1147 #define MCS51REG_ERROR
1148 #endif
1149 #ifndef MICROCONTROLLER_DEFINED
1150 #define MICROCONTROLLER_DEFINED
1151 #endif
1152 #ifdef MCS51REG_ENABLE_WARNINGS
1153 #warning Selected HW: Infineon / Siemens SAB80515 & SAB80535
1154 #endif
1155 // 8051 register set without IP
1156 #define P0
1157 #define SP
1158 #define DPL
1159 #define DPH
1160 #define PCON__SMOD__x__x__x__x__x__x__x
1161 #define TCON
1162 #define TMOD
1163 #define TL0
1164 #define TL1
1165 #define TH0
1166 #define TH1
1167 #define P1
1168 #define SCON
1169 #define SBUF
1170 #define P2
1171 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1172 #define P3
1173 #define PSW
1174 #define ACC
1175 #define B
1176 // SAB80515 specific registers
1177 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1178 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1179 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1180 #define IRCON
1181 #define CCEN
1182 #define CCL1
1183 #define CCH1
1184 #define CCL2
1185 #define CCH2
1186 #define CCL3
1187 #define CCH3
1188 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1189 #define CRCL
1190 #define CRCH
1191 #define TL2
1192 #define TH2
1193 #define ADCON
1194 #define ADDAT
1195 #define DAPR__SAB80515
1196 #define P4_AT_0XE8
1197 #define P5_AT_0XF8
1198 #define P6_AT_0XDB
1199 #endif
1200 // end of definitions for the Infineon / Siemens SAB80515
1201
1202
1203 // definitions for the Infineon / Siemens SAB80515A
1204 #ifdef MICROCONTROLLER_SAB80515A
1205 #ifdef MICROCONTROLLER_DEFINED
1206 #define MCS51REG_ERROR
1207 #endif
1208 #ifndef MICROCONTROLLER_DEFINED
1209 #define MICROCONTROLLER_DEFINED
1210 #endif
1211 #ifdef MCS51REG_ENABLE_WARNINGS
1212 #warning Selected HW: Infineon / Siemens SAB80515A
1213 #endif
1214 // 8051 register set without IP
1215 #define P0
1216 #define SP
1217 #define DPL
1218 #define DPH
1219 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1220 #define TCON
1221 #define TMOD
1222 #define TL0
1223 #define TL1
1224 #define TH0
1225 #define TH1
1226 #define P1
1227 #define SCON
1228 #define SBUF
1229 #define P2
1230 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1231 #define P3
1232 #define PSW
1233 #define ACC
1234 #define B
1235 // SAB80515A specific registers
1236 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1237 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1238 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1239 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1240 #define IRCON
1241 #define CCEN
1242 #define CCL1
1243 #define CCH1
1244 #define CCL2
1245 #define CCH2
1246 #define CCL3
1247 #define CCH3
1248 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1249 #define CRCL
1250 #define CRCH
1251 #define TL2
1252 #define TH2
1253 #define ADCON0
1254 #define ADDATH
1255 #define ADDATL
1256 #define ADCON1
1257 #define SRELL
1258 #define SYSCON
1259 #define SRELH
1260 #define P4_AT_0XE8
1261 #define P5_AT_0XF8
1262 #define P6_AT_0XDB
1263 #define XPAGE
1264 #endif
1265 // end of definitions for the Infineon / Siemens SAB80515A
1266
1267
1268 // definitions for the Infineon / Siemens SAB80517
1269 #ifdef MICROCONTROLLER_SAB80517
1270 #ifdef MICROCONTROLLER_DEFINED
1271 #define MCS51REG_ERROR
1272 #endif
1273 #ifndef MICROCONTROLLER_DEFINED
1274 #define MICROCONTROLLER_DEFINED
1275 #endif
1276 #ifdef MCS51REG_ENABLE_WARNINGS
1277 #warning Selected HW: Infineon / Siemens SAB80517
1278 #endif
1279 // 8051 register set without IP, SCON & SBUF
1280 #define P0
1281 #define SP
1282 #define DPL
1283 #define DPH
1284 #define PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
1285 #define TCON
1286 #define TMOD
1287 #define TL0
1288 #define TL1
1289 #define TH0
1290 #define TH1
1291 #define P1
1292 // #define SCON
1293 // #define SBUF
1294 #define P2
1295 #define IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
1296 #define P3
1297 #define PSW
1298 #define ACC
1299 #define B
1300 // SAB80517 specific registers
1301 #define P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
1302 #define IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
1303 #define IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
1304 #define IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
1305 #define IEN2__SAB80517
1306 #define IRCON
1307 #define CCEN
1308 #define CCL1
1309 #define CCH1
1310 #define CCL2
1311 #define CCH2
1312 #define CCL3
1313 #define CCH3
1314 #define CCL4
1315 #define CCH4
1316 #define CC4EN
1317 #define CMEN
1318 #define CMH0
1319 #define CML0
1320 #define CMH1
1321 #define CML1
1322 #define CMH2
1323 #define CML2
1324 #define CMH3
1325 #define CML3
1326 #define CMH4
1327 #define CML4
1328 #define CMH5
1329 #define CML5
1330 #define CMH6
1331 #define CML6
1332 #define CMH7
1333 #define CML7
1334 #define CMSEL
1335 #define T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
1336 #define CRCL
1337 #define CRCH
1338 #define CTCOM_AT_0XE1
1339 #define CTRELH
1340 #define CTRELL
1341 #define TL2
1342 #define TH2
1343 #define ADCON0
1344 #define ADCON1
1345 #define ADDAT
1346 #define DAPR__SAB80517
1347 #define P4_AT_0XE8
1348 #define P5_AT_0XF8
1349 #define P6_AT_0XFA
1350 #define P7_AT_0XDB
1351 #define P8_AT_0XDD
1352 #define DPSEL
1353 #define ARCON
1354 #define MD0
1355 #define MD1
1356 #define MD2
1357 #define MD3
1358 #define MD4
1359 #define MD5
1360 #define S0BUF
1361 #define S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
1362 #define S0RELH
1363 #define S0RELL
1364 #define S1BUF
1365 #define S1CON_AT_0X9B
1366 #define S1RELH
1367 #define S1RELL
1368 #define WDTH
1369 #define WDTL
1370 #define WDTREL
1371 #endif
1372 // end of definitions for the Infineon / Siemens SAB80517
1373
1374
1375 // definitions for the Atmel T89C51RD2
1376 #ifdef MICROCONTROLLER_T89C51RD2
1377 #ifdef MICROCONTROLLER_DEFINED
1378 #define MCS51REG_ERROR
1379 #endif
1380 #ifndef MICROCONTROLLER_DEFINED
1381 #define MICROCONTROLLER_DEFINED
1382 #endif
1383 #ifdef MCS51REG_ENABLE_WARNINGS
1384 #warning Selected HW: T89C51RD2
1385 #endif
1386
1387 // 8051 register set
1388 #define P0
1389 #define SP
1390 #define DPL
1391 #define DPH
1392 #define PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
1393 #define TCON
1394 #define TMOD
1395 #define TL0
1396 #define TL1
1397 #define TH0
1398 #define TH1
1399 #define P1
1400 #define SCON
1401 #define SBUF
1402 #define P2
1403 #define IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
1404 #define SADDR
1405 #define P3
1406 #define IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
1407 #define PSW
1408 #define ACC
1409 #define B
1410
1411 // 8052 register set
1412 #define T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
1413 #define RCAP2L
1414 #define RCAP2H
1415 #define TL2
1416 #define TH2
1417
1418 // T89C51RD2 register set
1419 #define P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
1420 #define P5_AT_0XE8
1421 #define SADEN0
1422
1423 #define AUXR1__x__x__x__x__GF3__x__x__DPS
1424 #define WDTRST_AT_0XA6
1425 #define WDTPRG_AT_0XA7
1426 #define AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1427 #define IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
1428 #define FCON
1429 #define EECON
1430 #define EETIM
1431 #define CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
1432 #define CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
1433 #define CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
1434 #define CCAPM0_AT_0XDA
1435 #define CCAPM1_AT_0XDB
1436 #define CCAPM2_AT_0XDC
1437 #define CCAPM3_AT_0XDD
1438 #define CCAPM4_AT_0XDE
1439 #define CL_AT_0XE9
1440 #define CCAP0L_AT_0XEA
1441 #define CCAP1L_AT_0XEB
1442 #define CCAP2L_AT_0XEC
1443 #define CCAP3L_AT_0XED
1444 #define CCAP4L_AT_0XEE
1445 #define CH_AT_0XF9
1446 #define CCAP0H_AT_0XFA
1447 #define CCAP1H_AT_0XFB
1448 #define CCAP2H_AT_0XFC
1449 #define CCAP3H_AT_0XFD
1450 #define CCAP4H_AT_0XFE
1451 #endif /* MICROCONTROLLER_T89C51RD2 */
1452 /* end of definition for the Atmel T89C51RD2 */
1453
1454
1455 /////////////////////////////////////////////////////////
1456 /// don't specify microcontrollers below this line! ///
1457 /////////////////////////////////////////////////////////
1458
1459
1460 // default microcontroller -> 8051
1461 // use default if no microcontroller specified
1462 #ifndef MICROCONTROLLER_DEFINED
1463 #define MICROCONTROLLER_DEFINED
1464 #ifdef MCS51REG_ENABLE_WARNINGS
1465 #warning No microcontroller defined!
1466 #warning Code generated for the 8051
1467 #endif
1468 // 8051 register set
1469 #define P0
1470 #define SP
1471 #define DPL
1472 #define DPH
1473 #define PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
1474 #define TCON
1475 #define TMOD
1476 #define TL0
1477 #define TL1
1478 #define TH0
1479 #define TH1
1480 #define P1
1481 #define SCON
1482 #define SBUF
1483 #define P2
1484 #define IE__EA__x__x__ES__ET1__EX1__ET0__EX0
1485 #define P3
1486 #define IP__x__x__x__PS__PT1__PX1__PT0__PX0
1487 #define PSW
1488 #define ACC
1489 #define B
1490 #endif
1491 // end of definitions for the default microcontroller
1492
1493
1494 #ifdef MCS51REG_ERROR
1495 #error Two or more microcontrollers defined!
1496 #endif
1497
1498 #ifdef MCS51REG_EXTERNAL_ROM
1499 #ifndef MCS51REG_UNDEFINE_P0
1500 #define MCS51REG_UNDEFINE_P0
1501 #endif
1502 #ifndef MCS51REG_UNDEFINE_P2
1503 #define MCS51REG_UNDEFINE_P2
1504 #endif
1505 #endif
1506
1507 #ifdef MCS51REG_EXTERNAL_RAM
1508 #ifndef MCS51REG_UNDEFINE_P0
1509 #define MCS51REG_UNDEFINE_P0
1510 #endif
1511 #ifndef MCS51REG_UNDEFINE_P2
1512 #define MCS51REG_UNDEFINE_P2
1513 #endif
1514 #endif
1515
1516 #ifdef MCS51REG_UNDEFINE_P0
1517 #undef P0
1518 #endif
1519
1520 #ifdef MCS51REG_UNDEFINE_P2
1521 #undef P2
1522 #endif
1523
1524 ////////////////////////////////
1525 /// Register definitions ///
1526 /// (In alphabetical order) ///
1527 ////////////////////////////////
1528
1529 #ifdef ACC
1530 #undef ACC
1531 SFR(ACC, 0xE0);
1532 #endif
1533
1534 #ifdef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1535 #undef ACON__PAGEE__PAGES1__PAGES0__x__x__x__x__x
1536 SFR(ACON, 0x9D); // DS89C420 specific
1537 // Not directly accessible bits
1538 #define PAGES0 0x20
1539 #define PAGES1 0x40
1540 #define PAGEE 0x80
1541 #endif
1542
1543 #ifdef ACON__x__x__x__x__x__SA__AM1__AM0
1544 #undef ACON__x__x__x__x__x__SA__AM1__AM0
1545 SFR(ACON, 0x9D); // DS89C390 specific
1546 // Not directly accessible bits
1547 #define AM0 0x01
1548 #define AM1 0x02
1549 #define SA 0x04
1550 #endif
1551
1552 #ifdef ADCH_AT_0XC6
1553 #undef ADCH_AT_0XC6
1554 SFR(ADCH, 0xC6); // A/D converter high
1555 #endif
1556
1557 #ifdef ADCON
1558 #undef ADCON
1559 SFR(ADCON, 0xD8); // A/D-converter control register SAB80515 specific
1560 // Bit registers
1561 SBIT(MX0, 0xD8, 0);
1562 SBIT(MX1, 0xD8, 1);
1563 SBIT(MX2, 0xD8, 2);
1564 SBIT(ADM, 0xD8, 3);
1565 SBIT(BSY, 0xD8, 4);
1566 SBIT(CLK, 0xD8, 6);
1567 SBIT(BD, 0xD8, 7);
1568 #endif
1569
1570 // ADCON0 ... Infineon / Siemens also called this register ADCON in the User Manual
1571 #ifdef ADCON0
1572 #undef ADCON0
1573 SFR(ADCON0, 0xD8); // A/D-converter control register 0 SAB80515A &
1574 // Bit registers // SAB80517 specific
1575 SBIT(MX0, 0xD8, 0);
1576 SBIT(MX1, 0xD8, 1);
1577 SBIT(MX2, 0xD8, 2);
1578 SBIT(ADM, 0xD8, 3);
1579 SBIT(BSY, 0xD8, 4);
1580 SBIT(ADEX, 0xD8, 5);
1581 SBIT(CLK, 0xD8, 6);
1582 SBIT(BD, 0xD8, 7);
1583 // Not directly accessible ADCON0
1584 #define ADCON0_MX0 0x01
1585 #define ADCON0_MX1 0x02
1586 #define ADCON0_MX2 0x04
1587 #define ADCON0_ADM 0x08
1588 #define ADCON0_BSY 0x10
1589 #define ADCON0_ADEX 0x20
1590 #define ADCON0_CLK 0x40
1591 #define ADCON0_BD 0x80
1592 #endif
1593
1594 #ifdef ADCON1
1595 #undef ADCON1
1596 SFR(ADCON1, 0xDC); // A/D-converter control register 1 SAB80515A & SAB80517 specific
1597 // Not directly accessible ADCON1
1598 #define ADCON1_MX0 0x01
1599 #define ADCON1_MX1 0x02
1600 #define ADCON1_MX2 0x04
1601 #define ADCON1_ADCL 0x80
1602 #endif
1603
1604 #ifdef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1605 #undef ADCON__ADC_1__ADC_0__ADEX__ADCI__ADCS__AADR2__AADR1__AADR0
1606 SFR(ADCON, 0xC5); // A/D control, P80C552 specific
1607 // Not directly accessible Bits.
1608 #define AADR0 0x01
1609 #define AADR1 0x02
1610 #define AADR2 0x04
1611 #define ADCS 0x08
1612 #define ADCI 0x10
1613 #define ADEX 0x20
1614 #define ADC_0 0x40 // different name as ADC0 in P5
1615 #define ADC_1 0x80 // different name as ADC1 in P5
1616 #endif
1617
1618 #ifdef ADDAT
1619 #undef ADDAT
1620 SFR(ADDAT, 0xD9); // A/D-converter data register SAB80515 specific
1621 #endif
1622
1623 #ifdef ADDATH
1624 #undef ADDATH
1625 SFR(ADDATH, 0xD9); // A/D data high byte SAB80515A specific
1626 #endif
1627
1628 #ifdef ADDATL
1629 #undef ADDATL
1630 SFR(ADDATL, 0xDA); // A/D data low byte SAB80515A specific
1631 #endif
1632
1633 #ifdef ARCON
1634 #undef ARCON
1635 SFR(ARCON, 0xEF); // arithmetic control register SAB80517
1636 #endif
1637
1638 #ifdef AP
1639 #undef AP
1640 SFR(AP, 0x9C); // DS80C390
1641 #endif
1642
1643 #ifdef AUXR__x__x__x__x__x__x__EXTRAM__A0
1644 #undef AUXR__x__x__x__x__x__x__EXTRAM__A0
1645 // P89C668 specific, Auxilary
1646 SFR(AUXR, 0x8E);
1647 // not bit addressable:
1648 #define EXTRAM 0x02
1649 #define A0 0x01
1650 #endif
1651
1652 #ifdef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1653 #undef AUXR__x__x__M0__x__XRS1__XRS0__EXTRAM__A0
1654 SFR(AUXR, 0x8E);
1655 #define AO 0x01
1656 #define EXTRAM 0x02
1657 #define XRS0 0x04
1658 #define XRS1 0x08
1659 #define M0 0x20
1660 #endif
1661 #ifdef B
1662 #undef B
1663 SFR(B, 0xF0);
1664 // Bit registers
1665 SBIT(BREG_F0, 0xF0, 0);
1666 SBIT(BREG_F1, 0xF0, 1);
1667 SBIT(BREG_F2, 0xF0, 2);
1668 SBIT(BREG_F3, 0xF0, 3);
1669 SBIT(BREG_F4, 0xF0, 4);
1670 SBIT(BREG_F5, 0xF0, 5);
1671 SBIT(BREG_F6, 0xF0, 6);
1672 SBIT(BREG_F7, 0xF0, 7);
1673 #endif
1674
1675 #ifdef AUXR1__x__x__x__x__GF3__x__x__DPS
1676 #undef AUXR1__x__x__x__x__GF3__x__x__DPS
1677 SFR(AUXR1, 0xA2);
1678 #define DPS 0x01
1679 #define GF3 0x08
1680 #endif
1681
1682 #ifdef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1683 #undef AUXR1__x__x__ENBOOT__x__GF2__0__x__DPS
1684 // P89C668 specific, Auxilary 1
1685 SFR(AUXR1, 0xA2);
1686 #define ENBOOT 0x20
1687 #define GF2 0x08
1688 #define ALWAYS_ZERO 0x04
1689 #define DPS 0x01
1690 #endif
1691
1692 #ifdef BP2
1693 #undef BP2
1694 SFR(BP2, 0xC3);
1695 // Not directly accessible bits
1696 #define MS0 0x01
1697 #define MS1 0x02
1698 #define MS2 0x04
1699 #define LB1 0x08
1700 #define LB2 0x10
1701 #define LB3 0x20
1702 #endif
1703
1704 #ifdef C0C
1705 #undef C0C
1706 SFR(C0C, 0xA3); // DS80C390 specific
1707 // Not directly accessible bits
1708 #define SWINT 0x01
1709 #define ERCS 0x02
1710 #define AUTOB 0x04
1711 #define CRST 0x08
1712 #define SIESTA 0x10
1713 #define PDE 0x20
1714 #define STIE 0x40
1715 #define ERIE 0x80
1716 #endif
1717
1718 #ifdef C0IR
1719 #undef C0IR
1720 SFR(C0IR, 0xA5); // DS80C390 specific
1721 // Not directly accessible bits
1722 #define INTIN0 0x01
1723 #define INTIN1 0x02
1724 #define INTIN2 0x04
1725 #define INTIN3 0x08
1726 #define INTIN4 0x10
1727 #define INTIN5 0x20
1728 #define INTIN6 0x40
1729 #define INTIN7 0x80
1730 #endif
1731
1732 #ifdef C0M1C
1733 #undef C0M1C
1734 SFR(C0M1C, 0xAB); // DS80C390 specific
1735 // Not directly accessible bits
1736 #define DTUP 0x01
1737 #define ROW_TIH 0x02
1738 #define MTRQ 0x04
1739 #define EXTRQ 0x08
1740 #define INTRQ 0x10
1741 #define ERI 0x20
1742 #define ETI 0x40
1743 #define MSRDY 0x80
1744 #endif
1745
1746 #ifdef C0M2C
1747 #undef C0M2C
1748 SFR(C0M2C, 0xAC); // DS80C390 specific
1749 #endif
1750
1751 #ifdef C0M3C
1752 #undef C0M3C
1753 SFR(C0M3C, 0xAD); // DS80C390 specific
1754 #endif
1755
1756 #ifdef C0M4C
1757 #undef C0M4C
1758 SFR(C0M4C, 0xAE); // DS80C390 specific
1759 #endif
1760
1761 #ifdef C0M5C
1762 #undef C0M5C
1763 SFR(C0M5C, 0xAF); // DS80C390 specific
1764 #endif
1765
1766 #ifdef C0M6C
1767 #undef C0M6C
1768 SFR(C0M6C, 0xB3); // DS80C390 specific
1769 #endif
1770
1771 #ifdef C0M7C
1772 #undef C0M7C
1773 SFR(C0M7C, 0xB4); // DS80C390 specific
1774 #endif
1775
1776 #ifdef C0M8C
1777 #undef C0M8C
1778 SFR(C0M8C, 0xB5); // DS80C390 specific
1779 #endif
1780
1781 #ifdef C0M9C
1782 #undef C0M9C
1783 SFR(C0M9C, 0xB6); // DS80C390 specific
1784 #endif
1785
1786 #ifdef C0M10C
1787 #undef C0M10C
1788 SFR(C0M10C, 0xB7); // DS80C390 specific
1789 #endif
1790
1791 #ifdef C0M11C
1792 #undef C0M11C
1793 SFR(C0M11C, 0xBB); // DS80C390 specific
1794 #endif
1795
1796 #ifdef C0M12C
1797 #undef C0M12C
1798 SFR(C0M12C, 0xBC); // DS80C390 specific
1799 #endif
1800
1801 #ifdef C0M13C
1802 #undef C0M13C
1803 SFR(C0M13C, 0xBD); // DS80C390 specific
1804 #endif
1805
1806 #ifdef C0M14C
1807 #undef C0M14C
1808 SFR(C0M14C, 0xBE); // DS80C390 specific
1809 #endif
1810
1811 #ifdef C0M15C
1812 #undef C0M15C
1813 SFR(C0M15C, 0xBF); // DS80C390 specific
1814 #endif
1815
1816 #ifdef C0RE
1817 #undef C0RE
1818 SFR(C0RE, 0xA7); // DS80C390 specific
1819 #endif
1820
1821 #ifdef C0RMS0
1822 #undef C0RMS0
1823 SFR(C0RMS0, 0x96); // DS80C390 specific
1824 #endif
1825
1826 #ifdef C0RMS1
1827 #undef C0RMS1
1828 SFR(C0RMS1, 0x97); // DS80C390 specific
1829 #endif
1830
1831 #ifdef C0S
1832 #undef C0S
1833 SFR(C0S, 0xA4); // DS80C390 specific
1834 // Not directly accessible bits
1835 #define ER0 0x01
1836 #define ER1 0x02
1837 #define ER2 0x04
1838 #define TXS 0x08
1839 #define RXS 0x10
1840 #define WKS 0x20
1841 #define EC96_128 0x40
1842 #define BSS 0x80
1843 #endif
1844
1845 #ifdef C0TE
1846 #undef C0TE
1847 SFR(C0TE, 0xA6); // DS80C390 specific
1848 #endif
1849
1850 #ifdef C0TMA0
1851 #undef C0TMA0
1852 SFR(C0TMA0, 0x9E); // DS80C390 specific
1853 #endif
1854
1855 #ifdef C0TMA1
1856 #undef C0TMA1
1857 SFR(C0TMA1, 0x9F); // DS80C390 specific
1858 #endif
1859
1860 #ifdef C1C
1861 #undef C1C
1862 SFR(C1C, 0xE3); // DS80C390 specific
1863 // Not directly accessible bits
1864 #define SWINT 0x01
1865 #define ERCS 0x02
1866 #define AUTOB 0x04
1867 #define CRST 0x08
1868 #define SIESTA 0x10
1869 #define PDE 0x20
1870 #define STIE 0x40
1871 #define ERIE 0x80
1872 #endif
1873
1874 #ifdef C1IR
1875 #undef C1IR
1876 SFR(C1IR, 0xE5); // DS80C390 specific
1877 // Not directly accessible bits
1878 #define INTIN0 0x01
1879 #define INTIN1 0x02
1880 #define INTIN2 0x04
1881 #define INTIN3 0x08
1882 #define INTIN4 0x10
1883 #define INTIN5 0x20
1884 #define INTIN6 0x40
1885 #define INTIN7 0x80
1886 #endif
1887
1888 #ifdef C1IRE
1889 #undef C1IRE
1890 SFR(C1RE, 0xE7); // DS80C390 specific
1891 #endif
1892
1893 #ifdef C1M1C
1894 #undef C1M1C
1895 SFR(C1M1C, 0xEB); // DS80C390 specific
1896 #endif
1897
1898 #ifdef C1M2C
1899 #undef C1M2C
1900 SFR(C1M2C, 0xEC); // DS80C390 specific
1901 #endif
1902
1903 #ifdef C1M3C
1904 #undef C1M3C
1905 SFR(C1M3C, 0xED); // DS80C390 specific
1906 #endif
1907
1908 #ifdef C1M4C
1909 #undef C1M4C
1910 SFR(C1M4C, 0xEE); // DS80C390 specific
1911 #endif
1912
1913 #ifdef C1M5C
1914 #undef C1M5C
1915 SFR(C1M5C, 0xEF); // DS80C390 specific
1916 #endif
1917
1918 #ifdef C1M6C
1919 #undef C1M6C
1920 SFR(C1M6C, 0xF3); // DS80C390 specific
1921 #endif
1922
1923 #ifdef C1M7C
1924 #undef C1M7C
1925 SFR(C1M7C, 0xF4); // DS80C390 specific
1926 #endif
1927
1928 #ifdef C1M8C
1929 #undef C1M8C
1930 SFR(C1M8C, 0xF5); // DS80C390 specific
1931 #endif
1932
1933 #ifdef C1M9C
1934 #undef C1M9C
1935 SFR(C1M9C, 0xF6); // DS80C390 specific
1936 #endif
1937
1938 #ifdef C1M10C
1939 #undef C1M10C
1940 SFR(C1M10C, 0xF7); // DS80C390 specific
1941 #endif
1942
1943 #ifdef C1M11C
1944 #undef C1M11C
1945 SFR(C1M11C, 0xFB); // DS80C390 specific
1946 #endif
1947
1948 #ifdef C1M12C
1949 #undef C1M12C
1950 SFR(C1M12C, 0xFC); // DS80C390 specific
1951 #endif
1952
1953 #ifdef C1M13C
1954 #undef C1M13C
1955 SFR(C1M13C, 0xFD); // DS80C390 specific
1956 #endif
1957
1958 #ifdef C1M14C
1959 #undef C1M14C
1960 SFR(C1M14C, 0xFE); // DS80C390 specific
1961 #endif
1962
1963 #ifdef C1M15C
1964 #undef C1M15C
1965 SFR(C1M15C, 0xFF); // DS80C390 specific
1966 #endif
1967
1968 #ifdef C1S
1969 #undef C1S
1970 SFR(C1S, 0xE4); // DS80C390 specific
1971 // Not directly accessible bits
1972 #define ER0 0x01
1973 #define ER1 0x02
1974 #define ER2 0x04
1975 #define TXS 0x08
1976 #define RXS 0x10
1977 #define WKS 0x20
1978 #define CECE 0x40
1979 #define BSS 0x80
1980 #endif
1981
1982 #ifdef C1ITE
1983 #undef C1ITE
1984 SFR(C1TE, 0xE6); // DS80C390 specific
1985 #endif
1986
1987 #ifdef C1RSM0
1988 #undef C1RSM0
1989 SFR(C1RSM0, 0xD6); // DS80C390 specific
1990 #endif
1991
1992 #ifdef C1RSM1
1993 #undef C1RSM1
1994 SFR(C1RSM1, 0xD7); // DS80C390 specific
1995 #endif
1996
1997 #ifdef C1TMA0
1998 #undef C1TMA0
1999 SFR(C1TMA0, 0xDE); // DS80C390 specific
2000 #endif
2001
2002 #ifdef C1TMA1
2003 #undef C1TMA1
2004 SFR(C1TMA1, 0xDF); // DS80C390 specific
2005 #endif
2006
2007 #ifdef CC1
2008 #undef CC1
2009 SFR(CC1, 0xC2);
2010 #endif
2011
2012 #ifdef CC2
2013 #undef CC2
2014 SFR(CC2, 0xC4);
2015 #endif
2016
2017 #ifdef CC3
2018 #undef CC3
2019 SFR(CC3, 0xC6);
2020 #endif
2021
2022 #ifdef CC4
2023 #undef CC4
2024 SFR(CC4, 0xCE);
2025 #endif
2026
2027 #ifdef CC4EN
2028 #undef CC4EN
2029 SFR(CC4EN, 0xC9); // compare/capture 4 enable register SAB80517 specific
2030 #endif
2031
2032 #ifdef CCAP0H_AT_0XFA
2033 #undef CCAP0H_AT_0XFA
2034 SFR(CCAP0H, 0xFA);
2035 #endif
2036
2037 #ifdef CCAP1H_AT_0XFB
2038 #undef CCAP1H_AT_0XFB
2039 SFR(CCAP1H, 0xFB);
2040 #endif
2041
2042 #ifdef CCAP2H_AT_0XFC
2043 #undef CCAP2H_AT_0XFC
2044 SFR(CCAP2H, 0xFC);
2045 #endif
2046
2047 #ifdef CCAP3H_AT_0XFD
2048 #undef CCAP3H_AT_0XFD
2049 SFR(CCAP3H, 0xFD);
2050 #endif
2051
2052 #ifdef CCAP4H_AT_0XFE
2053 #undef CCAP4H_AT_0XFE
2054 SFR(CCAP4H, 0xFE);
2055 #endif
2056
2057 #ifdef CCAP0L_AT_0XEA
2058 #undef CCAP0L_AT_0XEA
2059 SFR(CCAP0L, 0xEA);
2060 #endif
2061
2062 #ifdef CCAP1L_AT_0XEB
2063 #undef CCAP1L_AT_0XEB
2064 SFR(CCAP1L, 0xEB);
2065 #endif
2066
2067 #ifdef CCAP2L_AT_0XEC
2068 #undef CCAP2L_AT_0XEC
2069 SFR(CCAP2L, 0xEC);
2070 #endif
2071
2072 #ifdef CCAP3L_AT_0XED
2073 #undef CCAP3L_AT_0XED
2074 SFR(CCAP3L, 0xED);
2075 #endif
2076
2077 #ifdef CCAP4L_AT_0XEE
2078 #undef CCAP4L_AT_0XEE
2079 SFR(CCAP4L, 0xEE);
2080 #endif
2081
2082 #ifdef CCAPM0_AT_0XC2
2083 #undef CCAPM0_AT_0XC2
2084 // P89C668 specific, Capture module:
2085 SFR(CCAPM0, 0xC2);
2086 #endif
2087
2088 #ifdef CCAPM0_AT_0XDA
2089 #undef CCAPM0_AT_0XDA
2090 SFR(CCAPM0, 0xDA);
2091 #define ECCF 0x01
2092 #define PWM 0x02
2093 #define TOG 0x04
2094 #define MAT 0x08
2095 #define CAPN 0x10
2096 #define CAPP 0x20
2097 #define ECOM 0x40
2098 #endif
2099
2100 #ifdef CCAPM1_AT_0XC3
2101 #undef CCAPM1_AT_0XC3
2102 SFR(CCAPM1, 0xC3);
2103 #endif
2104
2105 #ifdef CCAPM1_AT_0XDB
2106 #undef CCAPM1_AT_0XDB
2107 SFR(CCAPM1, 0xDB);
2108 #endif
2109
2110 #ifdef CCAPM2_AT_0XC4
2111 #undef CCAPM2_AT_0XC4
2112 SFR(CCAPM2, 0xC4);
2113 #endif
2114
2115 #ifdef CCAPM2_AT_0XDC
2116 #undef CCAPM2_AT_0XDC
2117 SFR(CCAPM2, 0x0DC);
2118 #endif
2119
2120 #ifdef CCAPM3_AT_0XC5
2121 #undef CCAPM3_AT_0XC5
2122 SFR(CCAPM3, 0xC5);
2123 #endif
2124
2125 #ifdef CCAPM3_AT_0XDD
2126 #undef CCAPM3_AT_0XDD
2127 SFR(CCAPM3, 0x0DD);
2128 #endif
2129
2130 #ifdef CCAPM4_AT_0XDE
2131 #undef CCAPM4_AT_0XDE
2132 SFR(CCAPM4, 0x0DE);
2133 #endif
2134
2135 #ifdef CCAPM4_AT_0XC6
2136 #undef CCAPM4_AT_0XC6
2137 SFR(CCAPM4, 0xC6);
2138 #endif
2139
2140 #ifdef CCEN
2141 #undef CCEN
2142 SFR(CCEN, 0xC1); // compare/capture enable register SAB80515 specific
2143 #endif
2144
2145 #ifdef CCH1
2146 #undef CCH1
2147 SFR(CCH1, 0xC3); // compare/capture register 1, high byte SAB80515 specific
2148 #endif
2149
2150 #ifdef CCH2
2151 #undef CCH2
2152 SFR(CCH2, 0xC5); // compare/capture register 2, high byte SAB80515 specific
2153 #endif
2154
2155 #ifdef CCH3
2156 #undef CCH3
2157 SFR(CCH3, 0xC7); // compare/capture register 3, high byte SAB80515 specific
2158 #endif
2159
2160 #ifdef CCH4
2161 #undef CCH4
2162 SFR(CCH4, 0xCF); // compare/capture register 4, high byte SAB80515 specific
2163 #endif
2164
2165 #ifdef CCL1
2166 #undef CCL1
2167 SFR(CCL1, 0xC2); // compare/capture register 1, low byte SAB80515 specific
2168 #endif
2169
2170 #ifdef CCL2
2171 #undef CCL2
2172 SFR(CCL2, 0xC4); // compare/capture register 2, low byte SAB80515 specific
2173 #endif
2174
2175 #ifdef CCL3
2176 #undef CCL3
2177 SFR(CCL3, 0xC6); // compare/capture register 3, low byte SAB80515 specific
2178 #endif
2179
2180 #ifdef CCL4
2181 #undef CCL4
2182 SFR(CCL4, 0xCE); // compare/capture register 4, low byte SAB80515 specific
2183 #endif
2184
2185 #ifdef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2186 #undef CCON__0xD8__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2187 SFR(CCON, 0xD8); // T89C51RD2 specific register
2188 // Bit registers
2189 SBIT(CCF0, 0xD8, 0);
2190 SBIT(CCF1, 0xD8, 1);
2191 SBIT(CCF2, 0xD8, 2);
2192 SBIT(CCF3, 0xD8, 3);
2193 SBIT(CCF4, 0xD8, 4);
2194 SBIT(CR, 0xD8, 6);
2195 SBIT(CF, 0xD8, 7);
2196 #endif
2197
2198 #ifdef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2199 #undef CCON__CF__CR__x__CCF4__CCF3__CCF2__CCF1__CCF0
2200 // P89C668 specific, PCA Counter control:
2201 SFR(CCON, 0xC0);
2202 // Bit registers
2203 SBIT(CCF0, 0xC0, 0);
2204 SBIT(CCF1, 0xC0, 1);
2205 SBIT(CCF2, 0xC0, 2);
2206 SBIT(CCF3, 0xC0, 3);
2207 SBIT(CCF4, 0xC0, 4);
2208 //__sbit __at 0xC5 -
2209 SBIT(CR, 0xC0, 6);
2210 SBIT(CF, 0xC0, 7);
2211 #endif
2212
2213 #ifdef CCR
2214 #undef CCR
2215 SFR(CCR, 0xCA);
2216 #endif
2217
2218 #ifdef CH_AT_0XF9
2219 #undef CH_AT_0XF9
2220 SFR(CH, 0xF9);
2221 #endif
2222
2223 #ifdef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2224 #undef CMOD__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2225 // P89C668 specific, PCA Counter mode:
2226 SFR(CMOD, 0xC1);
2227 // not bit addressable:
2228 #define CIDL 0x80
2229 #define WDTE 0x40
2230 #define CPS1 0x04
2231 #define CPS0 0x02
2232 #define ECF 0x01
2233 #endif
2234
2235 #ifdef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2236 #undef CKCON__WD1__WD0__T2M__T1M__TOM__MD2__MD1__MD0
2237 SFR(CKCON, 0x8E); // DS80C320 & DS80C390 specific
2238 // Not directly accessible Bits.
2239 #define MD0 0x01
2240 #define MD1 0x02
2241 #define MD2 0x04
2242 #define T0M 0x08
2243 #define T1M 0x10
2244 #define T2M 0x20
2245 #define WD0 0x40
2246 #define WD1 0x80
2247 #endif
2248
2249 #ifdef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2250 #undef CKCON__X2__T0X2__T1X2__T2X2__SiX2__PcaX2__WdX2__x
2251 SFR(CKCON, 0x8F);
2252 #define X2 0x01
2253 #define T0X2 0x02
2254 #define T1X2 0x04
2255 #define T2X2 0x08
2256 #define SiX2 0x10
2257 #define PcaX2 0x20
2258 #define WdX2 0x40
2259 #endif
2260
2261 #ifdef CKMOD
2262 #undef CKMOD
2263 SFR(CKMOD, 0x96); // DS89C420 specific
2264 // Not directly accessible Bits.
2265 #define T0MH 0x08
2266 #define T1MH 0x10
2267 #define T2MH 0x20
2268 #endif
2269
2270 #ifdef CL_AT_0XE9
2271 #undef CL_AT_0XE9
2272 SFR(CL, 0xE9);
2273 #endif
2274
2275 #ifdef CLRMSK
2276 #undef CLRMSK
2277 SFR(CLRMSK, 0xA6);
2278 #endif
2279
2280 #ifdef CMEN
2281 #undef CMEN
2282 SFR(CMEN, 0xF6); // compare enable register SAB80517 specific
2283 #endif
2284
2285 #ifdef CMH0
2286 #undef CMH0
2287 SFR(CMH0, 0xD3); // compare register 0 high byte SAB80517 specific
2288 #endif
2289
2290 #ifdef CMH1
2291 #undef CMH1
2292 SFR(CMH1, 0xD5); // compare register 1 high byte SAB80517 specific
2293 #endif
2294
2295 #ifdef CMH2
2296 #undef CMH2
2297 SFR(CMH2, 0xD7); // compare register 2 high byte SAB80517 specific
2298 #endif
2299
2300 #ifdef CMH3
2301 #undef CMH3
2302 SFR(CMH3, 0xE3); // compare register 3 high byte SAB80517 specific
2303 #endif
2304
2305 #ifdef CMH4
2306 #undef CMH4
2307 SFR(CMH4, 0xE5); // compare register 4 high byte SAB80517 specific
2308 #endif
2309
2310 #ifdef CMH5
2311 #undef CMH5
2312 SFR(CMH5, 0xE7); // compare register 5 high byte SAB80517 specific
2313 #endif
2314
2315 #ifdef CMH6
2316 #undef CMH6
2317 SFR(CMH6, 0xF3); // compare register 6 high byte SAB80517 specific
2318 #endif
2319
2320 #ifdef CMH7
2321 #undef CMH7
2322 SFR(CMH7, 0xF5); // compare register 7 high byte SAB80517 specific
2323 #endif
2324
2325 #ifdef CMH0_AT_0XC9
2326 #undef CMH0_AT_0XC9
2327 SFR(CMH0, 0xC9); // Compare high 0, P80C552 specific
2328 #endif
2329
2330 #ifdef CMH1_AT_0XCA
2331 #undef CMH1_AT_0XCA
2332 SFR(CMH1, 0xCA); // Compare high 1, P80C552 specific
2333 #endif
2334
2335 #ifdef CMH2_AT_0XCB
2336 #undef CMH2_AT_0XCB
2337 SFR(CMH2, 0xCB); // Compare high 2, P80C552 specific
2338 #endif
2339
2340 #ifdef CML0
2341 #undef CML0
2342 SFR(CML0, 0xD2); // compare register 0 low byte SAB80517 specific
2343 #endif
2344
2345 #ifdef CML1
2346 #undef CML1
2347 SFR(CML1, 0xD4); // compare register 1 low byte SAB80517 specific
2348 #endif
2349
2350 #ifdef CML2
2351 #undef CML2
2352 SFR(CML2, 0xD6); // compare register 2 low byte SAB80517 specific
2353 #endif
2354
2355 #ifdef CML3
2356 #undef CML3
2357 SFR(CML3, 0xE2); // compare register 3 low byte SAB80517 specific
2358 #endif
2359
2360 #ifdef CML4
2361 #undef CML4
2362 SFR(CML4, 0xE4); // compare register 4 low byte SAB80517 specific
2363 #endif
2364
2365 #ifdef CML5
2366 #undef CML5
2367 SFR(CML5, 0xE6); // compare register 5 low byte SAB80517 specific
2368 #endif
2369
2370 #ifdef CML6
2371 #undef CML6
2372 SFR(CML6, 0xF2); // compare register 6 low byte SAB80517 specific
2373 #endif
2374
2375 #ifdef CML7
2376 #undef CML7
2377 SFR(CML7, 0xF4); // compare register 7 low byte SAB80517 specific
2378 #endif
2379
2380 #ifdef CML0_AT_0XA9
2381 #undef CML0_AT_0XA9
2382 SFR(CML0, 0xA9); // Compare low 0, P80C552 specific
2383 #endif
2384
2385 #ifdef CML1_AT_0XAA
2386 #undef CML1_AT_0XAA
2387 SFR(CML1, 0xAA); // Compare low 1, P80C552 specific
2388 #endif
2389
2390 #ifdef CML2_AT_0XAB
2391 #undef CML2_AT_0XAB
2392 SFR(CML2, 0xAB); // Compare low 2, P80C552 specific
2393 #endif
2394
2395 #ifdef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2396 #undef CMOD__0xD9__CIDL__WDTE__x__x__x__CPS1__CPS0__ECF
2397 SFR(CMOD, 0xD9);
2398 #define ECF 0x01
2399 #define CPS0 0x02
2400 #define CPS1 0x04
2401 #define WDTE 0x40
2402 #define CIDL 0x80
2403 #endif
2404
2405 #ifdef CMSEL
2406 #undef CMSEL
2407 SFR(CMSEL, 0xF7); // compare input select SAB80517
2408 #endif
2409
2410 #ifdef COMCLRH
2411 #undef COMCLRH
2412 SFR(COMCLRH, 0xA4);
2413 #endif
2414
2415 #ifdef COMCLRL
2416 #undef COMCLRL
2417 SFR(COMCLRL, 0xA3);
2418 #endif
2419
2420 #ifdef COMSETH
2421 #undef COMSETH
2422 SFR(COMSETH, 0xA2);
2423 #endif
2424
2425 #ifdef COMSETL
2426 #undef COMSETL
2427 SFR(COMSETL, 0xA1);
2428 #endif
2429
2430 #ifdef COR
2431 #undef COR
2432 SFR(COR, 0xCE); // Dallas DS80C390 specific
2433 #define CLKOE 0x01
2434 #define COD0 0x02
2435 #define COD1 0x04
2436 #define C0BPR6 0x08
2437 #define C0BPR7 0x10
2438 #define C1BPR6 0x20
2439 #define C1BPR7 0x40
2440 #define IRDACK 0x80
2441 #endif
2442
2443 #ifdef CRC
2444 #undef CRC
2445 SFR(CRC, 0xC1); // Dallas DS5001 specific
2446 #define CRC_ 0x01
2447 #define MDM 0x02
2448 #define RNGE0 0x10
2449 #define RNGE1 0x20
2450 #define RNGE2 0x40
2451 #define RNGE3 0x80
2452 #endif
2453
2454 #ifdef CRCH
2455 #undef CRCH
2456 SFR(CRCH, 0xCB); // compare/reload/capture register, high byte SAB80515 specific
2457 #endif
2458
2459 #ifdef CRCHIGH
2460 #undef CRCHIGH
2461 SFR(CRCHIGH, 0xC3); // DS5001 specific
2462 #endif
2463
2464 #ifdef CRCL
2465 #undef CRCL
2466 SFR(CRCL, 0xCA); // compare/reload/capture register, low byte SAB80515 specific
2467 #endif
2468
2469 #ifdef CRCLOW
2470 #undef CRCLOW
2471 SFR(CRCLOW, 0xC2); // DS5001 specific
2472 #endif
2473
2474 #ifdef CT1COM
2475 #undef CT1COM
2476 SFR(CT1COM, 0xBC);
2477 #endif
2478
2479 #ifdef CTCOM_AT_0XE1
2480 #undef CTCOM_AT_0XE1
2481 SFR(CTCON, 0xE1); // com.timer control register SAB80517
2482 #endif
2483
2484 #ifdef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2485 #undef CTCON__CTN3__CTP3__CTN2__CTP2__CTN1__CTP1__CTN0__CTP0
2486 SFR(CTCON, 0xEB); // Capture control, P80C552 specific
2487 // Not directly accessible Bits.
2488 #define CTP0 0x01
2489 #define CTN0 0x02
2490 #define CTP1 0x04
2491 #define CTN1 0x08
2492 #define CTP2 0x10
2493 #define CTN2 0x20
2494 #define CTP3 0x40
2495 #define CTN3 0x80
2496 #endif
2497
2498 #ifdef CTH0_AT_0XCC
2499 #undef CTH0_AT_0XCC
2500 SFR(CTH0, 0xCC); // Capture high 0, P80C552 specific
2501 #endif
2502
2503 #ifdef CTH1_AT_0XCD
2504 #undef CTH1_AT_0XCD
2505 SFR(CTH1, 0xCD); // Capture high 1, P80C552 specific
2506 #endif
2507
2508 #ifdef CTH2_AT_0XCE
2509 #undef CTH2_AT_0XCE
2510 SFR(CTH2, 0xCE); // Capture high 2, P80C552 specific
2511 #endif
2512
2513 #ifdef CTH3_AT_0XCF
2514 #undef CTH3_AT_0XCF
2515 SFR(CTH3, 0xCF); // Capture high 3, P80C552 specific
2516 #endif
2517
2518 #ifdef CTL0_AT_0XAC
2519 #undef CTL0_AT_0XAC
2520 SFR(CTL0, 0xAC); // Capture low 0, P80C552 specific
2521 #endif
2522
2523 #ifdef CTL1_AT_0XAD
2524 #undef CTL1_AT_0XAD
2525 SFR(CTL1, 0xAD); // Capture low 1, P80C552 specific
2526 #endif
2527
2528 #ifdef CTL2_AT_0XAE
2529 #undef CTL2_AT_0XAE
2530 SFR(CTL2, 0xAE); // Capture low 2, P80C552 specific
2531 #endif
2532
2533 #ifdef CTL3_AT_0XAF
2534 #undef CTL3_AT_0XAF
2535 SFR(CTL3, 0xAF); // Capture low 3, P80C552 specific
2536 #endif
2537
2538 #ifdef CTRELH
2539 #undef CTRELH
2540 SFR(CTRELH, 0xDF); // com.timer rel register high byte SAB80517
2541 #endif
2542
2543 #ifdef CTRELL
2544 #undef CTRELL
2545 SFR(CTRELL, 0xDE); // com.timer rel register low byte SAB80517
2546 #endif
2547
2548 #ifdef DAPR__SAB80515
2549 #undef DAPR__SAB80515
2550 SFR(DAPR, 0xDA); // D/A-converter program register SAB80515 specific
2551 #endif
2552
2553 #ifdef DAPR__SAB80517
2554 #undef DAPR__SAB80517
2555 SFR(DAPR, 0xDA); // D/A-converter program register SAB80517 specific
2556 #endif
2557
2558 #ifdef DPH
2559 #undef DPH
2560 SFR(DPH, 0x83);
2561 SFR(DP0H, 0x83); // Alternate name for AT89S53
2562 #endif
2563
2564 #ifdef DPH1
2565 #undef DPH1
2566 SFR(DPH1, 0x85); // DS80C320 specific
2567 SFR(DP1H, 0x85); // Alternate name for AT89S53
2568 #endif
2569
2570 #ifdef DPL
2571 #undef DPL
2572 SFR(DPL, 0x82); // Alternate name for AT89S53
2573 SFR(DP0L, 0x82);
2574 #endif
2575
2576 #ifdef DPL1
2577 #undef DPL1
2578 SFR(DPL1, 0x84); // DS80C320 specific
2579 SFR(DP1L, 0x84); // Alternate name for AT89S53
2580 #endif
2581
2582 #ifdef DPS__x__x__x__x__x__x__x__SEL
2583 #undef DPS__x__x__x__x__x__x__x__SEL
2584 SFR(DPS, 0x86);
2585 // Not directly accessible DPS Bit. DS80C320 & DPS8XC520 specific
2586 #define SEL 0x01
2587 #endif
2588
2589 #ifdef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2590 #undef DPS__ID1__ID0__TSL__x__x__x__x__SEL
2591 SFR(DPS, 0x86);
2592 // Not directly accessible DPS Bit. DS89C390 specific
2593 #define SEL 0x01
2594 #define TSL 0x20
2595 #define ID0 0x40
2596 #define ID1 0x80
2597 #endif
2598
2599 #ifdef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2600 #undef DPS__ID1__ID0__TSL__AID__x__x__x__SEL
2601 SFR(DPS, 0x86);
2602 // Not directly accessible DPS Bit. DS89C420 specific
2603 #define SEL 0x01
2604 #define AID 0x10
2605 #define TSL 0x20
2606 #define ID0 0x40
2607 #define ID1 0x80
2608 #endif
2609
2610 #ifdef DPSEL
2611 #undef DPSEL
2612 SFR(DPSEL, 0x92); // data pointer select register SAB80517
2613 #endif
2614
2615 #ifdef DPX
2616 #undef DPX
2617 SFR(DPX1, 0x93); // DS80C390 specific
2618 #endif
2619
2620 #ifdef DPX1
2621 #undef DPX1
2622 SFR(DPX1, 0x95); // DS80C390 specific
2623 #endif
2624
2625 #ifdef EECON
2626 #undef EECON
2627 SFR(EECON, 0xD2);
2628 #define EEBUSY 0x01
2629 #define EEE 0x02
2630 #define EEPL0 0x10
2631 #define EEPL1 0x20
2632 #define EEPL2 0x40
2633 #define EEPL3 0x80
2634 #define EEPL 0xF0
2635 #endif
2636
2637 #ifdef EETIM
2638 #undef EETIM
2639 SFR(EETIM, 0xD3);
2640 #endif
2641
2642 #ifdef EICC1
2643 #undef EICC1
2644 SFR(EICC1, 0xBF);
2645 #endif
2646
2647 #ifdef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2648 #undef EIE__x__x__x__EWDI__EX5__EX4__EX3__EX2
2649 SFR(EIE, 0xE8);
2650 // Bit registers DS80C320 specific
2651 SBIT(EX2, 0xE8, 0);
2652 SBIT(EX3, 0xE8, 1);
2653 SBIT(EX4, 0xE8, 2);
2654 SBIT(EX5, 0xE8, 3);
2655 SBIT(EWDI, 0xE8, 4);
2656 #endif
2657
2658 #ifdef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2659 #undef EIE__CANBIE__C0IE__C1IE__EWDI__EX5__EX4__EX3__EX2
2660 SFR(EIE, 0xE8);
2661 // Bit registers DS80C390 specific
2662 SBIT(EX2, 0xE8, 0);
2663 SBIT(EX3, 0xE8, 1);
2664 SBIT(EX4, 0xE8, 2);
2665 SBIT(EX5, 0xE8, 3);
2666 SBIT(EWDI, 0xE8, 4);
2667 SBIT(C1IE, 0xE8, 5);
2668 SBIT(C0IE, 0xE8, 6);
2669 SBIT(CANBIE, 0xE8, 7);
2670 #endif
2671
2672 #ifdef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2673 #undef EIP__x__x__x__PWDI__PX5__PX4__PX3__PX2
2674 SFR(EIP, 0xF8);
2675 // Bit registers DS80C320 specific
2676 SBIT(PX2, 0xF8, 0);
2677 SBIT(PX3, 0xF8, 1);
2678 SBIT(PX4, 0xF8, 2);
2679 SBIT(PX5, 0xF8, 3);
2680 SBIT(PWDI, 0xF8, 4);
2681 #endif
2682
2683 #ifdef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2684 #undef EIP__CANBIP__C0IP__C1IP__PWDI__PX5__PX4__PX3__PX2__PX1__PX0
2685 SFR(EIP, 0xF8);
2686 // Bit registers DS80C320 specific
2687 SBIT(PX2, 0xF8, 0);
2688 SBIT(PX3, 0xF8, 1);
2689 SBIT(PX4, 0xF8, 2);
2690 SBIT(PX5, 0xF8, 3);
2691 SBIT(PWDI, 0xF8, 4);
2692 SBIT(C1IP, 0xF8, 5);
2693 SBIT(C0IP, 0xF8, 6);
2694 SBIT(CANBIP, 0xF8, 7);
2695 #endif
2696
2697 #ifdef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2698 #undef EIP0__x__x__x__LPWDI__LPX5__LPX4__LPX3__LPX2
2699 SFR(EIP0, 0xF8);
2700 // Bit registers DS89C420 specific
2701 SBIT(LPX2, 0xF8, 0);
2702 SBIT(LPX3, 0xF8, 1);
2703 SBIT(LPX4, 0xF8, 2);
2704 SBIT(LPX5, 0xF8, 3);
2705 SBIT(LPWDI, 0xF8, 4);
2706 #endif
2707
2708 #ifdef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2709 #undef EIP1__x__x__x__MPWDI__MPX5__MPX4__MPX3__MPX2
2710 SFR(EIP1, 0xF1);
2711 // Not directly accessible Bits DS89C420 specific
2712 #define MPX2 0x01
2713 #define MPX3 0x02
2714 #define MPX4 0x04
2715 #define MPX5 0x08
2716 #define MPWDI 0x10
2717 #endif
2718
2719 #ifdef ESP
2720 #undef ESP
2721 SFR(ESP, 0x9B);
2722 // Not directly accessible Bits DS80C390 specific
2723 #define ESP_0 0x01
2724 #define ESP_1 0x02
2725 #endif
2726
2727 #ifdef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2728 #undef EXIF__IE5__IE4__IE3__IE2__x__RGMD__RGSL__BGS
2729 SFR(EXIF, 0x91);
2730 // Not directly accessible EXIF Bits DS80C320 specific
2731 #define BGS 0x01
2732 #define RGSL 0x02
2733 #define RGMD 0x04
2734 #define IE2 0x10
2735 #define IE3 0x20
2736 #define IE4 0x40
2737 #define IE5 0x80
2738 #endif
2739
2740 #ifdef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2741 #undef EXIF__IE5__IE4__IE3__IE2__XT_RG__RGMD__RGSL__BGS
2742 SFR(EXIF, 0x91);
2743 // Not directly accessible EXIF Bits DS87C520 specific
2744 #define BGS 0x01
2745 #define RGSL 0x02
2746 #define RGMD 0x04
2747 #define XT_RG 0x08
2748 #define IE2 0x10
2749 #define IE3 0x20
2750 #define IE4 0x40
2751 #define IE5 0x80
2752 #endif
2753
2754 #ifdef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2755 #undef EXIF__IE5__IE4__IE3__IE2__CKRY__RGMD__RGSL__BGS
2756 SFR(EXIF, 0x91);
2757 // Not directly accessible EXIF Bits DS80C390 & DS89C420 specific
2758 #define BGS 0x01
2759 #define RGSL 0x02
2760 #define RGMD 0x04
2761 #define CKRY 0x08
2762 #define IE2 0x10
2763 #define IE3 0x20
2764 #define IE4 0x40
2765 #define IE5 0x80
2766 #endif
2767
2768 #ifdef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2769 #undef FCNTL__FBUSY__FERR__x__x__FC3__FC2__FC1__FC0
2770 SFR(FCNTL, 0xD5);
2771 // Not directly accessible DS89C420 specific
2772 #define FC0 0x01
2773 #define FC1 0x02
2774 #define FC2 0x04
2775 #define FC3 0x08
2776 #define FERR 0x40
2777 #define FBUSY 0x80
2778 #endif
2779
2780 #ifdef FCON
2781 #undef FCON
2782 SFR(FCON, 0xD1);
2783 #define FBUSY 0x01
2784 #define FMOD0 0x02
2785 #define FMOD1 0x04
2786 #define FPS 0x08
2787 #define FPL0 0x10
2788 #define FPL1 0x20
2789 #define FPL2 0x40
2790 #define FPL3 0x80
2791 #define FPL 0xF0
2792 #endif
2793
2794 #ifdef FDATA
2795 #undef FDATA
2796 SFR(FDATA, 0xD6);
2797 #endif
2798
2799 #ifdef FMODE
2800 #undef FMODE
2801 SFR(FMODE, 0xB3);
2802 #endif
2803
2804 #ifdef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2805 #undef IE__EA__x__x__ES__ET1__EX1__ET0__EX0
2806 SFR(IE, 0xA8);
2807 // Bit registers
2808 SBIT(EX0, 0xA8, 0);
2809 SBIT(ET0, 0xA8, 1);
2810 SBIT(EX1, 0xA8, 2);
2811 SBIT(ET1, 0xA8, 3);
2812 SBIT(ES, 0xA8, 4);
2813 SBIT(EA, 0xA8, 7);
2814 #endif
2815
2816 #ifdef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2817 #undef IE__EA__x__ET2__ES__ET1__EX1__ET0__EX0
2818 SFR(IE, 0xA8);
2819 // Bit registers
2820 SBIT(EX0, 0xA8, 0);
2821 SBIT(ET0, 0xA8, 1);
2822 SBIT(EX1, 0xA8, 2);
2823 SBIT(ET1, 0xA8, 3);
2824 SBIT(ES, 0xA8, 4);
2825 SBIT(ET2, 0xA8, 5); // Enable timer2 interrupt
2826 SBIT(EA, 0xA8, 7);
2827 #endif // IE
2828
2829 #ifdef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2830 #undef IE__EA__EAD__ES1__ES0__ET1__EX1__ET0__EX0
2831 SFR(IE, 0xA8); // same as IEN0 - Interrupt enable 0, P80C552 specific
2832 SFR(IEN0, 0xA8); // alternate name
2833 // Bit registers
2834 SBIT(EX0, 0xA8, 0);
2835 SBIT(ET0, 0xA8, 1);
2836 SBIT(EX1, 0xA8, 2);
2837 SBIT(ET1, 0xA8, 3);
2838 SBIT(ES0, 0xA8, 4);
2839 SBIT(ES1, 0xA8, 5);
2840 SBIT(EAD, 0xA8, 6);
2841 SBIT(EEA, 0xA8, 7);
2842 #endif
2843
2844 #ifdef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2845 #undef IE__EA__EC__ET2__ES__ET1__EX1__ET0__EX0
2846 SFR(IE, 0xA8);
2847 // Bit registers
2848 SBIT(EX0, 0xA8, 0);
2849 SBIT(ET0, 0xA8, 1);
2850 SBIT(EX1, 0xA8, 2);
2851 SBIT(ET1, 0xA8, 3);
2852 SBIT(ES, 0xA8, 4);
2853 SBIT(ET2, 0xA8, 5);
2854 SBIT(EC, 0xA8, 6);
2855 SBIT(EA, 0xA8, 7);
2856 #endif
2857
2858 #ifdef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2859 #undef IE__EA__ES1__ET2__ES__ET1__EX1__ET0__EX0
2860 SFR(IE, 0xA8);
2861 // Bit registers
2862 SBIT(EX0, 0xA8, 0);
2863 SBIT(ET0, 0xA8, 1);
2864 SBIT(EX1, 0xA8, 2);
2865 SBIT(ET1, 0xA8, 3);
2866 SBIT(ES, 0xA8, 4);
2867 SBIT(ES0, 0xA8, 4); // Alternate name
2868 SBIT(ET2, 0xA8, 5); // Enable timer2 interrupt
2869 SBIT(ES1, 0xA8, 6);
2870 SBIT(EA, 0xA8, 7);
2871 #endif // IE
2872
2873 #ifdef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2874 #undef IE__EA_WDT_ET2_ES_ET1_EX1_ET0_EX0
2875 SFR(IE, 0xA8);
2876 SFR(IEN0, 0xA8); // Alternate name
2877 // Bit registers for the SAB80515 and compatible IE
2878 SBIT(EX0, 0xA8, 0);
2879 SBIT(ET0, 0xA8, 1);
2880 SBIT(EX1, 0xA8, 2);
2881 SBIT(ET1, 0xA8, 3);
2882 SBIT(ES, 0xA8, 4);
2883 SBIT(ES0, 0xA8, 4);
2884 SBIT(ET2, 0xA8, 5); // Enable timer 2 overflow SAB80515 specific
2885 SBIT(WDT, 0xA8, 6); // watchdog timer reset - SAB80515 specific
2886 SBIT(EA, 0xA8, 7);
2887 SBIT(EAL, 0xA8, 7); // EA as called by Infineon / Siemens
2888 #endif
2889
2890 #ifdef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2891 #undef IEN0__EA__EC__ES1__ES0__ET1__EX1__ET0__EX0
2892 // P89C668 specific
2893 SFR(IEN0, 0xA8);
2894 // Bit registers
2895 SBIT(EX0, 0xA8, 0);
2896 SBIT(ET0, 0xA8, 1);
2897 SBIT(EX1, 0xA8, 2);
2898 SBIT(ET1, 0xA8, 3);
2899 SBIT(ES0, 0xA8, 4);
2900 SBIT(ES1, 0xA8, 5);
2901 SBIT(EC, 0xA8, 6);
2902 SBIT(EA, 0xA8, 7);
2903 #endif
2904
2905 #ifdef IEN1__x__x__x__x__x__x__x__ET2
2906 #undef IEN1__x__x__x__x__x__x__x__ET2
2907 // P89C668 specific bit registers
2908 SFR(IEN1, 0xE8);
2909 // Bit registers
2910 SBIT(ET2, 0xE8, 0);
2911 #endif
2912
2913 #ifdef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2914 #undef IEN1__ET2__ECM2__ECM1__ECM0__ECT3__ECT2__ECT1__ECT0
2915 SFR(IEN1, 0xE8); // Interrupt enable 1, P80C552 specific
2916 // Bit registers
2917 SBIT(ECT0, 0xE8, 0);
2918 SBIT(ECT1, 0xE8, 1);
2919 SBIT(ECT2, 0xE8, 2);
2920 SBIT(ECT3, 0xE8, 3);
2921 SBIT(ECM0, 0xE8, 4);
2922 SBIT(ECM1, 0xE8, 5);
2923 SBIT(ECM2, 0xE8, 6);
2924 SBIT(ET2, 0xE8, 7);
2925 #endif
2926
2927 #ifdef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2928 #undef IEN1__EXEN2__SWDT__EX6__EX5__EX4__EX3__EX2__EADC
2929 SFR(IEN1, 0xB8); // interrupt enable register - SAB80515 specific
2930 // Bit registers
2931 SBIT(EADC, 0xB8, 0); // A/D converter interrupt enable
2932 SBIT(EX2, 0xB8, 1);
2933 SBIT(EX3, 0xB8, 2);
2934 SBIT(EX4, 0xB8, 3);
2935 SBIT(EX5, 0xB8, 4);
2936 SBIT(EX6, 0xB8, 5);
2937 SBIT(SWDT, 0xB8, 6); // watchdog timer start/reset
2938 SBIT(EXEN2, 0xB8, 7); // timer2 external reload interrupt enable
2939 #endif
2940
2941 #ifdef IEN2__SAB80517
2942 #undef IEN2__SAB80517
2943 SFR(IEN2, 0x9A); // interrupt enable register 2 SAB80517
2944 #endif
2945
2946 #ifdef IEN3
2947 #undef IEN3
2948 SFR(IEN3, 0xBE);
2949 #endif
2950
2951 #ifdef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2952 #undef IP__x__x__x__PS__PT1__PX1__PT0__PX0
2953 SFR(IP, 0xB8);
2954 // Bit registers
2955 SBIT(PX0, 0xB8, 0);
2956 SBIT(PT0, 0xB8, 1);
2957 SBIT(PX1, 0xB8, 2);
2958 SBIT(PT1, 0xB8, 3);
2959 SBIT(PS, 0xB8, 4);
2960 #endif
2961
2962 #ifdef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2963 #undef IP__x__x__PT2__PS__PT1__PX1__PT0__PX0
2964 SFR(IP, 0xB8);
2965 // Bit registers
2966 SBIT(PX0, 0xB8, 0);
2967 SBIT(PT0, 0xB8, 1);
2968 SBIT(PX1, 0xB8, 2);
2969 SBIT(PT1, 0xB8, 3);
2970 SBIT(PS, 0xB8, 4);
2971 SBIT(PS0, 0xB8, 4); // alternate name
2972 SBIT(PT2, 0xB8, 5);
2973 #endif
2974
2975 #ifdef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2976 #undef IP__x__PAD__PS1__PS0__PT1__PX1__PT0__PX0
2977 SFR(IP, 0xB8); // Interrupt priority 0, P80C552 specific
2978 SFR(IP0, 0xB8); // alternate name
2979 // Bit registers
2980 SBIT(PX0, 0xB8, 0);
2981 SBIT(PT0, 0xB8, 1);
2982 SBIT(PX1, 0xB8, 2);
2983 SBIT(PT1, 0xB8, 3);
2984 SBIT(PS0, 0xB8, 4);
2985 SBIT(PS1, 0xB8, 5);
2986 SBIT(PAD, 0xB8, 6);
2987 #endif
2988
2989 #ifdef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2990 #undef IP__x__PPC__PT2__PS__PT1__PX1__PT0__PX0
2991 SFR(IP, 0xB8);
2992 // Bit registers
2993 SBIT(PX0, 0xB8, 0);
2994 SBIT(PT0, 0xB8, 1);
2995 SBIT(PX1, 0xB8, 2);
2996 SBIT(PT1, 0xB8, 3);
2997 SBIT(PS, 0xB8, 4);
2998 SBIT(PT2, 0xB8, 5);
2999 SBIT(PPC, 0xB8, 6);
3000 #endif
3001
3002 #ifdef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
3003 #undef IP__x__PS1__PT2__PS__PT1_PX1__PT0__PX0
3004 SFR(IP, 0xB8);
3005 // Bit registers
3006 SBIT(PX0, 0xB8, 0);
3007 SBIT(PT0, 0xB8, 1);
3008 SBIT(PX1, 0xB8, 2);
3009 SBIT(PT1, 0xB8, 3);
3010 SBIT(PS, 0xB8, 4);
3011 SBIT(PT2, 0xB8, 5);
3012 SBIT(PS1, 0xB8, 6);
3013 #endif
3014
3015 #ifdef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
3016 #undef IP__PT2__PPC__PS1__PS0__PT1__PX1__PT0__PX0
3017 // P89C668 specific:
3018 SFR(IP, 0xB8);
3019 // Bit registers
3020 SBIT(PX0, 0xB8, 0);
3021 SBIT(PT0, 0xB8, 1);
3022 SBIT(PX1, 0xB8, 2);
3023 SBIT(PT1, 0xB8, 3);
3024 SBIT(PS0, 0xB8, 4);
3025 SBIT(PS1, 0xB8, 5);
3026 SBIT(PPC, 0xB8, 6);
3027 SBIT(PT2, 0xB8, 7);
3028 #endif
3029
3030 #ifdef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
3031 #undef IP__RWT__x__x__PS__PT1__PX1__PT0__PX0
3032 SFR(IP, 0xB8);
3033 // Bit registers
3034 SBIT(PX0, 0xB8, 0);
3035 SBIT(PT0, 0xB8, 1);
3036 SBIT(PX1, 0xB8, 2);
3037 SBIT(PT1, 0xB8, 3);
3038 SBIT(PS, 0xB8, 4);
3039 SBIT(RWT, 0xB8, 7);
3040 #endif
3041
3042 #ifdef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
3043 #undef IP0__x__WDTS__IP0_5__IP0_4__IP0_3__IP0_2__IP0_1__IP0_0
3044 SFR(IP0, 0xA9); // interrupt priority register SAB80515 specific
3045 // Not directly accessible IP0 bits
3046 #define IP0_0 0x01
3047 #define IP0_1 0x02
3048 #define IP0_2 0x04
3049 #define IP0_3 0x08
3050 #define IP0_4 0x10
3051 #define IP0_5 0x20
3052 #define WDTS 0x40
3053 #endif
3054
3055 #ifdef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
3056 #undef IP0__x__LPS1__LPT2__LPS0__LPT1__LPX1__LPT0__LPX0
3057 SFR(IP0, 0xB8); // interrupt priority register DS89C420 specific
3058 // Bit registers
3059 SBIT(LPX0, 0xB8, 0);
3060 SBIT(LPT0, 0xB8, 1);
3061 SBIT(LPX1, 0xB8, 2);
3062 SBIT(LPT1, 0xB8, 3);
3063 SBIT(LPS0, 0xB8, 4);
3064 SBIT(LPT2, 0xB8, 5);
3065 SBIT(LPS1, 0xB8, 6);
3066 #endif
3067
3068 #ifdef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
3069 #undef IP1__x__x__IP1_5__IP1_4__IP1_3__IP1_2__IP1_1__IP1_0
3070 SFR(IP1, 0xB9); // interrupt priority register SAB80515 specific
3071 // Not directly accessible IP1 bits
3072 #define IP1_0 0x01
3073 #define IP1_1 0x02
3074 #define IP1_2 0x04
3075 #define IP1_3 0x08
3076 #define IP1_4 0x10
3077 #define IP1_5 0x20
3078 #endif
3079
3080 #ifdef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
3081 #undef IP1__x__MPS1__MPT2__MPS0__MPT1__MPX1__MPT0__MPX0
3082 SFR(IP1, 0xB1); // interrupt priority register DS89C420 specific
3083 // Not directly accessible IP1 bits
3084 #define MPX0 0x01
3085 #define MPT0 0x02
3086 #define MPX1 0x04
3087 #define MPT1 0x08
3088 #define MPS0 0x10
3089 #define MPT2 0x20
3090 #define MPS1 0x40
3091 #endif
3092
3093 #ifdef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
3094 #undef IP1__PT2__PCM2__PCM1__PCM0__PCT3__PCT2__PCT1__PCT0
3095 SFR(IP1, 0xF8); // Interrupt priority 1, P80C552 specific
3096 // Bit registers
3097 SBIT(PCT0, 0xF8, 0);
3098 SBIT(PCT1, 0xF8, 1);
3099 SBIT(PCT2, 0xF8, 2);
3100 SBIT(PCT3, 0xF8, 3);
3101 SBIT(PCM0, 0xF8, 4);
3102 SBIT(PCM1, 0xF8, 5);
3103 SBIT(PCM2, 0xF8, 6);
3104 SBIT(PT2, 0xF8, 7);
3105 #endif
3106
3107 #ifdef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
3108 #undef IPH__x__PPCH__PT2H__PSH__PT1H__PX1H__PT0H__PX0H
3109 SFR(IPH, 0xB7);
3110 #define PX0H 0x01
3111 #define PT0H 0x02
3112 #define PX1H 0x04
3113 #define PT1H 0x08
3114 #define PSH 0x10
3115 #define PT2H 0x20
3116 #define PPCH 0x40
3117 #endif
3118
3119 #ifdef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
3120 #undef IPH__PT2H__PPCH__PS1H__PS0H__PT1H__PX1H__PT0H__PX0H
3121 // P89C668 specific:
3122 SFR(IPH, 0xB7);
3123 // not bit addressable:
3124 #define PX0H 0x01
3125 #define PT0H 0x02
3126 #define PX1H 0x04
3127 #define PT1H 0x08
3128 #define PS0H 0x10
3129 #define PS1H 0x20
3130 #define PPCH 0x40
3131 #define PT2H 0x80
3132 #endif
3133
3134 #ifdef IRCON
3135 #undef IRCON
3136 SFR(IRCON, 0xC0); // interrupt control register - SAB80515 specific
3137 // Bit registers
3138 SBIT(IADC, 0xC0, 0); // A/D converter irq flag
3139 SBIT(IEX2, 0xC0, 1); // external interrupt edge detect flag
3140 SBIT(IEX3, 0xC0, 2);
3141 SBIT(IEX4, 0xC0, 3);
3142 SBIT(IEX5, 0xC0, 4);
3143 SBIT(IEX6, 0xC0, 5);
3144 SBIT(TF2, 0xC0, 6); // timer 2 owerflow flag
3145 SBIT(EXF2, 0xC0, 7); // timer2 reload flag
3146 #endif
3147
3148 #ifdef IRCON0
3149 #undef IRCON0
3150 SFR(IRCON0, 0xC0); // interrupt control register - SAB80515 specific
3151 // Bit registers
3152 SBIT(IADC, 0xC0, 0); // A/D converter irq flag
3153 SBIT(IEX2, 0xC0, 1); // external interrupt edge detect flag
3154 SBIT(IEX3, 0xC0, 2);
3155 SBIT(IEX4, 0xC0, 3);
3156 SBIT(IEX5, 0xC0, 4);
3157 SBIT(IEX6, 0xC0, 5);
3158 SBIT(TF2, 0xC0, 6); // timer 2 owerflow flag
3159 SBIT(EXF2, 0xC0, 7); // timer2 reload flag
3160 #endif
3161
3162 #ifdef IRCON1
3163 #undef IRCON1
3164 SFR(IRCON1, 0xD1); // interrupt control register - SAB80515 specific
3165 #endif
3166
3167 #ifdef IRCON2
3168 #undef IRCON2
3169 SFR(IRCON2, 0xBF);
3170 #endif
3171
3172 #ifdef MA
3173 #undef MA
3174 SFR(MA, 0xD3); // DS80C390
3175 #endif
3176
3177 #ifdef MB
3178 #undef MB
3179 SFR(MB, 0xD4); // DS80C390
3180 #endif
3181
3182 #ifdef MC
3183 #undef MC
3184 SFR(MC, 0xD5); // DS80C390
3185 #endif
3186
3187 #ifdef MCNT0
3188 #undef MCNT0
3189 SFR(MCNT0, 0xD1); // DS80C390
3190 #define MAS0 0x01
3191 #define MAS1 0x02
3192 #define MAS2 0x04
3193 #define MAS3 0x08
3194 #define MAS4 0x10
3195 #define SCB 0x20
3196 #define CSE 0x40
3197 #define LSHIFT 0x80
3198 #endif
3199
3200 #ifdef MCNT1
3201 #undef MCNT1
3202 SFR(MCNT1, 0xD2); // DS80C390
3203 #define CLM 0x10
3204 #define MOF 0x40
3205 #define MST 0x80
3206 #endif
3207
3208 #ifdef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
3209 #undef MCON__IDM1__IDM0__CMA__x__PDCE3__PDCE2__PDCE1__PDCE0
3210 SFR(MCON, 0xC6); // DS80C390
3211 #define PDCE0 0x01
3212 #define PDCE1 0x02
3213 #define PDCE2 0x04
3214 #define PDCE3 0x08
3215 #define CMA 0x20
3216 #define IDM0 0x40
3217 #define IDM1 0x80
3218 #endif
3219
3220 #ifdef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
3221 #undef MCON__PA3__PA2__PA1__PA0__RA32_8__ECE2__PAA__SL
3222 SFR(MCON, 0xC6); // DS5000
3223 #define SL 0x01
3224 #define PAA 0x02
3225 #define ECE2 0x04
3226 #define RA32_8 0x08
3227 #define PA0 0x10
3228 #define PA1 0x20
3229 #define PA2 0x40
3230 #define PA3 0x80
3231 #endif
3232
3233 #ifdef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3234 #undef MCON__PA3__PA2__PA1__PA0__RG1__PES__PM__SL
3235 SFR(MCON, 0xC6); // DS5001
3236 #define SL 0x01
3237 #define PM 0x02
3238 #define PES 0x04
3239 #define RG1 0x08
3240 #define PA0 0x10
3241 #define PA1 0x20
3242 #define PA2 0x40
3243 #define PA3 0x80
3244 #endif
3245
3246 #ifdef MD0
3247 #undef MD0
3248 SFR(MD0, 0xE9); // MUL / DIV register 0 SAB80517
3249 #endif
3250
3251 #ifdef MD1
3252 #undef MD1
3253 SFR(MD1, 0xEA); // MUL / DIV register 1 SAB80517
3254 #endif
3255
3256 #ifdef MD2
3257 #undef MD2
3258 SFR(MD2, 0xEB); // MUL / DIV register 2 SAB80517
3259 #endif
3260
3261 #ifdef MD3
3262 #undef MD3
3263 SFR(MD3, 0xEC); // MUL / DIV register 3 SAB80517
3264 #endif
3265
3266 #ifdef MD4
3267 #undef MD4
3268 SFR(MD4, 0xED); // MUL / DIV register 4 SAB80517
3269 #endif
3270
3271 #ifdef MD5
3272 #undef MD5
3273 SFR(MD5, 0xEE); // MUL / DIV register 5 SAB80517
3274 #endif
3275
3276 #ifdef MXAX
3277 #undef MXAX
3278 SFR(MXAX, 0xEA); // Dallas DS80C390
3279 #endif
3280
3281 #ifdef P0
3282 #undef P0
3283 SFR(P0, 0x80);
3284 // Bit Registers
3285 SBIT(P0_0, 0x80, 0);
3286 SBIT(P0_1, 0x80, 1);
3287 SBIT(P0_2, 0x80, 2);
3288 SBIT(P0_3, 0x80, 3);
3289 SBIT(P0_4, 0x80, 4);
3290 SBIT(P0_5, 0x80, 5);
3291 SBIT(P0_6, 0x80, 6);
3292 SBIT(P0_7, 0x80, 7);
3293 #endif
3294
3295 #ifdef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3296 #undef P0_EXT__AD7__AD6__AD5__AD4__AD3__AD2__AD1__AD0
3297 // P89C668 alternate names for bits in P0
3298 SBIT(AD0, 0x80, 0);
3299 SBIT(AD1, 0x80, 1);
3300 SBIT(AD2, 0x80, 2);
3301 SBIT(AD3, 0x80, 3);
3302 SBIT(AD4, 0x80, 4);
3303 SBIT(AD5, 0x80, 5);
3304 SBIT(AD6, 0x80, 6);
3305 SBIT(AD7, 0x80, 7);
3306 #endif
3307
3308 #ifdef P1
3309 #undef P1
3310 SFR(P1, 0x90);
3311 // Bit registers
3312 SBIT(P1_0, 0x90, 0);
3313 SBIT(P1_1, 0x90, 1);
3314 SBIT(P1_2, 0x90, 2);
3315 SBIT(P1_3, 0x90, 3);
3316 SBIT(P1_4, 0x90, 4);
3317 SBIT(P1_5, 0x90, 5);
3318 SBIT(P1_6, 0x90, 6);
3319 SBIT(P1_7, 0x90, 7);
3320 #endif
3321
3322 #ifdef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3323 #undef P1_EXT__INT5__INT4__INT3__INT2__TXD1__RXD1__T2EX__T2
3324 // P1 alternate functions
3325 SBIT(T2, 0x90, 0);
3326 SBIT(T2EX, 0x90, 1);
3327 SBIT(RXD1, 0x90, 2);
3328 SBIT(TXD1, 0x90, 3);
3329 SBIT(INT2, 0x90, 4);
3330 SBIT(INT3, 0x90, 5);
3331 SBIT(INT4, 0x90, 6);
3332 SBIT(INT5, 0x90, 7);
3333 #endif
3334
3335 #ifdef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3336 #undef P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3337 // P89C669 alternate names for bits __at P1
3338 // P1_EXT__SDA__SCL__CEX2__CEX1__CEX0__ECI__T2EX__T2
3339 SBIT(T2, 0x90, 0);
3340 SBIT(T2EX, 0x90, 1);
3341 SBIT(ECI, 0x90, 2);
3342 SBIT(CEX0, 0x90, 3);
3343 SBIT(CEX1, 0x90, 4);
3344 SBIT(CEX2, 0x90, 5);
3345 SBIT(SCL, 0x90, 6);
3346 SBIT(SDA, 0x90, 7);
3347 #endif
3348
3349 #ifdef P1_EXT__T2__CLKOUT__T2EX__INT2__INT6_CC3__INT5_CC2__INT4_CC1__INT3_CC0
3350 SBIT(INT3_CC0, 0x90, 0); // P1 alternate functions - SAB80515 specific
3351 SBIT(INT4_CC1, 0x90, 1);
3352 SBIT(INT5_CC2, 0x90, 2);
3353 SBIT(INT6_CC3, 0x90, 3);
3354 SBIT(INT2, 0x90, 4);
3355 SBIT(T2EX, 0x90, 5);
3356 SBIT(CLKOUT, 0x90, 6);
3357 SBIT(T2, 0x90, 7);
3358 #endif
3359
3360 #ifdef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3361 #undef P1_EXT__CT0I__CT1I__CT2I__CT3I__T2__RT2__SCL__SDA
3362 // Bit registers
3363 SBIT(CT0I, 0x90, 0); // Port 1 alternate functions, P80C552 specific
3364 SBIT(CT1I, 0x90, 1);
3365 SBIT(CT2I, 0x90, 2);
3366 SBIT(CT3I, 0x90, 3);
3367 SBIT(T2, 0x90, 4);
3368 SBIT(RT2, 0x90, 5);
3369 SBIT(SCL, 0x90, 6);
3370 SBIT(SDA, 0x90, 7);
3371 #endif
3372
3373 #ifdef P1_EXT__x__x__x__x__x__x__T2EX__T2
3374 #undef P1_EXT__x__x__x__x__x__x__T2EX__T2
3375 // P1 alternate functions
3376 SBIT(T2, 0x90, 0);
3377 SBIT(T2EX, 0x90, 1);
3378 #endif
3379
3380 #ifdef P2
3381 #undef P2
3382 SFR(P2, 0xA0);
3383 // Bit registers
3384 SBIT(P2_0, 0xA0, 0);
3385 SBIT(P2_1, 0xA0, 1);
3386 SBIT(P2_2, 0xA0, 2);
3387 SBIT(P2_3, 0xA0, 3);
3388 SBIT(P2_4, 0xA0, 4);
3389 SBIT(P2_5, 0xA0, 5);
3390 SBIT(P2_6, 0xA0, 6);
3391 SBIT(P2_7, 0xA0, 7);
3392 #endif
3393
3394 #ifdef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3395 #undef P2_EXT__AD15__AD14__AD13__AD12__AD11__AD10__AD9__AD8
3396 // P89C668 specific bit registers __at P2:
3397 SBIT(AD8, 0xA0, 0);
3398 SBIT(AD9, 0xA0, 1);
3399 SBIT(AD10, 0xA0, 2);
3400 SBIT(AD11, 0xA0, 3);
3401 SBIT(AD12, 0xA0, 4);
3402 SBIT(AD13, 0xA0, 5);
3403 SBIT(AD14, 0xA0, 6);
3404 SBIT(AD15, 0xA0, 7);
3405 #endif
3406
3407 #ifdef P3
3408 #undef P3
3409 SFR(P3, 0xB0);
3410 // Bit registers
3411 SBIT(P3_0, 0xB0, 0);
3412 SBIT(P3_1, 0xB0, 1);
3413 SBIT(P3_2, 0xB0, 2);
3414 SBIT(P3_3, 0xB0, 3);
3415 SBIT(P3_4, 0xB0, 4);
3416 SBIT(P3_5, 0xB0, 5);
3417 #ifndef MCS51REG_EXTERNAL_RAM
3418 SBIT(P3_6, 0xB0, 6);
3419 SBIT(P3_7, 0xB0, 7);
3420 #endif
3421 // alternate names
3422 SBIT(RXD, 0xB0, 0);
3423 SBIT(RXD0, 0xB0, 0);
3424 SBIT(TXD, 0xB0, 1);
3425 SBIT(TXD0, 0xB0, 1);
3426 SBIT(INT0, 0xB0, 2);
3427 SBIT(INT1, 0xB0, 3);
3428 SBIT(T0, 0xB0, 4);
3429 SBIT(T1, 0xB0, 5);
3430 #ifndef MCS51REG_EXTERNAL_RAM
3431 SBIT(WR, 0xB0, 6);
3432 SBIT(RD, 0xB0, 7);
3433 #endif
3434 #endif
3435
3436 #ifdef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3437 #undef P3_EXT__x__x__CEX4__CEX3__x__x__x__x
3438 // P89C668 specific bit registers __at P3 (alternate names)
3439 SBIT(CEX4, 0xB0, 5);
3440 SBIT(CEX3, 0xB0, 4);
3441 #endif
3442
3443 #ifdef P4_AT_0X80
3444 #undef P4_AT_0X80
3445 SFR(P4, 0x80); // Port 4 - DS80C390
3446 // Bit registers
3447 SBIT(P4_0, 0x80, 0);
3448 SBIT(P4_1, 0x80, 1);
3449 SBIT(P4_2, 0x80, 2);
3450 SBIT(P4_3, 0x80, 3);
3451 SBIT(P4_4, 0x80, 4);
3452 SBIT(P4_5, 0x80, 5);
3453 SBIT(P4_6, 0x80, 6);
3454 SBIT(P4_7, 0x80, 7);
3455 #endif
3456
3457 #ifdef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3458 #undef P4_AT_0XC0__CMT0__CMT1__CMSR5__CMSR4__CMSR3__CMSR2__CMSR1__CMSR0
3459 SFR(P4, 0xC0); // Port 4, P80C552 specific
3460 // Bit registers
3461 SBIT(CMSR0, 0xC0, 0);
3462 SBIT(CMSR1, 0xC0, 1);
3463 SBIT(CMSR2, 0xC0, 2);
3464 SBIT(CMSR3, 0xC0, 3);
3465 SBIT(CMSR4, 0xC0, 4);
3466 SBIT(CMSR5, 0xC0, 5);
3467 SBIT(CMT0, 0xC0, 6);
3468 SBIT(CMT1, 0xC0, 7);
3469 #endif
3470
3471 #ifdef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3472 #undef P4_AT_0XC0__P4_7__P4_6__P4_5__P4_3__P4_2__P4_1__P4_0
3473 SFR(P4, 0xC0); // Port 4, T89C51 specific
3474 // Bit registers
3475 SBIT(P4_0, 0xC0, 0);
3476 SBIT(P4_1, 0xC0, 1);
3477 SBIT(P4_2, 0xC0, 2);
3478 SBIT(P4_3, 0xC0, 3);
3479 SBIT(P4_4, 0xC0, 4);
3480 SBIT(P4_5, 0xC0, 5);
3481 SBIT(P4_6, 0xC0, 6);
3482 SBIT(P4_7, 0xC0, 7);
3483 #endif
3484
3485 #ifdef P4_AT_0XE8
3486 #undef P4_AT_0XE8
3487 SFR(P4, 0xE8); // Port 4 - SAB80515 & compatible microcontrollers
3488 // Bit registers
3489 SBIT(P4_0, 0xE8, 0);
3490 SBIT(P4_1, 0xE8, 1);
3491 SBIT(P4_2, 0xE8, 2);
3492 SBIT(P4_3, 0xE8, 3);
3493 SBIT(P4_4, 0xE8, 4);
3494 SBIT(P4_5, 0xE8, 5);
3495 SBIT(P4_6, 0xE8, 6);
3496 SBIT(P4_7, 0xE8, 7);
3497 #endif
3498
3499 #ifdef P4CNT
3500 #undef P4CNT
3501 SFR(P4CNT, 0x92); // DS80C390
3502 // Not directly accessible bits
3503 #define P4CNT_0 0x01
3504 #define P4CNT_1 0x02
3505 #define P4CNT_2 0x04
3506 #define P4CNT_3 0x08
3507 #define P4CNT_4 0x10
3508 #define P4CNT_5 0x20
3509 #define SBCAN 0x40
3510 #endif
3511
3512 #ifdef P5_AT_0XA1
3513 #undef P5_AT_0XA1
3514 SFR(P5, 0xA1); // Port 5 - DS80C390
3515 #endif
3516
3517 #ifdef P5_AT_0XE8
3518 #undef P5_AT_0XE8
3519 SFR(P5, 0xE8); // Port 5 - T89C51RD2
3520 // Bit registers
3521 SBIT(P5_0, 0xE8, 0);
3522 SBIT(P5_1, 0xE8, 1);
3523 SBIT(P5_2, 0xE8, 2);
3524 SBIT(P5_3, 0xE8, 3);
3525 SBIT(P5_4, 0xE8, 4);
3526 SBIT(P5_5, 0xE8, 5);
3527 SBIT(P5_6, 0xE8, 6);
3528 SBIT(P5_7, 0xE8, 7);
3529 #endif
3530
3531 #ifdef P5CNT
3532 #undef P5CNT
3533 SFR(P5CNT, 0xA2); // DS80C390
3534 // Not directly accessible bits
3535 #define P5CNT_0 0x01
3536 #define P5CNT_1 0x02
3537 #define P5CNT_2 0x04
3538 #define C0_I_O 0x08
3539 #define C1_I_O 0x10
3540 #define SP1EC 0x20
3541 #define SBCAN0BA 0x40
3542 #define SBCAN1BA 0x80
3543 #endif
3544
3545 #ifdef P5_AT_0XC4
3546 #undef P5_AT_0XC4
3547 SFR(P5, 0xC4); // Port 5, P80C552 specific
3548 // Not directly accessible Bits.
3549 #define ADC0 0x01
3550 #define ADC1 0x02
3551 #define ADC2 0x04
3552 #define ADC3 0x08
3553 #define ADC4 0x10
3554 #define ADC5 0x20
3555 #define ADC6 0x40
3556 #define ADC7 0x80
3557 #endif
3558
3559 #ifdef P5_AT_0XF8
3560 #undef P5_AT_0XF8
3561 SFR(P5, 0xF8); // Port 5 - SAB80515 & compatible microcontrollers
3562 // Bit registers
3563 SBIT(P5_0, 0xF8, 0);
3564 SBIT(P5_1, 0xF8, 1);
3565 SBIT(P5_2, 0xF8, 2);
3566 SBIT(P5_3, 0xF8, 3);
3567 SBIT(P5_4, 0xF8, 4);
3568 SBIT(P5_5, 0xF8, 5);
3569 SBIT(P5_6, 0xF8, 6);
3570 SBIT(P5_7, 0xF8, 7);
3571 #endif
3572
3573 #ifdef P6_AT_0XDB
3574 #undef P6_AT_0XDB
3575 SFR(P6, 0xDB); // Port 6 - SAB80515 & compatible microcontrollers
3576 #endif
3577
3578 #ifdef P6_AT_0XFA
3579 #undef P6_AT_0XFA
3580 SFR(P6, 0xFA); // Port 6 - SAB80517 specific
3581 #endif
3582
3583 #ifdef P7_AT_0XDB
3584 #undef P7_AT_0XDB
3585 SFR(P7, 0xDB); // Port 7 - SAB80517 specific
3586 #endif
3587
3588 #ifdef P8_AT_0XDD
3589 #undef P8_AT_0XDD
3590 SFR(P8, 0xDD); // Port 6 - SAB80517 specific
3591 #endif
3592
3593 #ifdef P9_AT_0XF9
3594 #undef P9_AT_0XF9
3595 SFR(P9, 0xF9);
3596 #endif
3597
3598 #ifdef PCON__SMOD__x__x__x__x__x__x__x
3599 #undef PCON__SMOD__x__x__x__x__x__x__x
3600 SFR(PCON, 0x87);
3601 // Not directly accessible PCON bits
3602 #define SMOD 0x80
3603 #endif
3604
3605 #ifdef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3606 #undef PCON__SMOD__x__x__x__GF1__GF0__PD__IDL
3607 SFR(PCON, 0x87);
3608 // Not directly accessible PCON bits
3609 #define IDL 0x01
3610 #define PD 0x02
3611 #define GF0 0x04
3612 #define GF1 0x08
3613 #define SMOD 0x80
3614 #endif
3615
3616 #ifdef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3617 #undef PCON__SMOD__x__x__WLE__GF1__GF0__PD__IDL
3618 SFR(PCON, 0x87); // PCON, P80C552 specific
3619 // Not directly accessible Bits.
3620 #define IDL 0x01
3621 #define IDLE 0x01 /* same as IDL */
3622 #define PD 0x02
3623 #define GF0 0x04
3624 #define GF1 0x08
3625 #define WLE 0x10
3626 #define SMOD 0x80
3627 #endif
3628
3629 #ifdef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3630 #undef PCON__SMOD__PDS__IDLS__x__x__x__PD__IDL
3631 SFR(PCON, 0x87);
3632 // Not directly accessible PCON bits
3633 #define IDL 0x01
3634 #define IDLE 0x01 /* same as IDL */
3635 #define PD 0x02
3636 #define PDE 0x02 /* same as PD */
3637 #define IDLS 0x20
3638 #define PDS 0x40
3639 #define SMOD 0x80
3640 // alternate names
3641 #define PCON_IDLE 0x01
3642 #define PCON_PDE 0x02
3643 #define PCON_GF0 0x04
3644 #define PCON_GF1 0x08
3645 #define PCON_IDLS 0x20
3646 #define PCON_PDS 0x40
3647 #define PCON_SMOD 0x80
3648 #endif
3649
3650 #ifdef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3651 #undef PCON__SMOD__POR__PFW__WTR__EPFW__EWT__STOP__IDL
3652 SFR(PCON, 0x87);
3653 // Not directly accessible PCON bits
3654 #define IDL 0x01
3655 #define IDLE 0x01 /* same as IDL */
3656 #define STOP 0x02
3657 #define EWT 0x04
3658 #define EPFW 0x08
3659 #define WTR 0x10
3660 #define PFW 0x20
3661 #define POR 0x40
3662 #define SMOD 0x80
3663 #endif
3664
3665 #ifdef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3666 #undef PCON__SMOD__SMOD0__x__x__GF1__GF0__STOP__IDLE
3667 SFR(PCON, 0x87);
3668 // Not directly accessible PCON bits
3669 #define IDL 0x01
3670 #define IDLE 0x01 /* same as IDL */
3671 #define STOP 0x02
3672 #define GF0 0x04
3673 #define GF1 0x08
3674 #define SMOD0 0x40
3675 #define SMOD 0x80
3676 #endif
3677
3678 #ifdef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3679 #undef PCON__SMOD__SMOD0__OFDF__OFDE__GF1__GF0__STOP__IDLE
3680 SFR(PCON, 0x87);
3681 // Not directly accessible PCON bits
3682 #define IDL 0x01
3683 #define IDLE 0x01 /* same as IDL */
3684 #define STOP 0x02
3685 #define GF0 0x04
3686 #define GF1 0x08
3687 #define OFDE 0x10
3688 #define OFDF 0x20
3689 #define SMOD0 0x40
3690 #define SMOD 0x80
3691 #define SMOD_0 0x80 /* same as SMOD */
3692 #endif
3693
3694 #ifdef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3695 #undef PCON__SMOD1__SMOD0__x__POF__GF1__GF0__PD__IDL
3696 SFR(PCON, 0x87);
3697 #define IDL 0x01
3698 #define PD 0x02
3699 #define GF0 0x04
3700 #define GF1 0x08
3701 #define POF 0x10
3702 #define SMOD0 0x40
3703 #define SMOD1 0x80
3704 #endif
3705
3706 #ifdef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3707 #undef PMR__CD1__CD0__SWB__x__XTOFF__ALEOFF__DME1__DME0
3708 SFR(PMR, 0xC4); // DS87C520, DS83C520
3709 // Not directly accessible bits
3710 #define DME0 0x01
3711 #define DME1 0x02
3712 #define ALEOFF 0x04
3713 #define XTOFF 0x08
3714 #define SWB 0x20
3715 #define CD0 0x40
3716 #define CD1 0x80
3717 #endif
3718
3719 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3720 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEOFF__x__x
3721 SFR(PMR, 0xC4); // DS80C390
3722 // Not directly accessible bits
3723 #define ALEOFF 0x04
3724 #define XTOFF 0x08
3725 #define _4X_2X 0x10
3726 #define SWB 0x20
3727 #define CD0 0x40
3728 #define CD1 0x80
3729 #endif
3730
3731 #ifdef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3732 #undef PMR__CD1__CD0__SWB__CTM__4X_2X__ALEON__DME1__DME0
3733 SFR(PMR, 0xC4); // DS89C420
3734 // Not directly accessible bits
3735 #define DME0 0x01
3736 #define DME1 0x02
3737 #define ALEON 0x04
3738 #define _4X_2X 0x08
3739 #define CTM 0x10
3740 #define SWB 0x20
3741 #define CD0 0x40
3742 #define CD1 0x80
3743 #endif
3744
3745 #ifdef PRSC
3746 #undef PRSC
3747 SFR(PRSC, 0xB4);
3748 #endif
3749
3750 #ifdef PSW
3751 #undef PSW
3752 SFR(PSW, 0xD0);
3753 // Bit registers
3754 SBIT(P, 0xD0, 0);
3755 SBIT(F1, 0xD0, 1);
3756 SBIT(OV, 0xD0, 2);
3757 SBIT(RS0, 0xD0, 3);
3758 SBIT(RS1, 0xD0, 4);
3759 SBIT(F0, 0xD0, 5);
3760 SBIT(AC, 0xD0, 6);
3761 SBIT(CY, 0xD0, 7);
3762 #endif
3763
3764 #ifdef PWM0_AT_0XFC
3765 #undef PWM0_AT_0XFC
3766 SFR(PWM0, 0xFC); // PWM register 0, P80C552 specific
3767 #endif
3768
3769 #ifdef PWM1_AT_0XFD
3770 #undef PWM1_AT_0XFD
3771 SFR(PWM1, 0xFD); // PWM register 1, P80C552 specific
3772 #endif
3773
3774 #ifdef PWMP_AT_0XFE
3775 #undef PWMP_AT_0XFE
3776 SFR(PWMP, 0xFE); // PWM prescaler, P80C552 specific
3777 #endif
3778
3779 #ifdef RCAP2H
3780 #undef RCAP2H
3781 SFR(RCAP2H, 0xCB);
3782 #endif
3783
3784 #ifdef RCAP2L
3785 #undef RCAP2L
3786 SFR(RCAP2L, 0xCA);
3787 #endif
3788
3789 #ifdef RNR
3790 #undef RNR
3791 SFR(RNR, 0xCF);
3792 #endif
3793
3794 #ifdef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3795 #undef ROMSIZE__x__x__x__x__x__RMS2__RMS1__RMS0
3796 SFR(ROMSIZE, 0xC2); // DS87C520, DS83C520
3797 // Not directly accessible bits
3798 #define RSM0 0x01
3799 #define RSM1 0x02
3800 #define RSM2 0x04
3801 #endif
3802
3803 #ifdef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3804 #undef ROMSIZE__x__x__x__x__PRAME__RMS2__RMS1__RMS0
3805 SFR(ROMSIZE, 0xC2); // DS89C420
3806 // Not directly accessible bits
3807 #define RSM0 0x01
3808 #define RSM1 0x02
3809 #define RSM2 0x04
3810 #define PRAME 0x08
3811 #endif
3812
3813 #ifdef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3814 #undef ROMSIZE__HBPF__BPF__TE__MOVCX__PRAME__RMS2__RMS1__RMS0
3815 SFR(ROMSIZE, 0xC2); // DS87C520, DS83C520
3816 // Not directly accessible bits
3817 #define RSM0 0x01
3818 #define RSM1 0x02
3819 #define RSM2 0x04
3820 #define PRAME 0x08
3821 #define MOVCX 0x10
3822 #define TE 0x20
3823 #define BPF 0x40
3824 #define HBPF 0x80
3825 #endif
3826
3827 #ifdef RPCTL
3828 #undef RPCTL
3829 SFR(RPCTL, 0xD8); // Dallas DS5001 specific
3830 // Bit registers
3831 SBIT(RG0, 0xD8, 0);
3832 SBIT(RPCON, 0xD8, 1);
3833 SBIT(DMA, 0xD8, 2);
3834 SBIT(IBI, 0xD8, 3);
3835 SBIT(AE, 0xD8, 4);
3836 SBIT(EXBS, 0xD8, 5);
3837 SBIT(RNR_FLAG, 0xD8, 7);
3838 #endif
3839
3840 #ifdef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3841 #undef RTE__TP47__TP46__RP45__RP44__RP43__RP42__RP41__RP40
3842 SFR(RTE, 0xEF); // Reset/toggle enable, P80C552 specific
3843 // Not directly accessible Bits.
3844 #define RP40 0x01
3845 #define RP41 0x02
3846 #define RP42 0x04
3847 #define RP43 0x08
3848 #define RP44 0x10
3849 #define RP45 0x20
3850 #define TP46 0x40
3851 #define TP47 0x80
3852 #endif
3853
3854 #ifdef S0BUF
3855 #undef S0BUF
3856 SFR(S0BUF, 0x99); // serial channel 0 buffer register SAB80517 specific
3857 #endif
3858
3859 #ifdef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3860 #undef S0CON__SM0__SM1__SM2__REN__TB8__RB8__TI__RI
3861 SFR(S0CON, 0x98); // serial channel 0 control register P80C552 specific
3862 // Bit registers
3863 // Already defined in SCON
3864 //SBIT(RI0, 0x98, 0);
3865 //SBIT(TI0, 0x98, 1);
3866 //SBIT(RB8, 0x98, 2);
3867 //SBIT(TB8, 0x98, 3);
3868 //SBIT(REN, 0x98, 4);
3869 //SBIT(SM2, 0x98, 5);
3870 //SBIT(SM1, 0x98, 6);
3871 //SBIT(SM0, 0x98, 7);
3872 #endif
3873
3874 #ifdef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3875 #undef S0CON__SM0__SM1__SM20__REN0__TB80__RB80__TI0__RI0
3876 // serial channel 0 buffer register SAB80517 specific(same as stock SCON)
3877 SFR(S0CON, 0x98);
3878 // Bit registers
3879 SBIT(RI0, 0x98, 0);
3880 SBIT(TI0, 0x98, 1);
3881 SBIT(RB80, 0x98, 2);
3882 SBIT(TB80, 0x98, 3);
3883 SBIT(REN0, 0x98, 4);
3884 SBIT(SM20, 0x98, 5);
3885 SBIT(SM1, 0x98, 6);
3886 SBIT(SM0, 0x98, 7);
3887 #endif
3888
3889 #ifdef S0RELL
3890 #undef S0RELL
3891 SFR(S0RELL, 0xAA); // serial channel 0 reload register low byte SAB80517 specific
3892 #endif
3893
3894 #ifdef S0RELH
3895 #undef S0RELH
3896 SFR(S0RELH, 0xBA); // serial channel 0 reload register high byte SAB80517 specific
3897 #endif
3898
3899 #ifdef S1ADR__x__x__x__x__x__x__x__GC
3900 #undef S1ADR__x__x__x__x__x__x__x__GC
3901 SFR(S1ADR, 0xDB); // Serial 1 address, P80C552 specific
3902 // Not directly accessible Bits.
3903 #define GC 0x01
3904 #endif
3905
3906 #ifdef S1BUF
3907 #undef S1BUF
3908 SFR(S1BUF, 0x9C); // serial channel 1 buffer register SAB80517 specific
3909 #endif
3910
3911 #ifdef S1CON_AT_0X9B
3912 #undef S1CON_AT_0X9B
3913 SFR(S1CON, 0x9B); // serial channel 1 control register SAB80517 specific
3914 #endif
3915
3916 #ifdef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3917 #undef S1CON__CR2__ENS1__STA__ST0__SI__AA__CR1__CR0
3918 SFR(S1CON, 0xD8); // Serial 1 control, P80C552 specific
3919 SFR(SICON, 0xD8); // sometimes called SICON
3920 // Bit registers
3921 SBIT(CR0, 0xD8, 0);
3922 SBIT(CR1, 0xD8, 1);
3923 SBIT(AA, 0xD8, 2);
3924 SBIT(SI, 0xD8, 3);
3925 SBIT(ST0, 0xD8, 4);
3926 SBIT(STA, 0xD8, 5);
3927 SBIT(ENS1, 0xD8, 6);
3928 SBIT(CR2, 0xD8, 7);
3929 #endif
3930
3931 #ifdef S1DAT_AT_0XDA
3932 #undef S1DAT_AT_0XDA
3933 SFR(S1DAT, 0xDA); // Serial 1 data, P80C552 specific
3934 SFR(SIDAT, 0xDA); // sometimes called SIDAT
3935 #endif
3936
3937 #ifdef S1IST_AT_0XDC
3938 #undef S1IST_AT_0XDC
3939 // P89C668 specific
3940 SFR(S1IST, 0xDC);
3941 #endif
3942
3943 #ifdef S1RELL
3944 #undef S1RELL
3945 SFR(S1RELL, 0x9D); // serial channel 1 reload register low byte SAB80517 specific
3946 #endif
3947
3948 #ifdef S1RELH
3949 #undef S1RELH
3950 SFR(S1RELH, 0xBB); // serial channel 1 reload register high byte SAB80517 specific
3951 #endif
3952
3953 #ifdef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3954 #undef S1STA__SC4__SC3__SC2__SC1__SC0__x__x__x
3955 SFR(S1STA, 0xD9); // Serial 1 status, P80C552 specific
3956 // Not directly accessible Bits.
3957 #define SC0 0x08
3958 #define SC1 0x10
3959 #define SC2 0x20
3960 #define SC3 0x40
3961 #define SC4 0x80
3962 #endif
3963
3964 #ifdef SADR_AT_0XA9
3965 #undef SADR_AT_0XA9
3966 SFR(SADDR, 0xA9);
3967 #endif
3968
3969 #ifdef SADDR0
3970 #undef SADDR0
3971 // DS80C320 specific
3972 SFR(SADDR0, 0xA9);
3973 #endif
3974
3975 #ifdef SADDR1
3976 #undef SADDR1
3977 // DS80C320 specific
3978 SFR(SADDR1, 0xAA);
3979 #endif
3980
3981 #ifdef SADEN_AT_0XB9
3982 #undef SADEN_AT_0XB9
3983 SFR(SADEN, 0xB9);
3984 #endif
3985
3986 #ifdef SADEN0
3987 #undef SADEN0
3988 // DS80C320 & DS80C390 specific
3989 SFR(SADEN0, 0xB9);
3990 #endif
3991
3992 #ifdef SADEN1
3993 #undef SADEN1
3994 // DS80C320 & DS80C390 specific
3995 SFR(SADEN1, 0xBA);
3996 #endif
3997
3998 #ifdef SBUF
3999 #undef SBUF
4000 SFR(SBUF, 0x99);
4001 SFR(SBUF0, 0x99);
4002 #endif
4003
4004 #ifdef SBUF1
4005 #undef SBUF1
4006 // DS80C320 & DS80C390 specific
4007 SFR(SBUF1, 0xC1);
4008 #endif
4009
4010 #ifdef SCON
4011 #undef SCON
4012 SFR(SCON, 0x98);
4013 // Bit registers
4014 SBIT(RI, 0x98, 0);
4015 SBIT(TI, 0x98, 1);
4016 SBIT(RB8, 0x98, 2);
4017 SBIT(TB8, 0x98, 3);
4018 SBIT(REN, 0x98, 4);
4019 SBIT(SM2, 0x98, 5);
4020 SBIT(SM1, 0x98, 6);
4021 SBIT(SM0, 0x98, 7);
4022 #endif
4023
4024 #ifdef SCON0
4025 #undef SCON0
4026 SFR(SCON0, 0x98);
4027 // Bit registers
4028 SBIT(RI_0, 0x98, 0);
4029 SBIT(TI_0, 0x98, 1);
4030 SBIT(RB8_0, 0x98, 2);
4031 SBIT(TB8_0, 0x98, 3);
4032 SBIT(REN_0, 0x98, 4);
4033 SBIT(SM2_0, 0x98, 5);
4034 SBIT(SM1_0, 0x98, 6);
4035 SBIT(SM0_0, 0x98, 7);
4036 SBIT(FE_0, 0x98, 7);
4037 SBIT(SM0_FE_0, 0x98, 7);
4038 #endif
4039
4040 #ifdef SCON1
4041 #undef SCON1
4042 // DS80C320 - 80C390 specific
4043 SFR(SCON1, 0xC0);
4044 // Bit registers
4045 SBIT(RI_1, 0xC0, 0);
4046 SBIT(TI_1, 0xC0, 1);
4047 SBIT(RB8_1, 0xC0, 2);
4048 SBIT(TB8_1, 0xC0, 3);
4049 SBIT(REN_1, 0xC0, 4);
4050 SBIT(SM2_1, 0xC0, 5);
4051 SBIT(SM1_1, 0xC0, 6);
4052 SBIT(SM0_1, 0xC0, 7);
4053 SBIT(FE_1, 0xC0, 7);
4054 SBIT(SM0_FE_1, 0xC0, 7);
4055 #endif
4056
4057 #ifdef SETMSK
4058 #undef SETMSK
4059 SFR(SETMSK, 0xA5);
4060 #endif
4061
4062 #ifdef SP
4063 #undef SP
4064 SFR(SP, 0x81);
4065 #endif
4066
4067 #ifdef SPCR
4068 #undef SPCR
4069 SFR(SPCR, 0xD5); // AT89S53 specific
4070 // Not directly accesible bits
4071 #define SPR0 0x01
4072 #define SPR1 0x02
4073 #define CPHA 0x04
4074 #define CPOL 0x08
4075 #define MSTR 0x10
4076 #define DORD 0x20
4077 #define SPE 0x40
4078 #define SPIE 0x80
4079 #endif
4080
4081 #ifdef SPDR
4082 #undef SPDR
4083 SFR(SPDR, 0x86); // AT89S53 specific
4084 // Not directly accesible bits
4085 #define SPD_0 0x01
4086 #define SPD_1 0x02
4087 #define SPD_2 0x04
4088 #define SPD_3 0x08
4089 #define SPD_4 0x10
4090 #define SPD_5 0x20
4091 #define SPD_6 0x40
4092 #define SPD_7 0x80
4093 #endif
4094
4095 #ifdef SPSR
4096 #undef SPSR
4097 SFR(SPSR, 0xAA); // AT89S53 specific
4098 // Not directly accesible bits
4099 #define SPIF 0x40
4100 #define WCOL 0x80
4101 #endif
4102
4103 #ifdef SRELH
4104 #undef SRELH
4105 SFR(SRELH, 0xBA); // Baudrate generator reload high
4106 #endif
4107
4108 #ifdef SRELL
4109 #undef SRELL
4110 SFR(SRELL, 0xAA); // Baudrate generator reload low
4111 #endif
4112
4113 #ifdef STATUS__PIP__HIP__LIP__x__x__x__x__x
4114 #undef STATUS__PIP__HIP__LIP__x__x__x__x__x
4115 // DS80C320 specific
4116 SFR(STATUS, 0xC5);
4117 // Not directly accessible Bits. DS80C320 specific
4118 #define LIP 0x20
4119 #define HIP 0x40
4120 #define PIP 0x80
4121 #endif
4122
4123 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
4124 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
4125 SFR(STATUS, 0xC5); // DS80C390 specific
4126 // Not directly accessible Bits.
4127 #define SPRA0 0x01
4128 #define SPTA0 0x02
4129 #define SPRA1 0x04
4130 #define SPTA1 0x08
4131 #define LIP 0x20
4132 #define HIP 0x40
4133 #define PIP 0x80
4134 #endif
4135
4136 #ifdef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
4137 #undef STATUS__PIS2__PIS1__PIS0__x__SPTA1__SPRA1__SPTA0__SPRA0
4138 SFR(STATUS, 0xC5); // DS89C420 specific
4139 // Not directly accessible Bits.
4140 #define SPRA0 0x01
4141 #define SPTA0 0x02
4142 #define SPRA1 0x04
4143 #define SPTA1 0x08
4144 #define PIS0 0x20
4145 #define PIS1 0x40
4146 #define PIS2 0x80
4147 #endif
4148
4149 #ifdef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
4150 #undef STATUS__PIP__HIP__LIP__x__SPTA1__SPRA1__SPTA0__SPRA0
4151 SFR(STATUS, 0xC5); // DS80C390 specific
4152 // Not directly accessible Bits.
4153 #define SPRA0 0x01
4154 #define SPTA0 0x02
4155 #define SPRA1 0x04
4156 #define SPTA1 0x08
4157 #define LIP 0x20
4158 #define HIP 0x40
4159 #define PIP 0x80
4160 #endif
4161
4162 #ifdef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
4163 #undef STATUS__PIP__HIP__LIP__XTUP__SPTA2__SPTA1__SPTA0__SPRA0
4164 SFR(STATUS, 0xC5); // DS87C520 & DS83520specific
4165 // Not directly accessible Bits.
4166 #define SPRA0 0x01
4167 #define SPTA0 0x02
4168 #define SPTA1 0x04
4169 #define SPTA2 0x08
4170 #define XTUP 0x10
4171 #define LIP 0x20
4172 #define HIP 0x40
4173 #define PIP 0x80
4174 #endif
4175
4176 #ifdef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
4177 #undef STATUS__ST7__ST6__ST5__ST4__IA0__F0__IBF__OBF
4178 SFR(STATUS, 0xDA); // DS5001specific
4179 // Not directly accessible Bits.
4180 #define OBF 0x01
4181 #define IBF 0x02
4182 #define F0 0x04
4183 #define IA0 0x08
4184 #define ST4 0x10
4185 #define ST5 0x20
4186 #define ST6 0x40
4187 #define ST7 0x80
4188 #endif
4189
4190 #ifdef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
4191 #undef STE__TG47__TG46__SP45__SP44__SP43__SP42__SP41__SP40
4192 SFR(STE, 0xEE); // Set enable, P80C552 specific
4193 // Not directly accessible Bits.
4194 #define SP40 0x01
4195 #define SP41 0x02
4196 #define SP42 0x04
4197 #define SP43 0x08
4198 #define SP44 0x10
4199 #define SP45 0x20
4200 #define TG46 0x40
4201 #define TG47 0x80
4202 #endif
4203
4204 #ifdef SYSCON
4205 #undef SYSCON
4206 SFR(SYSCON, 0xB1); // XRAM Controller Access Control
4207 // SYSCON bits
4208 #define SYSCON_XMAP0 0x01
4209 #define SYSCON_XMAP1 0x02
4210 #define SYSCON_RMAP 0x10
4211 #define SYSCON_EALE 0x20
4212 #endif
4213
4214 #ifdef SYSCON1
4215 #undef SYSCON1
4216 SFR(SYSCON1, 0xB2);
4217 #endif
4218
4219 #ifdef T2
4220 #undef T2
4221 SFR(T2, 0xCC);
4222 #endif
4223
4224 #ifdef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
4225 #undef T2CON__TF2__EXF2__RCLK__TCLK__EXEN2__TR2__C_T2__CP_RL2
4226 SFR(T2CON, 0xC8);
4227 // Definitions for the 8052 compatible microcontrollers.
4228 // Bit registers
4229 SBIT(CP_RL2, 0xC8, 0);
4230 SBIT(C_T2, 0xC8, 1);
4231 SBIT(TR2, 0xC8, 2);
4232 SBIT(EXEN2, 0xC8, 3);
4233 SBIT(TCLK, 0xC8, 4);
4234 SBIT(RCLK, 0xC8, 5);
4235 SBIT(EXF2, 0xC8, 6);
4236 SBIT(TF2, 0xC8, 7);
4237 // alternate names
4238 SBIT(T2CON_0, 0xC8, 0);
4239 SBIT(T2CON_1, 0xC8, 1);
4240 SBIT(T2CON_2, 0xC8, 2);
4241 SBIT(T2CON_3, 0xC8, 3);
4242 SBIT(T2CON_4, 0xC8, 4);
4243 SBIT(T2CON_5, 0xC8, 5);
4244 SBIT(T2CON_6, 0xC8, 6);
4245 SBIT(T2CON_7, 0xC8, 7);
4246 #endif
4247
4248 #ifdef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
4249 #undef T2CON__T2PS__I3FR__I2FR__T2R1__T2R0__T2CM__T2I1__T2I0
4250 SFR(T2CON, 0xC8);
4251 // Definitions for the Infineon / Siemens SAB80515, SAB80515A, SAB80517
4252 // Bit registers
4253 SBIT(T2I0, 0xC8, 0);
4254 SBIT(T2I1, 0xC8, 1);
4255 SBIT(T2CM, 0xC8, 2);
4256 SBIT(T2R0, 0xC8, 3);
4257 SBIT(T2R1, 0xC8, 4);
4258 SBIT(I2FR, 0xC8, 5);
4259 SBIT(I3FR, 0xC8, 6);
4260 SBIT(T2PS, 0xC8, 7);
4261 // alternate names
4262 SBIT(T2CON_0, 0xC8, 0);
4263 SBIT(T2CON_1, 0xC8, 1);
4264 SBIT(T2CON_2, 0xC8, 2);
4265 SBIT(T2CON_3, 0xC8, 3);
4266 SBIT(T2CON_4, 0xC8, 4);
4267 SBIT(T2CON_5, 0xC8, 5);
4268 SBIT(T2CON_6, 0xC8, 6);
4269 SBIT(T2CON_7, 0xC8, 7);
4270 #endif
4271
4272 #ifdef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4273 #undef T2MOD__x__x__x__D13T1__D13T2__x__T2OE__DCEN
4274 // Definitions for the timer/counter 2 of the Atmel & Dallas microcontrollers
4275 SFR(T2MOD, 0xC9);
4276 // Not not directly accessible T2MOD bits
4277 #define DCEN 0x01
4278 #define T2OE 0x02
4279 #define D13T2 0x08
4280 #define D13T1 0x10
4281 #endif
4282
4283 #ifdef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4284 #undef T2MOD__x__x__x__x__x__x__T2OE__DCEN
4285 // Definitions for the timer/counter 2 of the Atmel 89x52 microcontroller
4286 SFR(T2MOD, 0xC9);
4287 // Not not directly accessible T2MOD bits
4288 #define DCEN 0x01
4289 #define T2OE 0x02
4290 // Alternate names
4291 #define DCEN_ 0x01
4292 #define T2OE_ 0x02
4293 #endif
4294
4295 #ifdef T3_AT_0XFF
4296 #undef T3_AT_0XFF
4297 SFR(T3, 0xFF); // Timer 3, P80C552 specific
4298 #endif
4299
4300 #ifdef TA
4301 #undef TA
4302 // DS500x, DS80C320 & DS80C390 specific
4303 SFR(TA, 0xC7);
4304 #endif
4305
4306 #ifdef TCON
4307 #undef TCON
4308 SFR(TCON, 0x88);
4309 // Bit registers
4310 SBIT(IT0, 0x88, 0);
4311 SBIT(IE0, 0x88, 1);
4312 SBIT(IT1, 0x88, 2);
4313 SBIT(IE1, 0x88, 3);
4314 SBIT(TR0, 0x88, 4);
4315 SBIT(TF0, 0x88, 5);
4316 SBIT(TR1, 0x88, 6);
4317 SBIT(TF1, 0x88, 7);
4318 #endif
4319
4320 #ifdef TH0
4321 #undef TH0
4322 SFR(TH0, 0x8C);
4323 #endif
4324
4325 #ifdef TH1
4326 #undef TH1
4327 SFR(TH1, 0x8D);
4328 #endif
4329
4330 #ifdef TH2
4331 #undef TH2
4332 SFR(TH2, 0xCD);
4333 #endif
4334
4335 #ifdef TL0
4336 #undef TL0
4337 SFR(TL0, 0x8A);
4338 #endif
4339
4340 #ifdef TL1
4341 #undef TL1
4342 SFR(TL1, 0x8B);
4343 #endif
4344
4345 #ifdef TL2
4346 #undef TL2
4347 SFR(TL2, 0xCC);
4348 #endif
4349
4350 #ifdef TMOD
4351 #undef TMOD
4352 SFR(TMOD, 0x89);
4353 // Not directly accessible TMOD bits
4354 #define T0_M0 0x01
4355 #define T0_M1 0x02
4356 #define T0_CT 0x04
4357 #define T0_GATE 0x08
4358 #define T1_M0 0x10
4359 #define T1_M1 0x20
4360 #define T1_CT 0x40
4361 #define T1_GATE 0x80
4362
4363 #define T0_MASK 0x0F
4364 #define T1_MASK 0xF0
4365 #endif
4366
4367 #ifdef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4368 #undef TM2CON__T2IS1__T2IS0__T2ER__T2B0__T2P1__T2P0__T2MS1__T2MS0
4369 SFR(TM2CON, 0xEA); // Timer 2 control, P80C552 specific
4370 // Not directly accessible Bits.
4371 #define T2MS0 0x01
4372 #define T2MS1 0x02
4373 #define T2P0 0x04
4374 #define T2P1 0x08
4375 #define T2B0 0x10
4376 #define T2ER 0x20
4377 #define T2IS0 0x40
4378 #define T2IS1 0x80
4379 #endif
4380
4381 #ifdef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4382 #undef TM2IR__T20V__CMI2__CMI1__CMI0__CTI3__CTI2__CTI1__CTI0
4383 SFR(TM2IR, 0xC8); // Timer 2 int flag reg, P80C552 specific
4384 // Bit register
4385 SBIT(CTI0, 0xC8, 0);
4386 SBIT(CTI1, 0xC8, 1);
4387 SBIT(CTI2, 0xC8, 2);
4388 SBIT(CTI3, 0xC8, 3);
4389 SBIT(CMI0, 0xC8, 4);
4390 SBIT(CMI1, 0xC8, 5);
4391 SBIT(CMI2, 0xC8, 6);
4392 SBIT(T20V, 0xC8, 7);
4393 #endif
4394
4395 #ifdef TMH2_AT_0XED
4396 #undef TMH2_AT_0XED
4397 SFR(TMH2, 0xED); // Timer high 2, P80C552 specific
4398 #endif
4399
4400 #ifdef TML2_AT_0XEC
4401 #undef TML2_AT_0XEC
4402 SFR(TML2, 0xEC); // Timer low 2, P80C552 specific
4403 #endif
4404
4405 #ifdef WCON
4406 #undef WCON
4407 SFR(WCON, 0x96); // AT89S53 specific
4408 // Not directly accesible bits
4409 #define WDTEN 0x01
4410 #define WDTRST 0x02
4411 #define DPS 0x04
4412 #define PS0 0x20
4413 #define PS1 0x40
4414 #define PS2 0x80
4415 #endif
4416
4417 #ifdef WDCON
4418 #undef WDCON
4419 // DS80C320 - 390, DS89C420, etc. specific
4420 SFR(WDCON, 0xD8);
4421 // Bit registers
4422 SBIT(RWT, 0xD8, 0);
4423 SBIT(EWT, 0xD8, 1);
4424 SBIT(WTRF, 0xD8, 2);
4425 SBIT(WDIF, 0xD8, 3);
4426 SBIT(PFI, 0xD8, 4);
4427 SBIT(EPFI, 0xD8, 5);
4428 SBIT(POR, 0xD8, 6);
4429 SBIT(SMOD_1, 0xD8, 7);
4430 #endif
4431
4432 #ifdef WDTPRG_AT_0XA7
4433 #undef WDTPRG_AT_0XA7
4434 SFR(WDTPRG, 0xA7);
4435 #define WDTRPRG_S0 0x01
4436 #define WDTRPRG_S1 0x02
4437 #define WDTRPRG_S2 0x04
4438 #endif
4439
4440 #ifdef WDTREL
4441 #undef WDTREL
4442 SFR(WDTREL, 0x86); // Watchdof Timer reload register
4443 #endif
4444
4445 #ifdef WDTRST_AT_0XA6
4446 #undef WDTRST_AT_0XA6
4447 SFR(WDTRST, 0xA6);
4448 #endif
4449
4450 #ifdef XPAGE
4451 #undef XPAGE
4452 SFR(XPAGE, 0x91); // Page Address Register for Extended On-Chip Ram - Infineon / Siemens SAB80515A specific
4453 #endif
4454
4455 /////////////////////////
4456 /// Interrupt vectors ///
4457 /////////////////////////
4458
4459 // Interrupt numbers: address = (number * 8) + 3
4460 #define IE0_VECTOR 0 // 0x03 external interrupt 0
4461 #define TF0_VECTOR 1 // 0x0b timer 0
4462 #define IE1_VECTOR 2 // 0x13 external interrupt 1
4463 #define TF1_VECTOR 3 // 0x1b timer 1
4464 #define SI0_VECTOR 4 // 0x23 serial port 0
4465
4466 #ifdef MICROCONTROLLER_AT89S53
4467 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4468 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4469 #endif
4470
4471 #ifdef MICROCONTROLLER_AT89X52
4472 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4473 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4474 #endif
4475
4476 #ifdef MICROCONTROLLER_AT89X55
4477 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4478 #define EX2_VECTOR 5 /* 0x2B external interrupt 2 */
4479 #endif
4480
4481 #ifdef MICROCONTROLLER_DS5000
4482 #define PFW_VECTOR 5 /* 0x2B */
4483 #endif
4484
4485 #ifdef MICROCONTROLLER_DS5001
4486 #define PFW_VECTOR 5 /* 0x2B */
4487 #endif
4488
4489 #ifdef MICROCONTROLLER_DS80C32X
4490 #define TF2_VECTOR 5 /* 0x2B */
4491 #define PFI_VECTOR 6 /* 0x33 */
4492 #define SIO1_VECTOR 7 /* 0x3B */
4493 #define IE2_VECTOR 8 /* 0x43 */
4494 #define IE3_VECTOR 9 /* 0x4B */
4495 #define IE4_VECTOR 10 /* 0x53 */
4496 #define IE5_VECTOR 11 /* 0x5B */
4497 #define WDI_VECTOR 12 /* 0x63 */
4498 #endif
4499
4500 #ifdef MICROCONTROLLER_DS89C420
4501 #define TF2_VECTOR 5 /* 0x2B */
4502 #define PFI_VECTOR 6 /* 0x33 */
4503 #define SIO1_VECTOR 7 /* 0x3B */
4504 #define IE2_VECTOR 8 /* 0x43 */
4505 #define IE3_VECTOR 9 /* 0x4B */
4506 #define IE4_VECTOR 10 /* 0x53 */
4507 #define IE5_VECTOR 11 /* 0x5B */
4508 #define WDI_VECTOR 12 /* 0x63 */
4509 #endif
4510
4511 #ifdef MICROCONTROLLER_DS8XC520
4512 #define TF2_VECTOR 5 /* 0x2B */
4513 #define PFI_VECTOR 6 /* 0x33 */
4514 #define SIO1_VECTOR 7 /* 0x3B */
4515 #define IE2_VECTOR 8 /* 0x43 */
4516 #define IE3_VECTOR 9 /* 0x4B */
4517 #define IE4_VECTOR 10 /* 0x53 */
4518 #define IE5_VECTOR 11 /* 0x5B */
4519 #define WDI_VECTOR 12 /* 0x63 */
4520 #endif
4521
4522 #ifdef MICROCONTROLLER_P80C552
4523 #define SIO1_VECTOR 5 // 0x2B SIO1 (I2C)
4524 #define CT0_VECTOR 6 // 0x33 T2 capture 0
4525 #define CT1_VECTOR 7 // 0x3B T2 capture 1
4526 #define CT2_VECTOR 8 // 0x43 T2 capture 2
4527 #define CT3_VECTOR 9 // 0x4B T2 capture 3
4528 #define ADC_VECTOR 10 // 0x53 ADC completion
4529 #define CM0_VECTOR 11 // 0x5B T2 compare 0
4530 #define CM1_VECTOR 12 // 0x63 T2 compare 1
4531 #define CM2_VECTOR 13 // 0x6B T2 compare 2
4532 #define TF2_VECTOR 14 // 0x73 T2 overflow
4533 #endif
4534
4535 #ifdef MICROCONTROLLER_P89C668
4536 #define SIO1_VECTOR 5 // 0x2b SIO1 (i2c)
4537 #define PCA_VECTOR 6 // 0x33 (Programmable Counter Array)
4538 #define TF2_VECTOR 7 // 0x3B (Timer 2)
4539 #endif
4540
4541 #ifdef MICROCONTROLLER_SAB80509
4542 #define RI0_VECTOR 4 // 0x23 serial port 0
4543 #define TI0_VECTOR 4 // 0x23 serial port 0
4544 #define TF2_VECTOR 5 // 0x2B timer 2
4545 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4546 // 0x33
4547 // 0x3B
4548 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4549 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4550 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4551 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4552 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4553 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4554 // 0x73 not used
4555 // 0x7B not used
4556 #define SI1_VECTOR 16 // 0x83 serial port 1
4557 #define RI1_VECTOR 16 // 0x83 serial port 1
4558 #define TI1_VECTOR 16 // 0x83 serial port 1
4559 // 0x8B not used
4560 #define ICM_VECTOR 18 // 0x93 compare registers CM0-CM7
4561 #define CTF_VECTOR 19 // 0x9B compare time overflow
4562 #define ICS_VECTOR 20 // 0xA3 compare register COMSET
4563 #define ICR_VECTOR 21 // 0xAB compare register COMCLR
4564 #define ICC_VECTOR 26 // 0xD3 compare event interrupt ICC10-ICC17
4565 #define CT1_VECTOR 27 // 0xDB compare timer 1 oveflow
4566 #endif
4567
4568 #ifdef MICROCONTROLLER_SAB80515
4569 #define TF2_VECTOR 5 // 0x2B timer 2
4570 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4571 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4572 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4573 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4574 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4575 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4576 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4577 #endif
4578
4579 #ifdef MICROCONTROLLER_SAB80515A
4580 #define TF2_VECTOR 5 // 0x2B timer 2
4581 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4582 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4583 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4584 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4585 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4586 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4587 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4588 #endif
4589
4590 #ifdef MICROCONTROLLER_SAB80517
4591 #define TF2_VECTOR 5 // 0x2B timer 2
4592 #define EX2_VECTOR 5 // 0x2B external interrupt 2
4593 #define IADC_VECTOR 8 // 0x43 A/D converter interrupt
4594 #define IEX2_VECTOR 9 // 0x4B external interrupt 2
4595 #define IEX3_VECTOR 10 // 0x53 external interrupt 3
4596 #define IEX4_VECTOR 11 // 0x5B external interrupt 4
4597 #define IEX5_VECTOR 12 // 0x63 external interrupt 5
4598 #define IEX6_VECTOR 13 // 0x6B external interrupt 6
4599 // 0x73 not used
4600 // 0x7B not used
4601 #define SI1_VECTOR 16 // 0x83 serial port 1
4602 // 0x8B not used
4603 // 0x93 not used
4604 #define COMPARE_VECTOR 19 // 0x9B compare
4605 #endif
4606
4607 #ifdef MICROCONTORLLER_T89C51RD2
4608 #define TF2_VECTOR 5 /* 0x2B timer 2 */
4609 #define PCA_VECTOR 6 /* 0x33 Programmable Counter Array interrupt */
4610 #endif /* MICROCONTORLLER_T89C51RD2 */
4611
4612 #endif // End of the header -> #ifndef MCS51REG_H
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