sdcc/device/include/mcs51/msm8xc154s.h

   1 /*-------------------------------------------------------------------------
   2    msm8xc154s.h - Register Declarations for the Oki MSM80C154S and
   3    MSM83C154S
   4
   5    Copyright (C) 2005,  Matthias Arndt / marndt@asmsoftware.de
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef MSM8xC154S_H
  31 #define MSM8xC154S_H
  32
  33 #include <8052.h>     /* load definitions for the 8052 core */
  34
  35 #ifdef REG8052_H
  36 #undef REG8052_H
  37 #endif
  38
  39 /* byte SFRs */
  40 __sfr __at (0xf8)       IOCON;  /* IOCON register */
  41
  42 /* bit locations */
  43 __sbit __at (0xf8)      ALF;    /* floating status on power down control */
  44 __sbit __at (0xf9)      P1HZ;   /* P1 high impedance input control */
  45 __sbit __at (0xfa)      P2HZ;   /* P2 high impedance input control */
  46 __sbit __at (0xfb)      P3HZ;   /* P3 high impedance input control */
  47 __sbit __at (0xfc)      IZC;    /* 10kO pull-up resistor control */
  48 __sbit __at (0xfd)      SERR;   /* Serial port reception flag */
  49 __sbit __at (0xfe)      T32;    /* interconnect T0 and T1 to 32bit timer/counter */
  50
  51 /* Bits in IP (0xb8) */
  52 __sbit __at (0xbf)      PCT;    /* Priority interrupt circuit control bit */
  53
  54 /* Bits in PCON (0x87) */
  55 #define RPD 0x20            /* Bit used to specify cancellation of CPU power down mode */
  56 #define HPD 0x40            /* The hard power down setting mode is enabled when this bit is set to "1". */
  57
  58 #endif