sdcc/device/include/mcs51/p89lpc9321.h

   1 /*-------------------------------------------------------------------------
   2    p89lpc9321.h - Register Declarations for NXP the P89LPC9321
   3    (Based on user manual (UM10310_1) Rev. 01 - 1 December 2008)
   4
   5    Copyright (C) 2009, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef REG_P89LPC9321_H
  31 #define REG_P89LPC9321_H
  32
  33 #include <compiler.h>
  34
  35 SFR(ACC,     0xe0); // Accumulator
  36     SBIT(ACC_7,   0xe0, 7);
  37     SBIT(ACC_6,   0xe0, 6);
  38     SBIT(ACC_5,   0xe0, 5);
  39     SBIT(ACC_4,   0xe0, 4);
  40     SBIT(ACC_3,   0xe0, 3);
  41     SBIT(ACC_2,   0xe0, 2);
  42     SBIT(ACC_1,   0xe0, 1);
  43     SBIT(ACC_0,   0xe0, 0);
  44 SFR(AUXR1,   0xa2); // Auxiliary function register
  45     #define CLKLP    0x80
  46     #define EBRR     0x40
  47     #define ENT1     0x20
  48     #define ENT0     0x10
  49     #define SRST     0x08
  50     #define DPS      0x01
  51 SFR(B,       0xf0); // B register
  52     SBIT(B_7,     0xf0, 7);
  53     SBIT(B_6,     0xf0, 6);
  54     SBIT(B_5,     0xf0, 5);
  55     SBIT(B_4,     0xf0, 4);
  56     SBIT(B_3,     0xf0, 3);
  57     SBIT(B_2,     0xf0, 2);
  58     SBIT(B_1,     0xf0, 1);
  59     SBIT(B_0,     0xf0, 0);
  60 SFR(BRGR0,   0xbe); // Baud rate generator 0 rate low
  61 SFR(BRGR1,   0xbf); // Baud rate generator 0 rate high
  62 SFR(BRGCON,  0xbd); // Baud rate generator 0 control
  63     #define SBRGS    0x02
  64     #define BRGEN    0x01
  65 SFR(CCCRA,   0xea); // Capture compare A control register
  66     #define ICECA2   0x80
  67     #define ICECA1   0x40
  68     #define ICECA0   0x20
  69     #define ICESA    0x10
  70     #define ICNFA    0x08
  71     #define FCOA     0x04
  72     #define OCMA1    0x02
  73     #define OCMA0    0x01
  74 SFR(CCCRB,   0xeb); // Capture compare B control register
  75     #define ICECB2   0x80
  76     #define ICECB1   0x40
  77     #define ICECB0   0x20
  78     #define ICESB    0x10
  79     #define ICNFB    0x08
  80     #define FCOB     0x04
  81     #define OCMB1    0x02
  82     #define OCMB0    0x01
  83 SFR(CCCRC,   0xec); // Capture compare C control register
  84     #define FCOC     0x04
  85     #define OCMC1    0x02
  86     #define OCMC0    0x01
  87 SFR(CCCRD,   0xed); // Capture compare D control register
  88     #define FCOD     0x04
  89     #define OCMD1    0x02
  90     #define OCMD0    0x01
  91 SFR(CMP1,    0xac); // Comparator 1 control register
  92     #define CE1      0x20
  93     #define CP1      0x10
  94     #define CN1      0x08
  95     #define OE1      0x04
  96     #define CO1      0x02
  97     #define CMF1     0x01
  98 SFR(CMP2,    0xad); // Comparator 2 control register
  99     #define CE2      0x20
 100     #define CP2      0x10
 101     #define CN2      0x08
 102     #define OE2      0x04
 103     #define CO2      0x02
 104     #define CMF2     0x01
 105 SFR(DEECON,  0xf1); // Data EEPROM control register
 106     #define EEIF     0x80
 107     #define HVERR    0x40
 108     #define ECTL1    0x20
 109     #define ECTL0    0x10
 110     #define EWERR1   0x04
 111     #define EWERR0   0x02
 112     #define EADR8    0x01
 113 SFR(DEEDAT,  0xf2); // Data EEPROM data register
 114 SFR(DEEADR,  0xf3); // Data EEPROM address register
 115 SFR(DIVM,    0x95); // CPU clock divide-by-M control
 116 SFR(DPH,     0x83); // Data pointer high
 117 SFR(DPL,     0x82); // Data pointer low
 118 SFR(FMADRH,  0xe7); // Program flash address high
 119 SFR(FMADRL,  0xe6); // Program flash address low
 120 SFR(FMCON,   0xe4); // Program flash control Read
 121     #define BUSY     0x80
 122     #define HVA      0x08
 123     #define HVE      0x04
 124     #define SV       0x02
 125     #define OI       0x01
 126     #define FMCMD_7  0x80
 127     #define FMCMD_6  0x40
 128     #define FMCMD_5  0x20
 129     #define FMCMD_4  0x10
 130     #define FMCMD_3  0x08
 131     #define FMCMD_2  0x04
 132     #define FMCMD_1  0x02
 133     #define FMCMD_0  0x01
 134 SFR(FMDATA,  0xe5); // Program flash data
 135 SFR(I2ADR,   0xdb); // I2C-bus slave address register
 136     #define I2ADR_6  0x80
 137     #define I2ADR_5  0x40
 138     #define I2ADR_4  0x20
 139     #define I2ADR_3  0x10
 140     #define I2ADR_2  0x08
 141     #define I2ADR_1  0x04
 142     #define I2ADR_0  0x02
 143     #define GC       0x01
 144 SFR(I2CON,   0xd8); // I2C-bus control register
 145     SBIT(I2CON_7, 0xd8, 7);
 146     SBIT(I2CON_6, 0xd8, 6);
 147     SBIT(I2CON_5, 0xd8, 5);
 148     SBIT(I2CON_4, 0xd8, 4);
 149     SBIT(I2CON_3, 0xd8, 3);
 150     SBIT(I2CON_2, 0xd8, 2);
 151     SBIT(I2CON_1, 0xd8, 1);
 152     SBIT(I2CON_0, 0xd8, 0);
 153     SBIT(I2EN,    0xd8, 6);
 154     SBIT(STA,     0xd8, 5);
 155     SBIT(STO,     0xd8, 4);
 156     SBIT(SI,      0xd8, 3);
 157     SBIT(AA,      0xd8, 2);
 158     SBIT(CRSEL,   0xd8, 0);
 159 SFR(I2DAT,   0xda); // I2C-bus data register
 160 SFR(I2SCLH,  0xdd); // Serial clock generator/SCL duty cycle register high
 161 SFR(I2SCLL,  0xdc); // Serial clock generator/SCL duty cycle register low
 162 SFR(I2STAT,  0xd9); // I2C-bus status register
 163     #define STA_4    0x80
 164     #define STA_3    0x40
 165     #define STA_2    0x20
 166     #define STA_1    0x10
 167     #define STA_0    0x08
 168 SFR(ICRAH,   0xab); // Input capture A register high
 169 SFR(ICRAL,   0xaa); // Input capture A register low
 170 SFR(ICRBH,   0xaf); // Input capture B register high
 171 SFR(ICRBL,   0xae); // Input capture B register low
 172 SFR(IEN0,    0xa8); // Interrupt enable 0
 173     SBIT(IEN0_7,  0xa8, 7);
 174     SBIT(IEN0_6,  0xa8, 6);
 175     SBIT(IEN0_5,  0xa8, 5);
 176     SBIT(IEN0_4,  0xa8, 4);
 177     SBIT(IEN0_3,  0xa8, 3);
 178     SBIT(IEN0_2,  0xa8, 2);
 179     SBIT(IEN0_1,  0xa8, 1);
 180     SBIT(IEN0_0,  0xa8, 0);
 181     SBIT(EA,      0xa8, 7);
 182     SBIT(EWDRT,   0xa8, 6);
 183     SBIT(EBO,     0xa8, 5);
 184     SBIT(ES,      0xa8, 4);
 185     SBIT(ESR,     0xa8, 4);
 186     SBIT(ET1,     0xa8, 3);
 187     SBIT(EX1,     0xa8, 2);
 188     SBIT(ET0,     0xa8, 1);
 189     SBIT(EX0,     0xa8, 0);
 190 SFR(IEN1,    0xe8); // Interrupt enable 1
 191     SBIT(IEN1_7,  0xe8, 7);
 192     SBIT(IEN1_6,  0xe8, 6);
 193     SBIT(IEN1_5,  0xe8, 5);
 194     SBIT(IEN1_4,  0xe8, 4);
 195     SBIT(IEN1_3,  0xe8, 3);
 196     SBIT(IEN1_2,  0xe8, 2);
 197     SBIT(IEN1_1,  0xe8, 1);
 198     SBIT(IEN1_0,  0xe8, 0);
 199     SBIT(EIEE,    0xe8, 7);
 200     SBIT(EST,     0xe8, 6);
 201     SBIT(ECCU,    0xe8, 4);
 202     SBIT(ESPI,    0xe8, 3);
 203     SBIT(EC,      0xe8, 2);
 204     SBIT(EKBI,    0xe8, 1);
 205     SBIT(EI2C,    0xe8, 0);
 206 SFR(IP0,     0xb8); // Interrupt priority 0
 207     SBIT(IP0_7,   0xb8, 7);
 208     SBIT(IP0_6,   0xb8, 6);
 209     SBIT(IP0_5,   0xb8, 5);
 210     SBIT(IP0_4,   0xb8, 4);
 211     SBIT(IP0_3,   0xb8, 3);
 212     SBIT(IP0_2,   0xb8, 2);
 213     SBIT(IP0_1,   0xb8, 1);
 214     SBIT(IP0_0,   0xb8, 0);
 215     SBIT(PWDRT,   0xb8, 6);
 216     SBIT(PBO,     0xb8, 5);
 217     SBIT(PS,      0xb8, 4);
 218     SBIT(PSR,     0xb8, 4);
 219     SBIT(PT1,     0xb8, 3);
 220     SBIT(PX1,     0xb8, 2);
 221     SBIT(PT0,     0xb8, 1);
 222     SBIT(PX0,     0xb8, 0);
 223 SFR(IP0H,    0xb7); // Interrupt priority 0 high
 224     #define PWDRTH   0x40
 225     #define PBOH     0x20
 226     #define PSH      0x10
 227     #define PSRH     0x10
 228     #define PT1H     0x08
 229     #define PX1H     0x04
 230     #define PT0H     0x02
 231     #define PX0H     0x01
 232 SFR(IP1,     0xf8); // Interrupt priority 1
 233     SBIT(IP1_7,   0xf8, 7);
 234     SBIT(IP1_6,   0xf8, 6);
 235     SBIT(IP1_5,   0xf8, 5);
 236     SBIT(IP1_4,   0xf8, 4);
 237     SBIT(IP1_3,   0xf8, 3);
 238     SBIT(IP1_2,   0xf8, 2);
 239     SBIT(IP1_1,   0xf8, 1);
 240     SBIT(IP1_0,   0xf8, 0);
 241     SBIT(PIEE,    0xf8, 7);
 242     SBIT(PST,     0xf8, 6);
 243     SBIT(PCCU,    0xf8, 4);
 244     SBIT(PSPI,    0xf8, 3);
 245     SBIT(PC,      0xf8, 2);
 246     SBIT(PKBI,    0xf8, 1);
 247     SBIT(PI2C,    0xf8, 0);
 248 SFR(IP1H,    0xf7); // Interrupt priority 1 high
 249     #define PIEEH    0x80
 250     #define PSTH     0x40
 251     #define PCCUH    0x10
 252     #define PSPIH    0x08
 253     #define PCH      0x04
 254     #define PKBIH    0x02
 255     #define PI2CH    0x01
 256 SFR(KBCON,   0x94); // Keypad control register
 257     #define PATN     0x02
 258     #define _SEL     0x01
 259 SFR(KBMASK,  0x86); // Keypad interrupt mask register
 260 SFR(KBPATN,  0x93); // Keypad pattern register
 261 SFR(OCRAH,   0xef); // Output compare A register high
 262 SFR(OCRAL,   0xee); // Output compare A register low
 263 SFR(OCRBH,   0xfb); // Output compare B register high
 264 SFR(OCRBL,   0xfa); // Output compare B register low
 265 SFR(OCRCH,   0xfd); // Output compare C register high
 266 SFR(OCRCL,   0xfc); // Output compare C register low
 267 SFR(OCRDH,   0xff); // Output compare D register high
 268 SFR(OCRDL,   0xfe); // Output compare D register low
 269 SFR(P0,      0x80); // Port 0
 270     SBIT(P0_7,    0x80, 7);
 271     SBIT(P0_6,    0x80, 6);
 272     SBIT(P0_5,    0x80, 5);
 273     SBIT(P0_4,    0x80, 4);
 274     SBIT(P0_3,    0x80, 3);
 275     SBIT(P0_2,    0x80, 2);
 276     SBIT(P0_1,    0x80, 1);
 277     SBIT(P0_0,    0x80, 0);
 278     SBIT(T1,      0x80, 7);
 279     SBIT(KB7,     0x80, 7);
 280     SBIT(CMP_1,   0x80, 6);
 281     SBIT(KB6,     0x80, 6);
 282     SBIT(CMPREF,  0x80, 5);
 283     SBIT(KB5,     0x80, 5);
 284     SBIT(CIN1A,   0x80, 4);
 285     SBIT(KB4,     0x80, 4);
 286     SBIT(CIN1B,   0x80, 3);
 287     SBIT(KB3,     0x80, 3);
 288     SBIT(CIN2A,   0x80, 2);
 289     SBIT(KB2,     0x80, 2);
 290     SBIT(CIN2B,   0x80, 1);
 291     SBIT(KB1,     0x80, 1);
 292     SBIT(CMP_2,   0x80, 0);
 293     SBIT(KB0,     0x80, 0);
 294 SFR(P1,      0x90); // Port 1
 295     SBIT(P1_7,    0x90, 7);
 296     SBIT(P1_6,    0x90, 6);
 297     SBIT(P1_5,    0x90, 5);
 298     SBIT(P1_4,    0x90, 4);
 299     SBIT(P1_3,    0x90, 3);
 300     SBIT(P1_2,    0x90, 2);
 301     SBIT(P1_1,    0x90, 1);
 302     SBIT(P1_0,    0x90, 0);
 303     SBIT(OCC,     0x90, 7);
 304     SBIT(OCB,     0x90, 6);
 305     SBIT(RST,     0x90, 5);
 306     SBIT(INT1,    0x90, 4);
 307     SBIT(INT0,    0x90, 3);
 308     SBIT(SDA,     0x90, 3);
 309     SBIT(T0,      0x90, 2);
 310     SBIT(SCL,     0x90, 2);
 311     SBIT(RXD,     0x90, 1);
 312     SBIT(TXD,     0x90, 0);
 313 SFR(P2,      0xa0); // Port 2
 314     SBIT(P2_7,    0xa0, 7);
 315     SBIT(P2_6,    0xa0, 6);
 316     SBIT(P2_5,    0xa0, 5);
 317     SBIT(P2_4,    0xa0, 4);
 318     SBIT(P2_3,    0xa0, 3);
 319     SBIT(P2_2,    0xa0, 2);
 320     SBIT(P2_1,    0xa0, 1);
 321     SBIT(P2_0,    0xa0, 0);
 322     SBIT(ICA,     0xa0, 7);
 323     SBIT(OCA,     0xa0, 6);
 324     SBIT(SPICLK,  0xa0, 5);
 325     SBIT(SS,      0xa0, 4);
 326     SBIT(MISO,    0xa0, 3);
 327     SBIT(MOSI,    0xa0, 2);
 328     SBIT(OCD,     0xa0, 1);
 329     SBIT(ICB,     0xa0, 0);
 330 SFR(P3,      0xb0); // Port 3
 331     SBIT(P3_7,    0xb0, 7);
 332     SBIT(P3_6,    0xb0, 6);
 333     SBIT(P3_5,    0xb0, 5);
 334     SBIT(P3_4,    0xb0, 4);
 335     SBIT(P3_3,    0xb0, 3);
 336     SBIT(P3_2,    0xb0, 2);
 337     SBIT(P3_1,    0xb0, 1);
 338     SBIT(P3_0,    0xb0, 0);
 339     SBIT(XTAL1,   0xb0, 1);
 340     SBIT(XTAL2,   0xb0, 0);
 341 SFR(P0M1,    0x84); // Port 0 output mode 1
 342     #define P0M1_7   0x80
 343     #define P0M1_6   0x40
 344     #define P0M1_5   0x20
 345     #define P0M1_4   0x10
 346     #define P0M1_3   0x08
 347     #define P0M1_2   0x04
 348     #define P0M1_1   0x02
 349     #define P0M1_0   0x01
 350 SFR(P0M2,    0x85); // Port 0 output mode 2
 351     #define P0M2_7   0x80
 352     #define P0M2_6   0x40
 353     #define P0M2_5   0x20
 354     #define P0M2_4   0x10
 355     #define P0M2_3   0x08
 356     #define P0M2_2   0x04
 357     #define P0M2_1   0x02
 358     #define P0M2_0   0x01
 359 SFR(P1M1,    0x91); // Port 1 output mode 1
 360     #define P1M1_7   0x80
 361     #define P1M1_6   0x40
 362     #define P1M1_4   0x10
 363     #define P1M1_3   0x08
 364     #define P1M1_2   0x04
 365     #define P1M1_1   0x02
 366     #define P1M1_0   0x01
 367 SFR(P1M2,    0x92); // Port 1 output mode 2
 368     #define P1M2_7   0x80
 369     #define P1M2_6   0x40
 370     #define P1M2_4   0x10
 371     #define P1M2_3   0x08
 372     #define P1M2_2   0x04
 373     #define P1M2_1   0x02
 374     #define P1M2_0   0x01
 375 SFR(P2M1,    0xa4); // Port 2 output mode 1
 376     #define P2M1_7   0x80
 377     #define P2M1_6   0x40
 378     #define P2M1_5   0x20
 379     #define P2M1_4   0x10
 380     #define P2M1_3   0x08
 381     #define P2M1_2   0x04
 382     #define P2M1_1   0x02
 383     #define P2M1_0   0x01
 384 SFR(P2M2,    0xa5); // Port 2 output mode 2
 385     #define P2M2_7   0x80
 386     #define P2M2_6   0x40
 387     #define P2M2_5   0x20
 388     #define P2M2_4   0x10
 389     #define P2M2_3   0x08
 390     #define P2M2_2   0x04
 391     #define P2M2_1   0x02
 392     #define P2M2_0   0x01
 393 SFR(P3M1,    0xb1); // Port 3 output mode 1
 394     #define P3M1_1   0x02
 395     #define P3M1_0   0x01
 396 SFR(P3M2,    0xb2); // Port 3 output mode 2
 397     #define P3M2_1   0x02
 398     #define P3M2_0   0x01
 399 SFR(PCON,    0x87); // Power control register
 400     #define SMOD1    0x80
 401     #define SMOD0    0x40
 402     #define BOI      0x10
 403     #define GF1      0x08
 404     #define GF0      0x04
 405     #define PMOD1    0x02
 406     #define PMOD0    0x01
 407 SFR(PCONA,   0xb5); // Power control register A
 408     #define RTCPD    0x80
 409     #define DEEPD    0x40
 410     #define VCPD     0x20
 411     #define I2PD     0x08
 412     #define SPPD     0x04
 413     #define SPD      0x02
 414     #define CCUPD    0x01
 415 SFR(PSW,     0xd0); // Program status word
 416     SBIT(PSW_7,   0xd0, 7);
 417     SBIT(PSW_6,   0xd0, 6);
 418     SBIT(PSW_5,   0xd0, 5);
 419     SBIT(PSW_4,   0xd0, 4);
 420     SBIT(PSW_3,   0xd0, 3);
 421     SBIT(PSW_2,   0xd0, 2);
 422     SBIT(PSW_1,   0xd0, 1);
 423     SBIT(PSW_0,   0xd0, 0);
 424     SBIT(CY,      0xd0, 7);
 425     SBIT(AC,      0xd0, 6);
 426     SBIT(F0,      0xd0, 5);
 427     SBIT(RS1,     0xd0, 4);
 428     SBIT(RS0,     0xd0, 3);
 429     SBIT(OV,      0xd0, 2);
 430     SBIT(F1,      0xd0, 1);
 431     SBIT(P,       0xd0, 0);
 432 SFR(PT0AD,   0xf6); // Port 0 digital input disable
 433     #define PT0AD_5  0x20
 434     #define PT0AD_4  0x10
 435     #define PT0AD_3  0x08
 436     #define PT0AD_2  0x04
 437     #define PT0AD_1  0x02
 438 SFR(RSTSRC,  0xdf); // Reset source register
 439     #define BOIF     0x40
 440     #define BOF      0x20
 441     #define POF      0x10
 442     #define R_BK     0x08
 443     #define R_WD     0x04
 444     #define R_SF     0x02
 445     #define R_EX     0x01
 446 SFR(RTCCON,  0xd1); // RTC control
 447     #define RTCF     0x80
 448     #define RTCS1    0x40
 449     #define RTCS0    0x20
 450     #define ERTC     0x02
 451     #define RTCEN    0x01
 452 SFR(RTCH,    0xd2); // RTC register high
 453 SFR(RTCL,    0xd3); // RTC register low
 454 SFR(SADDR,   0xa9); // Serial port address register
 455 SFR(SADEN,   0xb9); // Serial port address enable
 456 SFR(SBUF,    0x99); // Serial Port data buffer register
 457 SFR(SCON,    0x98); // Serial port control
 458     SBIT(SCON_7,  0x98, 7);
 459     SBIT(SCON_6,  0x98, 6);
 460     SBIT(SCON_5,  0x98, 5);
 461     SBIT(SCON_4,  0x98, 4);
 462     SBIT(SCON_3,  0x98, 3);
 463     SBIT(SCON_2,  0x98, 2);
 464     SBIT(SCON_1,  0x98, 1);
 465     SBIT(SCON_0,  0x98, 0);
 466     SBIT(SM0,     0x98, 7);
 467     SBIT(FE,      0x98, 7);
 468     SBIT(SM1,     0x98, 6);
 469     SBIT(SM2,     0x98, 5);
 470     SBIT(REN,     0x98, 4);
 471     SBIT(TB8,     0x98, 3);
 472     SBIT(RB8,     0x98, 2);
 473     SBIT(TI,      0x98, 1);
 474     SBIT(RI,      0x98, 0);
 475 SFR(SSTAT,   0xba); // Serial port extended status register
 476     #define DBMOD    0x80
 477     #define INTLO    0x40
 478     #define CIDIS    0x20
 479     #define DBISEL   0x10
 480     #define FE       0x08
 481     #define BR       0x04
 482     #define OE       0x02
 483     #define STINT    0x01
 484 SFR(SP,      0x81); // Stack pointer
 485 SFR(SPCTL,   0xe2); // SPI control register
 486     #define SSIG     0x80
 487     #define SPEN     0x40
 488     #define DORD     0x20
 489     #define MSTR     0x10
 490     #define CPOL     0x08
 491     #define CPHA     0x04
 492     #define SPR1     0x02
 493     #define SPR0     0x01
 494 SFR(SPSTAT,  0xe1); // SPI status register
 495     #define SPIF     0x80
 496     #define WCOL     0x40
 497 SFR(SPDAT,   0xe3); // SPI data register
 498 SFR(TAMOD,   0x8f); // Timer 0 and 1 auxiliary mode
 499     #define T1M2     0x10
 500     #define T0M2     0x01
 501 SFR(TCON,    0x88); // Timer 0 and 1 control
 502     SBIT(TCON_7,  0x88, 7);
 503     SBIT(TCON_6,  0x88, 6);
 504     SBIT(TCON_5,  0x88, 5);
 505     SBIT(TCON_4,  0x88, 4);
 506     SBIT(TCON_3,  0x88, 3);
 507     SBIT(TCON_2,  0x88, 2);
 508     SBIT(TCON_1,  0x88, 1);
 509     SBIT(TCON_0,  0x88, 0);
 510     SBIT(TF1,     0x88, 7);
 511     SBIT(TR1,     0x88, 6);
 512     SBIT(TF0,     0x88, 5);
 513     SBIT(TR0,     0x88, 4);
 514     SBIT(IE1,     0x88, 3);
 515     SBIT(IT1,     0x88, 2);
 516     SBIT(IE0,     0x88, 1);
 517     SBIT(IT0,     0x88, 0);
 518 SFR(TCR20,   0xc8); // CCU control register 0
 519     SBIT(TCR20_7, 0xc8, 7);
 520     SBIT(TCR20_6, 0xc8, 6);
 521     SBIT(TCR20_5, 0xc8, 5);
 522     SBIT(TCR20_4, 0xc8, 4);
 523     SBIT(TCR20_3, 0xc8, 3);
 524     SBIT(TCR20_2, 0xc8, 2);
 525     SBIT(TCR20_1, 0xc8, 1);
 526     SBIT(TCR20_0, 0xc8, 0);
 527     SBIT(PLEEN,   0xc8, 7);
 528     SBIT(HLTRN,   0xc8, 6);
 529     SBIT(HLTEN,   0xc8, 5);
 530     SBIT(ALTCD,   0xc8, 4);
 531     SBIT(ALTAB,   0xc8, 3);
 532     SBIT(TDIR2,   0xc8, 2);
 533     SBIT(TMOD21,  0xc8, 1);
 534     SBIT(TMOD20,  0xc8, 0);
 535 SFR(TCR21,   0xf9); // CCU control register 1
 536     #define TCOU2    0x80
 537     #define PLLDV_3  0x08
 538     #define PLLDV_2  0x04
 539     #define PLLDV_1  0x02
 540     #define PLLDV_0  0x01
 541 SFR(TH0,     0x8c); // Timer 0 high
 542 SFR(TH1,     0x8d); // Timer 1 high
 543 SFR(TH2,     0xcd); // CCU timer high
 544 SFR(TICR2,   0xc9); // CCU interrupt control register
 545     #define TOIE2    0x80
 546     #define TOCIE2D  0x40
 547     #define TOCIE2C  0x20
 548     #define TOCIE2B  0x10
 549     #define TOCIE2A  0x08
 550     #define TICIE2B  0x02
 551     #define TICIE2A  0x01
 552 SFR(TIFR2,   0xe9); // CCU interrupt flag register
 553     #define TOIF2    0x80
 554     #define TOCF2D   0x40
 555     #define TOCF2C   0x20
 556     #define TOCF2B   0x10
 557     #define TOCF2A   0x08
 558     #define TICF2B   0x02
 559     #define TICF2A   0x01
 560 SFR(TISE2,   0xde); // CCU interrupt status encode register
 561     #define ENCINT_2 0x04
 562     #define ENCINT_1 0x02
 563     #define ENCINT_0 0x01
 564 SFR(TL0,     0x8a); // Timer 0 low
 565 SFR(TL1,     0x8b); // Timer 1 low
 566 SFR(TL2,     0xcc); // CCU timer low
 567 SFR(TMOD,    0x89); // Timer 0 and 1 mode
 568     #define T1GATE   0x80
 569     #define T1C_T    0x40
 570     #define T1M1     0x20
 571     #define T1M0     0x10
 572     #define T0GATE   0x08
 573     #define T0C_T    0x04
 574     #define T0M1     0x02
 575     #define T0M0     0x01
 576 SFR(TOR2H,   0xcf); // CCU reload register high
 577 SFR(TOR2L,   0xce); // CCU reload register low
 578 SFR(TPCR2H,  0xcb); // Prescaler control register high
 579     #define TPCR2H_1 0x02
 580     #define TPCR2H_0 0x01
 581 SFR(TPCR2L,  0xca); // Prescaler control register low
 582     #define TPCR2L_7 0x80
 583     #define TPCR2L_6 0x40
 584     #define TPCR2L_5 0x20
 585     #define TPCR2L_4 0x10
 586     #define TPCR2L_3 0x08
 587     #define TPCR2L_2 0x04
 588     #define TPCR2L_1 0x02
 589     #define TPCR2L_0 0x01
 590 SFR(TRIM,    0x96); // Internal oscillator trim register
 591     #define RCCLK    0x80
 592     #define ENCLK    0x40
 593     #define TRIM_5   0x20
 594     #define TRIM_4   0x10
 595     #define TRIM_3   0x08
 596     #define TRIM_2   0x04
 597     #define TRIM_1   0x02
 598     #define TRIM_0   0x01
 599 SFR(WDCON,   0xa7); // Watchdog control register
 600     #define PRE2     0x80
 601     #define PRE1     0x40
 602     #define PRE0     0x20
 603     #define WDRUN    0x04
 604     #define WDTOF    0x02
 605     #define WDCLK    0x01
 606 SFR(WDL,     0xc1); // Watchdog load
 607 SFR(WFEED1,  0xc2); // Watchdog feed 1
 608 SFR(WFEED2,  0xc3); // Watchdog feed 2
 609 SFRX(BODCFG,  0xffc8); // BOD configuration register
 610     #define BOICFG1  0x02
 611     #define BOICFG0  0x01
 612 SFRX(CLKCON,  0xffde); // CLOCK Control register
 613     #define CLKOK    0x80
 614     #define XTALWD   0x10
 615     #define CLKDBL   0x08
 616     #define FOSC2    0x04
 617     #define FOSC1    0x02
 618     #define FOSC0    0x01
 619 SFRX(PGACON1, 0xffe1); // PGA1 control register
 620     #define ENPGA1   0x80
 621     #define PGASEL1_1 0x40
 622     #define PGASEL1_0 0x20
 623     #define PGATRIM_1 0x10
 624     #define PGAG11   0x02
 625     #define PGAG10   0x01
 626 SFRX(PGACON1B, 0xffe4); // PGA1 control register B
 627     #define PGAENO   0x01
 628     #define FF1      0x01
 629 SFRX(PGA1TRIM8X16X, 0xffe3); // PGA1 trim register
 630     #define PGA1_16XTRIM3 0x80
 631     #define PGA1_16XTRIM2 0x40
 632     #define PGA1_16XTRIM1 0x20
 633     #define PGA1_16XTRIM0 0x10
 634     #define PGA1_8XTRIM3 0x08
 635     #define PGA1_8XTRIM2 0x04
 636     #define PGA1_8XTRIM1 0x02
 637     #define PGA1_8XTRIM0 0x01
 638 SFRX(PGA1TRIM2X4X, 0xffe2); // PGA1 trim register
 639     #define PGA1_4XTRIM3 0x80
 640     #define PGA1_4XTRIM2 0x40
 641     #define PGA1_4XTRIM1 0x20
 642     #define PGA1_4XTRIM0 0x10
 643     #define PGA1_2XTRIM3 0x08
 644     #define PGA1_2XTRIM2 0x04
 645     #define PGA1_2XTRIM1 0x02
 646     #define PGA1_2XTRIM0 0x01
 647 SFRX(RTCDATH, 0xffbf); // Real-time clock data register high
 648 SFRX(RTCDATL, 0xffbe); // Real-time clock data register low
 649 #endif /*REG_P89LPC9321_H*/