sdcc/device/include/mcs51/p89lpc9331.h

   1 /*-------------------------------------------------------------------------
   2    p89lpc9331.h - Register Declarations for NXP  the P89LPC9331/P89LPC9341
   3    (Based on user manual (UM10308_3) Rev. 03 - 17 June 2009)
   4
   5    Copyright (C) 2009, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef REG_P89LPC9331_H
  31 #define REG_P89LPC9331_H
  32
  33 #include <compiler.h>
  34
  35 SFR(ACC,     0xe0); // Accumulator
  36     SBIT(ACC_7,   0xe0, 7);
  37     SBIT(ACC_6,   0xe0, 6);
  38     SBIT(ACC_5,   0xe0, 5);
  39     SBIT(ACC_4,   0xe0, 4);
  40     SBIT(ACC_3,   0xe0, 3);
  41     SBIT(ACC_2,   0xe0, 2);
  42     SBIT(ACC_1,   0xe0, 1);
  43     SBIT(ACC_0,   0xe0, 0);
  44 SFR(ADCON0,  0x8e); // A/D control register 0
  45     #define ENBI0    0x80
  46     #define ENADCI0  0x40
  47     #define TMM0     0x20
  48     #define EDGE0    0x10
  49     #define ADCI0    0x08
  50     #define ENADC0   0x04
  51     #define ADCS01   0x02
  52     #define ADCS00   0x01
  53 SFR(ADCON1,  0x97); // A/D control register 1
  54     #define ENBI1    0x80
  55     #define ENADCI1  0x40
  56     #define TMM1     0x20
  57     #define EDGE1    0x10
  58     #define ADCI1    0x08
  59     #define ENADC1   0x04
  60     #define ADCS11   0x02
  61     #define ADCS10   0x01
  62 SFR(ADINS,   0xa3); // A/D input select
  63     #define ADI13    0x80
  64     #define ADI12    0x40
  65     #define ADI11    0x20
  66     #define ADI10    0x10
  67     #define ADI03    0x08
  68     #define ADI02    0x04
  69     #define ADI01    0x02
  70     #define ADI00    0x01
  71 SFR(ADMODA,  0xc0); // A/D mode register A
  72     SBIT(ADMODA_7, 0xc0, 7);
  73     SBIT(ADMODA_6, 0xc0, 6);
  74     SBIT(ADMODA_5, 0xc0, 5);
  75     SBIT(ADMODA_4, 0xc0, 4);
  76     SBIT(ADMODA_3, 0xc0, 3);
  77     SBIT(ADMODA_2, 0xc0, 2);
  78     SBIT(ADMODA_1, 0xc0, 1);
  79     SBIT(ADMODA_0, 0xc0, 0);
  80     SBIT(BNDI1,   0xc0, 7);
  81     SBIT(BURST1,  0xc0, 6);
  82     SBIT(SCC1,    0xc0, 5);
  83     SBIT(SCAN1,   0xc0, 4);
  84     SBIT(BNDI0,   0xc0, 3);
  85     SBIT(BURST0,  0xc0, 2);
  86     SBIT(SCC0,    0xc0, 1);
  87     SBIT(SCAN0,   0xc0, 0);
  88 SFR(ADMODB,  0xa1); // A/D mode register B
  89     #define CLK2     0x80
  90     #define CLK1     0x40
  91     #define CLK0     0x20
  92     #define INBND0   0x10
  93     #define ENDAC1   0x08
  94     #define ENDAC0   0x04
  95     #define BSA1     0x02
  96     #define BSA0     0x01
  97 SFR(AD0BH,   0xbb); // A/D_0 boundary high register
  98 SFR(AD0BL,   0xa6); // A/D_0 boundary low register
  99 SFR(AD0DAT0, 0xc5); // A/D_0 data register 0
 100 SFR(AD0DAT1, 0xc6); // A/D_0 data register 1
 101 SFR(AD0DAT2, 0xc7); // A/D_0 data register 2
 102 SFR(AD0DAT3, 0xf4); // A/D_0 data register 3
 103 SFR(AD1BH,   0xc4); // A/D_1 boundary high register
 104 SFR(AD1BL,   0xbc); // A/D_1 boundary low register
 105 SFR(AD1DAT0, 0xd5); // A/D_1 data register 0
 106 SFR(AD1DAT1, 0xd6); // A/D_1 data register 1
 107 SFR(AD1DAT2, 0xd7); // A/D_1 data register 2
 108 SFR(AD1DAT3, 0xf5); // A/D_1 data register 3
 109 SFR(AUXR1,   0xa2); // Auxiliary function register
 110     #define CLKLP    0x80
 111     #define EBRR     0x40
 112     #define ENT1     0x20
 113     #define ENT0     0x10
 114     #define SRST     0x08
 115     #define DPS      0x01
 116 SFR(B,       0xf0); // B register
 117     SBIT(B_7,     0xf0, 7);
 118     SBIT(B_6,     0xf0, 6);
 119     SBIT(B_5,     0xf0, 5);
 120     SBIT(B_4,     0xf0, 4);
 121     SBIT(B_3,     0xf0, 3);
 122     SBIT(B_2,     0xf0, 2);
 123     SBIT(B_1,     0xf0, 1);
 124     SBIT(B_0,     0xf0, 0);
 125 SFR(BRGR0,   0xbe); // Baud rate generator 0 rate low
 126 SFR(BRGR1,   0xbf); // Baud rate generator 0 rate high
 127 SFR(BRGCON,  0xbd); // Baud rate generator 0 control
 128     #define SBRGS    0x02
 129     #define BRGEN    0x01
 130 SFR(CMP1,    0xac); // Comparator 1 control register
 131     #define CE1      0x20
 132     #define CP1      0x10
 133     #define CN1      0x08
 134     #define OE1      0x04
 135     #define CO1      0x02
 136     #define CMF1     0x01
 137 SFR(CMP2,    0xad); // Comparator 2 control register
 138     #define CE2      0x20
 139     #define CP2      0x10
 140     #define CN2      0x08
 141     #define OE2      0x04
 142     #define CO2      0x02
 143     #define CMF2     0x01
 144 SFR(DIVM,    0x95); // CPU clock divide-by-M control
 145 SFR(DPH,     0x83); // Data pointer high
 146 SFR(DPL,     0x82); // Data pointer low
 147 SFR(FMADRH,  0xe7); // Program flash address high
 148 SFR(FMADRL,  0xe6); // Program flash address low
 149 SFR(FMCON,   0xe4); // Program flash control Read
 150     #define BUSY     0x80
 151     #define HVA      0x08
 152     #define HVE      0x04
 153     #define SV       0x02
 154     #define OI       0x01
 155     #define FMCMD_7  0x80
 156     #define FMCMD_6  0x40
 157     #define FMCMD_5  0x20
 158     #define FMCMD_4  0x10
 159     #define FMCMD_3  0x08
 160     #define FMCMD_2  0x04
 161     #define FMCMD_1  0x02
 162     #define FMCMD_0  0x01
 163 SFR(FMDATA,  0xe5); // Program flash data
 164 SFR(I2ADR,   0xdb); // I2C-bus slave address register
 165     #define I2ADR_6  0x80
 166     #define I2ADR_5  0x40
 167     #define I2ADR_4  0x20
 168     #define I2ADR_3  0x10
 169     #define I2ADR_2  0x08
 170     #define I2ADR_1  0x04
 171     #define I2ADR_0  0x02
 172     #define GC       0x01
 173 SFR(I2CON,   0xd8); // I2C-bus control register
 174     SBIT(I2CON_7, 0xd8, 7);
 175     SBIT(I2CON_6, 0xd8, 6);
 176     SBIT(I2CON_5, 0xd8, 5);
 177     SBIT(I2CON_4, 0xd8, 4);
 178     SBIT(I2CON_3, 0xd8, 3);
 179     SBIT(I2CON_2, 0xd8, 2);
 180     SBIT(I2CON_1, 0xd8, 1);
 181     SBIT(I2CON_0, 0xd8, 0);
 182     SBIT(I2EN,    0xd8, 6);
 183     SBIT(STA,     0xd8, 5);
 184     SBIT(STO,     0xd8, 4);
 185     SBIT(SI,      0xd8, 3);
 186     SBIT(AA,      0xd8, 2);
 187     SBIT(CRSEL,   0xd8, 0);
 188 SFR(I2DAT,   0xda); // I2C-bus data register
 189 SFR(I2SCLH,  0xdd); // Serial clock generator/SCL duty cycle register high
 190 SFR(I2SCLL,  0xdc); // Serial clock generator/SCL duty cycle register low
 191 SFR(I2STAT,  0xd9); // I2C-bus status register
 192     #define STA_4    0x80
 193     #define STA_3    0x40
 194     #define STA_2    0x20
 195     #define STA_1    0x10
 196     #define STA_0    0x08
 197 SFR(IEN0,    0xa8); // Interrupt enable 0
 198     SBIT(IEN0_7,  0xa8, 7);
 199     SBIT(IEN0_6,  0xa8, 6);
 200     SBIT(IEN0_5,  0xa8, 5);
 201     SBIT(IEN0_4,  0xa8, 4);
 202     SBIT(IEN0_3,  0xa8, 3);
 203     SBIT(IEN0_2,  0xa8, 2);
 204     SBIT(IEN0_1,  0xa8, 1);
 205     SBIT(IEN0_0,  0xa8, 0);
 206     SBIT(EA,      0xa8, 7);
 207     SBIT(EWDRT,   0xa8, 6);
 208     SBIT(EBO,     0xa8, 5);
 209     SBIT(ES,      0xa8, 4);
 210     SBIT(ESR,     0xa8, 4);
 211     SBIT(ET1,     0xa8, 3);
 212     SBIT(EX1,     0xa8, 2);
 213     SBIT(ET0,     0xa8, 1);
 214     SBIT(EX0,     0xa8, 0);
 215 SFR(IEN1,    0xe8); // Interrupt enable 1
 216     SBIT(IEN1_7,  0xe8, 7);
 217     SBIT(IEN1_6,  0xe8, 6);
 218     SBIT(IEN1_5,  0xe8, 5);
 219     SBIT(IEN1_4,  0xe8, 4);
 220     SBIT(IEN1_3,  0xe8, 3);
 221     SBIT(IEN1_2,  0xe8, 2);
 222     SBIT(IEN1_1,  0xe8, 1);
 223     SBIT(IEN1_0,  0xe8, 0);
 224     SBIT(EAD,     0xe8, 7);
 225     SBIT(EST,     0xe8, 6);
 226     SBIT(ESPI,    0xe8, 3);
 227     SBIT(EC,      0xe8, 2);
 228     SBIT(EKBI,    0xe8, 1);
 229     SBIT(EI2C,    0xe8, 0);
 230 SFR(IP0,     0xb8); // Interrupt priority 0
 231     SBIT(IP0_7,   0xb8, 7);
 232     SBIT(IP0_6,   0xb8, 6);
 233     SBIT(IP0_5,   0xb8, 5);
 234     SBIT(IP0_4,   0xb8, 4);
 235     SBIT(IP0_3,   0xb8, 3);
 236     SBIT(IP0_2,   0xb8, 2);
 237     SBIT(IP0_1,   0xb8, 1);
 238     SBIT(IP0_0,   0xb8, 0);
 239     SBIT(PWDRT,   0xb8, 6);
 240     SBIT(PBO,     0xb8, 5);
 241     SBIT(PS,      0xb8, 4);
 242     SBIT(PSR,     0xb8, 4);
 243     SBIT(PT1,     0xb8, 3);
 244     SBIT(PX1,     0xb8, 2);
 245     SBIT(PT0,     0xb8, 1);
 246     SBIT(PX0,     0xb8, 0);
 247 SFR(IP0H,    0xb7); // Interrupt priority 0 high
 248     #define PWDRTH   0x40
 249     #define PBOH     0x20
 250     #define PSH      0x10
 251     #define PSRH     0x10
 252     #define PT1H     0x08
 253     #define PX1H     0x04
 254     #define PT0H     0x02
 255     #define PX0H     0x01
 256 SFR(IP1,     0xf8); // Interrupt priority 1
 257     SBIT(IP1_7,   0xf8, 7);
 258     SBIT(IP1_6,   0xf8, 6);
 259     SBIT(IP1_5,   0xf8, 5);
 260     SBIT(IP1_4,   0xf8, 4);
 261     SBIT(IP1_3,   0xf8, 3);
 262     SBIT(IP1_2,   0xf8, 2);
 263     SBIT(IP1_1,   0xf8, 1);
 264     SBIT(IP1_0,   0xf8, 0);
 265     SBIT(PAD,     0xf8, 7);
 266     SBIT(PST,     0xf8, 6);
 267     SBIT(PSPI,    0xf8, 3);
 268     SBIT(PC,      0xf8, 2);
 269     SBIT(PKBI,    0xf8, 1);
 270     SBIT(PI2C,    0xf8, 0);
 271 SFR(IP1H,    0xf7); // Interrupt priority 1 high
 272     #define PADH     0x80
 273     #define PSTH     0x40
 274     #define PSPIH    0x08
 275     #define PCH      0x04
 276     #define PKBIH    0x02
 277     #define PI2CH    0x01
 278 SFR(KBCON,   0x94); // Keypad control register
 279     #define PATN     0x02
 280     #define _SEL     0x01
 281 SFR(KBMASK,  0x86); // Keypad interrupt mask register
 282 SFR(KBPATN,  0x93); // Keypad pattern register
 283 SFR(P0,      0x80); // Port 0
 284     SBIT(P0_7,    0x80, 7);
 285     SBIT(P0_6,    0x80, 6);
 286     SBIT(P0_5,    0x80, 5);
 287     SBIT(P0_4,    0x80, 4);
 288     SBIT(P0_3,    0x80, 3);
 289     SBIT(P0_2,    0x80, 2);
 290     SBIT(P0_1,    0x80, 1);
 291     SBIT(P0_0,    0x80, 0);
 292     SBIT(T1,      0x80, 7);
 293     SBIT(KB7,     0x80, 7);
 294     SBIT(CMP_1,   0x80, 6);
 295     SBIT(KB6,     0x80, 6);
 296     SBIT(CMPREF,  0x80, 5);
 297     SBIT(KB5,     0x80, 5);
 298     SBIT(CIN1A,   0x80, 4);
 299     SBIT(KB4,     0x80, 4);
 300     SBIT(CIN1B,   0x80, 3);
 301     SBIT(KB3,     0x80, 3);
 302     SBIT(CIN2A,   0x80, 2);
 303     SBIT(KB2,     0x80, 2);
 304     SBIT(CIN2B,   0x80, 1);
 305     SBIT(KB1,     0x80, 1);
 306     SBIT(CMP_2,   0x80, 0);
 307     SBIT(KB0,     0x80, 0);
 308 SFR(P1,      0x90); // Port 1
 309     SBIT(P1_7,    0x90, 7);
 310     SBIT(P1_6,    0x90, 6);
 311     SBIT(P1_5,    0x90, 5);
 312     SBIT(P1_4,    0x90, 4);
 313     SBIT(P1_3,    0x90, 3);
 314     SBIT(P1_2,    0x90, 2);
 315     SBIT(P1_1,    0x90, 1);
 316     SBIT(P1_0,    0x90, 0);
 317     SBIT(RST,     0x90, 5);
 318     SBIT(INT1,    0x90, 4);
 319     SBIT(INT0,    0x90, 3);
 320     SBIT(SDA,     0x90, 3);
 321     SBIT(T0,      0x90, 2);
 322     SBIT(SCL,     0x90, 2);
 323     SBIT(RXD,     0x90, 1);
 324     SBIT(TXD,     0x90, 0);
 325 SFR(P2,      0xa0); // Port 2
 326     SBIT(P2_7,    0xa0, 7);
 327     SBIT(P2_6,    0xa0, 6);
 328     SBIT(P2_5,    0xa0, 5);
 329     SBIT(P2_4,    0xa0, 4);
 330     SBIT(P2_3,    0xa0, 3);
 331     SBIT(P2_2,    0xa0, 2);
 332     SBIT(P2_1,    0xa0, 1);
 333     SBIT(P2_0,    0xa0, 0);
 334     SBIT(SPICLK,  0xa0, 5);
 335     SBIT(SS,      0xa0, 4);
 336     SBIT(MISO,    0xa0, 3);
 337     SBIT(MOSI,    0xa0, 2);
 338 SFR(P3,      0xb0); // Port 3
 339     SBIT(P3_7,    0xb0, 7);
 340     SBIT(P3_6,    0xb0, 6);
 341     SBIT(P3_5,    0xb0, 5);
 342     SBIT(P3_4,    0xb0, 4);
 343     SBIT(P3_3,    0xb0, 3);
 344     SBIT(P3_2,    0xb0, 2);
 345     SBIT(P3_1,    0xb0, 1);
 346     SBIT(P3_0,    0xb0, 0);
 347     SBIT(XTAL1,   0xb0, 1);
 348     SBIT(XTAL2,   0xb0, 0);
 349 SFR(P0M1,    0x84); // Port 0 output mode 1
 350     #define P0M1_7   0x80
 351     #define P0M1_6   0x40
 352     #define P0M1_5   0x20
 353     #define P0M1_4   0x10
 354     #define P0M1_3   0x08
 355     #define P0M1_2   0x04
 356     #define P0M1_1   0x02
 357     #define P0M1_0   0x01
 358 SFR(P0M2,    0x85); // Port 0 output mode 2
 359     #define P0M2_7   0x80
 360     #define P0M2_6   0x40
 361     #define P0M2_5   0x20
 362     #define P0M2_4   0x10
 363     #define P0M2_3   0x08
 364     #define P0M2_2   0x04
 365     #define P0M2_1   0x02
 366     #define P0M2_0   0x01
 367 SFR(P1M1,    0x91); // Port 1 output mode 1
 368     #define P1M1_7   0x80
 369     #define P1M1_6   0x40
 370     #define P1M1_4   0x10
 371     #define P1M1_3   0x08
 372     #define P1M1_2   0x04
 373     #define P1M1_1   0x02
 374     #define P1M1_0   0x01
 375 SFR(P1M2,    0x92); // Port 1 output mode 2
 376     #define P1M2_7   0x80
 377     #define P1M2_6   0x40
 378     #define P1M2_4   0x10
 379     #define P1M2_3   0x08
 380     #define P1M2_2   0x04
 381     #define P1M2_1   0x02
 382     #define P1M2_0   0x01
 383 SFR(P2M1,    0xa4); // Port 2 output mode 1
 384     #define P2M1_7   0x80
 385     #define P2M1_6   0x40
 386     #define P2M1_5   0x20
 387     #define P2M1_4   0x10
 388     #define P2M1_3   0x08
 389     #define P2M1_2   0x04
 390     #define P2M1_1   0x02
 391     #define P2M1_0   0x01
 392 SFR(P2M2,    0xa5); // Port 2 output mode 2
 393     #define P2M2_7   0x80
 394     #define P2M2_6   0x40
 395     #define P2M2_5   0x20
 396     #define P2M2_4   0x10
 397     #define P2M2_3   0x08
 398     #define P2M2_2   0x04
 399     #define P2M2_1   0x02
 400     #define P2M2_0   0x01
 401 SFR(P3M1,    0xb1); // Port 3 output mode 1
 402     #define P3M1_1   0x02
 403     #define P3M1_0   0x01
 404 SFR(P3M2,    0xb2); // Port 3 output mode 2
 405     #define P3M2_1   0x02
 406     #define P3M2_0   0x01
 407 SFR(PCON,    0x87); // Power control register
 408     #define SMOD1    0x80
 409     #define SMOD0    0x40
 410     #define BOI      0x10
 411     #define GF1      0x08
 412     #define GF0      0x04
 413     #define PMOD1    0x02
 414     #define PMOD0    0x01
 415 SFR(PCONA,   0xb5); // Power control register A
 416     #define RTCPD    0x80
 417     #define VCPD     0x20
 418     #define ADPD     0x10
 419     #define I2PD     0x08
 420     #define SPPD     0x04
 421     #define SPD      0x02
 422 SFR(PSW,     0xd0); // Programstatus word
 423     SBIT(PSW_7,   0xd0, 7);
 424     SBIT(PSW_6,   0xd0, 6);
 425     SBIT(PSW_5,   0xd0, 5);
 426     SBIT(PSW_4,   0xd0, 4);
 427     SBIT(PSW_3,   0xd0, 3);
 428     SBIT(PSW_2,   0xd0, 2);
 429     SBIT(PSW_1,   0xd0, 1);
 430     SBIT(PSW_0,   0xd0, 0);
 431     SBIT(CY,      0xd0, 7);
 432     SBIT(AC,      0xd0, 6);
 433     SBIT(F0,      0xd0, 5);
 434     SBIT(RS1,     0xd0, 4);
 435     SBIT(RS0,     0xd0, 3);
 436     SBIT(OV,      0xd0, 2);
 437     SBIT(F1,      0xd0, 1);
 438     SBIT(P,       0xd0, 0);
 439 SFR(PT0AD,   0xf6); // Port 0 digital input disable
 440     #define PT0AD_5  0x20
 441     #define PT0AD_4  0x10
 442     #define PT0AD_3  0x08
 443     #define PT0AD_2  0x04
 444     #define PT0AD_1  0x02
 445 SFR(RSTSRC,  0xdf); // Reset source register
 446     #define BOIF     0x40
 447     #define BOF      0x20
 448     #define POF      0x10
 449     #define R_BK     0x08
 450     #define R_WD     0x04
 451     #define R_SF     0x02
 452     #define R_EX     0x01
 453 SFR(RTCCON,  0xd1); // RTC control
 454     #define RTCF     0x80
 455     #define RTCS1    0x40
 456     #define RTCS0    0x20
 457     #define ERTC     0x02
 458     #define RTCEN    0x01
 459 SFR(RTCH,    0xd2); // RTC register high
 460 SFR(RTCL,    0xd3); // RTC register low
 461 SFR(SADDR,   0xa9); // Serial port address register
 462 SFR(SADEN,   0xb9); // Serial port address enable
 463 SFR(SBUF,    0x99); // Serial Port data buffer register
 464 SFR(SCON,    0x98); // Serial port control
 465     SBIT(SCON_7,  0x98, 7);
 466     SBIT(SCON_6,  0x98, 6);
 467     SBIT(SCON_5,  0x98, 5);
 468     SBIT(SCON_4,  0x98, 4);
 469     SBIT(SCON_3,  0x98, 3);
 470     SBIT(SCON_2,  0x98, 2);
 471     SBIT(SCON_1,  0x98, 1);
 472     SBIT(SCON_0,  0x98, 0);
 473     SBIT(SM0,     0x98, 7);
 474     SBIT(FE,      0x98, 7);
 475     SBIT(SM1,     0x98, 6);
 476     SBIT(SM2,     0x98, 5);
 477     SBIT(REN,     0x98, 4);
 478     SBIT(TB8,     0x98, 3);
 479     SBIT(RB8,     0x98, 2);
 480     SBIT(TI,      0x98, 1);
 481     SBIT(RI,      0x98, 0);
 482 SFR(SSTAT,   0xba); // Serial port extended status register
 483     #define DBMOD    0x80
 484     #define INTLO    0x40
 485     #define CIDIS    0x20
 486     #define DBISEL   0x10
 487     #define FE       0x08
 488     #define BR       0x04
 489     #define OE       0x02
 490     #define STINT    0x01
 491 SFR(SP,      0x81); // Stack pointer
 492 SFR(SPCTL,   0xe2); // SPI control register
 493     #define SSIG     0x80
 494     #define SPEN     0x40
 495     #define DORD     0x20
 496     #define MSTR     0x10
 497     #define CPOL     0x08
 498     #define CPHA     0x04
 499     #define SPR1     0x02
 500     #define SPR0     0x01
 501 SFR(SPSTAT,  0xe1); // SPI status register
 502     #define SPIF     0x80
 503     #define WCOL     0x40
 504 SFR(SPDAT,   0xe3); // SPI data register
 505 SFR(TAMOD,   0x8f); // Timer 0 and 1 auxiliary mode
 506     #define T1M2     0x10
 507     #define T0M2     0x01
 508 SFR(TCON,    0x88); // Timer 0 and 1 control
 509     SBIT(TCON_7,  0x88, 7);
 510     SBIT(TCON_6,  0x88, 6);
 511     SBIT(TCON_5,  0x88, 5);
 512     SBIT(TCON_4,  0x88, 4);
 513     SBIT(TCON_3,  0x88, 3);
 514     SBIT(TCON_2,  0x88, 2);
 515     SBIT(TCON_1,  0x88, 1);
 516     SBIT(TCON_0,  0x88, 0);
 517     SBIT(TF1,     0x88, 7);
 518     SBIT(TR1,     0x88, 6);
 519     SBIT(TF0,     0x88, 5);
 520     SBIT(TR0,     0x88, 4);
 521     SBIT(IE1,     0x88, 3);
 522     SBIT(IT1,     0x88, 2);
 523     SBIT(IE0,     0x88, 1);
 524     SBIT(IT0,     0x88, 0);
 525 SFR(TH0,     0x8c); // Timer 0 high
 526 SFR(TH1,     0x8d); // Timer 1 high
 527 SFR(TL0,     0x8a); // Timer 0 low
 528 SFR(TL1,     0x8b); // Timer 1 low
 529 SFR(TMOD,    0x89); // Timer 0 and 1 mode
 530     #define T1GATE   0x80
 531     #define T1C_T    0x40
 532     #define T1M1     0x20
 533     #define T1M0     0x10
 534     #define T0GATE   0x08
 535     #define T0C_T    0x04
 536     #define T0M1     0x02
 537     #define T0M0     0x01
 538 SFR(TRIM,    0x96); // Internal oscillator trim register
 539     #define RCCLK    0x80
 540     #define ENCLK    0x40
 541     #define TRIM_5   0x20
 542     #define TRIM_4   0x10
 543     #define TRIM_3   0x08
 544     #define TRIM_2   0x04
 545     #define TRIM_1   0x02
 546     #define TRIM_0   0x01
 547 SFR(WDCON,   0xa7); // Watchdog control register
 548     #define PRE2     0x80
 549     #define PRE1     0x40
 550     #define PRE0     0x20
 551     #define WDRUN    0x04
 552     #define WDTOF    0x02
 553     #define WDCLK    0x01
 554 SFR(WDL,     0xc1); // Watchdog load
 555 SFR(WFEED1,  0xc2); // Watchdog feed 1
 556 SFR(WFEED2,  0xc3); // Watchdog feed 2
 557 SFRX(BODCFG,  0xffc8); // BOD configuration register
 558     #define BOICFG1  0x02
 559     #define BOICFG0  0x01
 560 SFRX(CLKCON,  0xffde); // CLOCK Control register
 561     #define CLKOK    0x80
 562     #define XTALWD   0x10
 563     #define CLKDBL   0x08
 564     #define FOSC2    0x04
 565     #define FOSC1    0x02
 566     #define FOSC0    0x01
 567 SFRX(TPSCON,  0xffca); // Temperature sensor control register
 568     #define TSEL1    0x08
 569     #define TSEL0    0x04
 570 SFRX(RTCDATH, 0xffbf); // Real-time clock data register high
 571 SFRX(RTCDATL, 0xffbe); // Real-time clock data register low
 572 #endif /*REG_P89LPC9331_H*/