sdcc/device/include/mcs51/p89lpc9351.h

   1 /*-------------------------------------------------------------------------
   2    p89lpc9351.h - Register Declarations for NXP  the P89LPC9351/P89LPC9361
   3    (Based on user manual (UM10308_3) Rev. 03 - 17 June 2009)
   4
   5    Copyright (C) 2009, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 #ifndef REG_P89LPC9351_H
  31 #define REG_P89LPC9351_H
  32
  33 #include <compiler.h>
  34
  35 SFR(ACC,     0xe0); // Accumulator
  36     SBIT(ACC_7,   0xe0, 7);
  37     SBIT(ACC_6,   0xe0, 6);
  38     SBIT(ACC_5,   0xe0, 5);
  39     SBIT(ACC_4,   0xe0, 4);
  40     SBIT(ACC_3,   0xe0, 3);
  41     SBIT(ACC_2,   0xe0, 2);
  42     SBIT(ACC_1,   0xe0, 1);
  43     SBIT(ACC_0,   0xe0, 0);
  44 SFR(ADCON0,  0x8e); // A/D control register 0
  45     #define ENBI0    0x80
  46     #define ENADCI0  0x40
  47     #define TMM0     0x20
  48     #define EDGE0    0x10
  49     #define ADCI0    0x08
  50     #define ENADC0   0x04
  51     #define ADCS01   0x02
  52     #define ADCS00   0x01
  53 SFR(ADCON1,  0x97); // A/D control register 1
  54     #define ENBI1    0x80
  55     #define ENADCI1  0x40
  56     #define TMM1     0x20
  57     #define EDGE1    0x10
  58     #define ADCI1    0x08
  59     #define ENADC1   0x04
  60     #define ADCS11   0x02
  61     #define ADCS10   0x01
  62 SFR(ADINS,   0xa3); // A/D input select
  63     #define ADI13    0x80
  64     #define ADI12    0x40
  65     #define ADI11    0x20
  66     #define ADI10    0x10
  67     #define ADI03    0x08
  68     #define ADI02    0x04
  69     #define ADI01    0x02
  70     #define ADI00    0x01
  71 SFR(ADMODA,  0xc0); // A/D mode register A
  72     SBIT(ADMODA_7, 0xc0, 7);
  73     SBIT(ADMODA_6, 0xc0, 6);
  74     SBIT(ADMODA_5, 0xc0, 5);
  75     SBIT(ADMODA_4, 0xc0, 4);
  76     SBIT(ADMODA_3, 0xc0, 3);
  77     SBIT(ADMODA_2, 0xc0, 2);
  78     SBIT(ADMODA_1, 0xc0, 1);
  79     SBIT(ADMODA_0, 0xc0, 0);
  80     SBIT(BNDI1,   0xc0, 7);
  81     SBIT(BURST1,  0xc0, 6);
  82     SBIT(SCC1,    0xc0, 5);
  83     SBIT(SCAN1,   0xc0, 4);
  84     SBIT(BNDI0,   0xc0, 3);
  85     SBIT(BURST0,  0xc0, 2);
  86     SBIT(SCC0,    0xc0, 1);
  87     SBIT(SCAN0,   0xc0, 0);
  88 SFR(ADMODB,  0xa1); // A/D mode register B
  89     #define CLK2     0x80
  90     #define CLK1     0x40
  91     #define CLK0     0x20
  92     #define INBND0   0x10
  93     #define ENDAC1   0x08
  94     #define ENDAC0   0x04
  95     #define BSA1     0x02
  96     #define BSA0     0x01
  97 SFR(AD0BH,   0xbb); // A/D_0 boundary high register
  98 SFR(AD0BL,   0xa6); // A/D_0 boundary low register
  99 SFR(AD0DAT0, 0xc5); // A/D_0 data register 0
 100 SFR(AD0DAT1, 0xc6); // A/D_0 data register 1
 101 SFR(AD0DAT2, 0xc7); // A/D_0 data register 2
 102 SFR(AD0DAT3, 0xf4); // A/D_0 data register 3
 103 SFR(AD1BH,   0xc4); // A/D_1 boundary high register
 104 SFR(AD1BL,   0xbc); // A/D_1 boundary low register
 105 SFR(AD1DAT0, 0xd5); // A/D_1 data register 0
 106 SFR(AD1DAT1, 0xd6); // A/D_1 data register 1
 107 SFR(AD1DAT2, 0xd7); // A/D_1 data register 2
 108 SFR(AD1DAT3, 0xf5); // A/D_1 data register 3
 109 SFR(AUXR1,   0xa2); // Auxiliary function register
 110     #define CLKLP    0x80
 111     #define EBRR     0x40
 112     #define ENT1     0x20
 113     #define ENT0     0x10
 114     #define SRST     0x08
 115     #define DPS      0x01
 116 SFR(B,       0xf0); // B register
 117     SBIT(B_7,     0xf0, 7);
 118     SBIT(B_6,     0xf0, 6);
 119     SBIT(B_5,     0xf0, 5);
 120     SBIT(B_4,     0xf0, 4);
 121     SBIT(B_3,     0xf0, 3);
 122     SBIT(B_2,     0xf0, 2);
 123     SBIT(B_1,     0xf0, 1);
 124     SBIT(B_0,     0xf0, 0);
 125 SFR(BRGR0,   0xbe); // Baud rate generator 0 rate low
 126 SFR(BRGR1,   0xbf); // Baud rate generator 0 rate high
 127 SFR(BRGCON,  0xbd); // Baud rate generator 0 control
 128     #define SBRGS    0x02
 129     #define BRGEN    0x01
 130 SFR(CCCRA,   0xea); // Capture compare A control register
 131     #define ICECA2   0x80
 132     #define ICECA1   0x40
 133     #define ICECA0   0x20
 134     #define ICESA    0x10
 135     #define ICNFA    0x08
 136     #define FCOA     0x04
 137     #define OCMA1    0x02
 138     #define OCMA0    0x01
 139 SFR(CCCRB,   0xeb); // Capture compare B control register
 140     #define ICECB2   0x80
 141     #define ICECB1   0x40
 142     #define ICECB0   0x20
 143     #define ICESB    0x10
 144     #define ICNFB    0x08
 145     #define FCOB     0x04
 146     #define OCMB1    0x02
 147     #define OCMB0    0x01
 148 SFR(CCCRC,   0xec); // Capture compare C control register
 149     #define FCOC     0x04
 150     #define OCMC1    0x02
 151     #define OCMC0    0x01
 152 SFR(CCCRD,   0xed); // Capture compare D control register
 153     #define FCOD     0x04
 154     #define OCMD1    0x02
 155     #define OCMD0    0x01
 156 SFR(CMP1,    0xac); // Comparator 1 control register
 157     #define CE1      0x20
 158     #define CP1      0x10
 159     #define CN1      0x08
 160     #define OE1      0x04
 161     #define CO1      0x02
 162     #define CMF1     0x01
 163 SFR(CMP2,    0xad); // Comparator 2 control register
 164     #define CE2      0x20
 165     #define CP2      0x10
 166     #define CN2      0x08
 167     #define OE2      0x04
 168     #define CO2      0x02
 169     #define CMF2     0x01
 170 SFR(DEECON,  0xf1); // Data EEPROM control register
 171     #define EEIF     0x80
 172     #define HVERR    0x40
 173     #define ECTL1    0x20
 174     #define ECTL0    0x10
 175     #define EWERR1   0x04
 176     #define EWERR0   0x02
 177     #define EADR8    0x01
 178 SFR(DEEDAT,  0xf2); // Data EEPROM data register
 179 SFR(DEEADR,  0xf3); // Data EEPROM address register
 180 SFR(DIVM,    0x95); // CPU clock divide-by-M control
 181 SFR(DPH,     0x83); // Data pointer high
 182 SFR(DPL,     0x82); // Data pointer low
 183 SFR(FMADRH,  0xe7); // Program flash address high
 184 SFR(FMADRL,  0xe6); // Program flash address low
 185 SFR(FMCON,   0xe4); // Program flash control Read
 186     #define BUSY     0x80
 187     #define HVA      0x08
 188     #define HVE      0x04
 189     #define SV       0x02
 190     #define OI       0x01
 191     #define FMCMD_7  0x80
 192     #define FMCMD_6  0x40
 193     #define FMCMD_5  0x20
 194     #define FMCMD_4  0x10
 195     #define FMCMD_3  0x08
 196     #define FMCMD_2  0x04
 197     #define FMCMD_1  0x02
 198     #define FMCMD_0  0x01
 199 SFR(FMDATA,  0xe5); // Program flash data
 200 SFR(I2ADR,   0xdb); // I2C-bus slave address register
 201     #define I2ADR_6  0x80
 202     #define I2ADR_5  0x40
 203     #define I2ADR_4  0x20
 204     #define I2ADR_3  0x10
 205     #define I2ADR_2  0x08
 206     #define I2ADR_1  0x04
 207     #define I2ADR_0  0x02
 208     #define GC       0x01
 209 SFR(I2CON,   0xd8); // I2C-bus control register
 210     SBIT(I2CON_7, 0xd8, 7);
 211     SBIT(I2CON_6, 0xd8, 6);
 212     SBIT(I2CON_5, 0xd8, 5);
 213     SBIT(I2CON_4, 0xd8, 4);
 214     SBIT(I2CON_3, 0xd8, 3);
 215     SBIT(I2CON_2, 0xd8, 2);
 216     SBIT(I2CON_1, 0xd8, 1);
 217     SBIT(I2CON_0, 0xd8, 0);
 218     SBIT(I2EN,    0xd8, 6);
 219     SBIT(STA,     0xd8, 5);
 220     SBIT(STO,     0xd8, 4);
 221     SBIT(SI,      0xd8, 3);
 222     SBIT(AA,      0xd8, 2);
 223     SBIT(CRSEL,   0xd8, 0);
 224 SFR(I2DAT,   0xda); // I2C-bus data register
 225 SFR(I2SCLH,  0xdd); // Serial clock generator/SCL duty cycle register high
 226 SFR(I2SCLL,  0xdc); // Serial clock generator/SCL duty cycle register low
 227 SFR(I2STAT,  0xd9); // I2C-bus status register
 228     #define STA_4    0x80
 229     #define STA_3    0x40
 230     #define STA_2    0x20
 231     #define STA_1    0x10
 232     #define STA_0    0x08
 233 SFR(ICRAH,   0xab); // Input capture A register high
 234 SFR(ICRAL,   0xaa); // Input capture A register low
 235 SFR(ICRBH,   0xaf); // Input capture B register high
 236 SFR(ICRBL,   0xae); // Input capture B register low
 237 SFR(IEN0,    0xa8); // Interrupt enable 0
 238     SBIT(IEN0_7,  0xa8, 7);
 239     SBIT(IEN0_6,  0xa8, 6);
 240     SBIT(IEN0_5,  0xa8, 5);
 241     SBIT(IEN0_4,  0xa8, 4);
 242     SBIT(IEN0_3,  0xa8, 3);
 243     SBIT(IEN0_2,  0xa8, 2);
 244     SBIT(IEN0_1,  0xa8, 1);
 245     SBIT(IEN0_0,  0xa8, 0);
 246     SBIT(EA,      0xa8, 7);
 247     SBIT(EWDRT,   0xa8, 6);
 248     SBIT(EBO,     0xa8, 5);
 249     SBIT(ES,      0xa8, 4);
 250     SBIT(ESR,     0xa8, 4);
 251     SBIT(ET1,     0xa8, 3);
 252     SBIT(EX1,     0xa8, 2);
 253     SBIT(ET0,     0xa8, 1);
 254     SBIT(EX0,     0xa8, 0);
 255 SFR(IEN1,    0xe8); // Interrupt enable 1
 256     SBIT(IEN1_7,  0xe8, 7);
 257     SBIT(IEN1_6,  0xe8, 6);
 258     SBIT(IEN1_5,  0xe8, 5);
 259     SBIT(IEN1_4,  0xe8, 4);
 260     SBIT(IEN1_3,  0xe8, 3);
 261     SBIT(IEN1_2,  0xe8, 2);
 262     SBIT(IEN1_1,  0xe8, 1);
 263     SBIT(IEN1_0,  0xe8, 0);
 264     SBIT(EADEE,   0xe8, 7);
 265     SBIT(EST,     0xe8, 6);
 266     SBIT(ECCU,    0xe8, 4);
 267     SBIT(ESPI,    0xe8, 3);
 268     SBIT(EC,      0xe8, 2);
 269     SBIT(EKBI,    0xe8, 1);
 270     SBIT(EI2C,    0xe8, 0);
 271 SFR(IP0,     0xb8); // Interrupt priority 0
 272     SBIT(IP0_7,   0xb8, 7);
 273     SBIT(IP0_6,   0xb8, 6);
 274     SBIT(IP0_5,   0xb8, 5);
 275     SBIT(IP0_4,   0xb8, 4);
 276     SBIT(IP0_3,   0xb8, 3);
 277     SBIT(IP0_2,   0xb8, 2);
 278     SBIT(IP0_1,   0xb8, 1);
 279     SBIT(IP0_0,   0xb8, 0);
 280     SBIT(PWDRT,   0xb8, 6);
 281     SBIT(PBO,     0xb8, 5);
 282     SBIT(PS,      0xb8, 4);
 283     SBIT(PSR,     0xb8, 4);
 284     SBIT(PT1,     0xb8, 3);
 285     SBIT(PX1,     0xb8, 2);
 286     SBIT(PT0,     0xb8, 1);
 287     SBIT(PX0,     0xb8, 0);
 288 SFR(IP0H,    0xb7); // Interrupt priority 0 high
 289     #define PWDRTH   0x40
 290     #define PBOH     0x20
 291     #define PSH      0x10
 292     #define PSRH     0x10
 293     #define PT1H     0x08
 294     #define PX1H     0x04
 295     #define PT0H     0x02
 296     #define PX0H     0x01
 297 SFR(IP1,     0xf8); // Interrupt priority 1
 298     SBIT(IP1_7,   0xf8, 7);
 299     SBIT(IP1_6,   0xf8, 6);
 300     SBIT(IP1_5,   0xf8, 5);
 301     SBIT(IP1_4,   0xf8, 4);
 302     SBIT(IP1_3,   0xf8, 3);
 303     SBIT(IP1_2,   0xf8, 2);
 304     SBIT(IP1_1,   0xf8, 1);
 305     SBIT(IP1_0,   0xf8, 0);
 306     SBIT(PADEE,   0xf8, 7);
 307     SBIT(PST,     0xf8, 6);
 308     SBIT(PCCU,    0xf8, 4);
 309     SBIT(PSPI,    0xf8, 3);
 310     SBIT(PC,      0xf8, 2);
 311     SBIT(PKBI,    0xf8, 1);
 312     SBIT(PI2C,    0xf8, 0);
 313 SFR(IP1H,    0xf7); // Interrupt priority 1 high
 314     #define PAEEH    0x80
 315     #define PSTH     0x40
 316     #define PCCUH    0x10
 317     #define PSPIH    0x08
 318     #define PCH      0x04
 319     #define PKBIH    0x02
 320     #define PI2CH    0x01
 321 SFR(KBCON,   0x94); // Keypad control register
 322     #define PATN     0x02
 323     #define _SEL     0x01
 324 SFR(KBMASK,  0x86); // Keypad interrupt mask register
 325 SFR(KBPATN,  0x93); // Keypad pattern register
 326 SFR(OCRAH,   0xef); // Output compare A register high
 327 SFR(OCRAL,   0xee); // Output compare A register low
 328 SFR(OCRBH,   0xfb); // Output compare B register high
 329 SFR(OCRBL,   0xfa); // Output compare B register low
 330 SFR(OCRCH,   0xfd); // Output compare C register high
 331 SFR(OCRCL,   0xfc); // Output compare C register low
 332 SFR(OCRDH,   0xff); // Output compare D register high
 333 SFR(OCRDL,   0xfe); // Output compare D register low
 334 SFR(P0,      0x80); // Port 0
 335     SBIT(P0_7,    0x80, 7);
 336     SBIT(P0_6,    0x80, 6);
 337     SBIT(P0_5,    0x80, 5);
 338     SBIT(P0_4,    0x80, 4);
 339     SBIT(P0_3,    0x80, 3);
 340     SBIT(P0_2,    0x80, 2);
 341     SBIT(P0_1,    0x80, 1);
 342     SBIT(P0_0,    0x80, 0);
 343     SBIT(T1,      0x80, 7);
 344     SBIT(KB7,     0x80, 7);
 345     SBIT(CMP_1,   0x80, 6);
 346     SBIT(KB6,     0x80, 6);
 347     SBIT(CMPREF,  0x80, 5);
 348     SBIT(KB5,     0x80, 5);
 349     SBIT(CIN1A,   0x80, 4);
 350     SBIT(KB4,     0x80, 4);
 351     SBIT(CIN1B,   0x80, 3);
 352     SBIT(KB3,     0x80, 3);
 353     SBIT(CIN2A,   0x80, 2);
 354     SBIT(KB2,     0x80, 2);
 355     SBIT(CIN2B,   0x80, 1);
 356     SBIT(KB1,     0x80, 1);
 357     SBIT(CMP_2,   0x80, 0);
 358     SBIT(KB0,     0x80, 0);
 359 SFR(P1,      0x90); // Port 1
 360     SBIT(P1_7,    0x90, 7);
 361     SBIT(P1_6,    0x90, 6);
 362     SBIT(P1_5,    0x90, 5);
 363     SBIT(P1_4,    0x90, 4);
 364     SBIT(P1_3,    0x90, 3);
 365     SBIT(P1_2,    0x90, 2);
 366     SBIT(P1_1,    0x90, 1);
 367     SBIT(P1_0,    0x90, 0);
 368     SBIT(OCC,     0x90, 7);
 369     SBIT(OCB,     0x90, 6);
 370     SBIT(RST,     0x90, 5);
 371     SBIT(INT1,    0x90, 4);
 372     SBIT(INT0,    0x90, 3);
 373     SBIT(SDA,     0x90, 3);
 374     SBIT(T0,      0x90, 2);
 375     SBIT(SCL,     0x90, 2);
 376     SBIT(RXD,     0x90, 1);
 377     SBIT(TXD,     0x90, 0);
 378 SFR(P2,      0xa0); // Port 2
 379     SBIT(P2_7,    0xa0, 7);
 380     SBIT(P2_6,    0xa0, 6);
 381     SBIT(P2_5,    0xa0, 5);
 382     SBIT(P2_4,    0xa0, 4);
 383     SBIT(P2_3,    0xa0, 3);
 384     SBIT(P2_2,    0xa0, 2);
 385     SBIT(P2_1,    0xa0, 1);
 386     SBIT(P2_0,    0xa0, 0);
 387     SBIT(ICA,     0xa0, 7);
 388     SBIT(OCA,     0xa0, 6);
 389     SBIT(SPICLK,  0xa0, 5);
 390     SBIT(SS,      0xa0, 4);
 391     SBIT(MISO,    0xa0, 3);
 392     SBIT(MOSI,    0xa0, 2);
 393     SBIT(OCD,     0xa0, 1);
 394     SBIT(ICB,     0xa0, 0);
 395 SFR(P3,      0xb0); // Port 3
 396     SBIT(P3_7,    0xb0, 7);
 397     SBIT(P3_6,    0xb0, 6);
 398     SBIT(P3_5,    0xb0, 5);
 399     SBIT(P3_4,    0xb0, 4);
 400     SBIT(P3_3,    0xb0, 3);
 401     SBIT(P3_2,    0xb0, 2);
 402     SBIT(P3_1,    0xb0, 1);
 403     SBIT(P3_0,    0xb0, 0);
 404     SBIT(XTAL1,   0xb0, 1);
 405     SBIT(XTAL2,   0xb0, 0);
 406 SFR(P0M1,    0x84); // Port 0 output mode 1
 407     #define P0M1_7   0x80
 408     #define P0M1_6   0x40
 409     #define P0M1_5   0x20
 410     #define P0M1_4   0x10
 411     #define P0M1_3   0x08
 412     #define P0M1_2   0x04
 413     #define P0M1_1   0x02
 414     #define P0M1_0   0x01
 415 SFR(P0M2,    0x85); // Port 0 output mode 2
 416     #define P0M2_7   0x80
 417     #define P0M2_6   0x40
 418     #define P0M2_5   0x20
 419     #define P0M2_4   0x10
 420     #define P0M2_3   0x08
 421     #define P0M2_2   0x04
 422     #define P0M2_1   0x02
 423     #define P0M2_0   0x01
 424 SFR(P1M1,    0x91); // Port 1 output mode 1
 425     #define P1M1_7   0x80
 426     #define P1M1_6   0x40
 427     #define P1M1_4   0x10
 428     #define P1M1_3   0x08
 429     #define P1M1_2   0x04
 430     #define P1M1_1   0x02
 431     #define P1M1_0   0x01
 432 SFR(P1M2,    0x92); // Port 1 output mode 2
 433     #define P1M2_7   0x80
 434     #define P1M2_6   0x40
 435     #define P1M2_4   0x10
 436     #define P1M2_3   0x08
 437     #define P1M2_2   0x04
 438     #define P1M2_1   0x02
 439     #define P1M2_0   0x01
 440 SFR(P2M1,    0xa4); // Port 2 output mode 1
 441     #define P2M1_7   0x80
 442     #define P2M1_6   0x40
 443     #define P2M1_5   0x20
 444     #define P2M1_4   0x10
 445     #define P2M1_3   0x08
 446     #define P2M1_2   0x04
 447     #define P2M1_1   0x02
 448     #define P2M1_0   0x01
 449 SFR(P2M2,    0xa5); // Port 2 output mode 2
 450     #define P2M2_7   0x80
 451     #define P2M2_6   0x40
 452     #define P2M2_5   0x20
 453     #define P2M2_4   0x10
 454     #define P2M2_3   0x08
 455     #define P2M2_2   0x04
 456     #define P2M2_1   0x02
 457     #define P2M2_0   0x01
 458 SFR(P3M1,    0xb1); // Port 3 output mode 1
 459     #define P3M1_1   0x02
 460     #define P3M1_0   0x01
 461 SFR(P3M2,    0xb2); // Port 3 output mode 2
 462     #define P3M2_1   0x02
 463     #define P3M2_0   0x01
 464 SFR(PCON,    0x87); // Power control register
 465     #define SMOD1    0x80
 466     #define SMOD0    0x40
 467     #define BOI      0x10
 468     #define GF1      0x08
 469     #define GF0      0x04
 470     #define PMOD1    0x02
 471     #define PMOD0    0x01
 472 SFR(PCONA,   0xb5); // Power control register A
 473     #define RTCPD    0x80
 474     #define DEEPD    0x40
 475     #define VCPD     0x20
 476     #define ADPD     0x10
 477     #define I2PD     0x08
 478     #define SPPD     0x04
 479     #define SPD      0x02
 480     #define CCUPD    0x01
 481 SFR(PSW,     0xd0); // Program status word
 482     SBIT(PSW_7,   0xd0, 7);
 483     SBIT(PSW_6,   0xd0, 6);
 484     SBIT(PSW_5,   0xd0, 5);
 485     SBIT(PSW_4,   0xd0, 4);
 486     SBIT(PSW_3,   0xd0, 3);
 487     SBIT(PSW_2,   0xd0, 2);
 488     SBIT(PSW_1,   0xd0, 1);
 489     SBIT(PSW_0,   0xd0, 0);
 490     SBIT(CY,      0xd0, 7);
 491     SBIT(AC,      0xd0, 6);
 492     SBIT(F0,      0xd0, 5);
 493     SBIT(RS1,     0xd0, 4);
 494     SBIT(RS0,     0xd0, 3);
 495     SBIT(OV,      0xd0, 2);
 496     SBIT(F1,      0xd0, 1);
 497     SBIT(P,       0xd0, 0);
 498 SFR(PT0AD,   0xf6); // Port 0 digital input disable
 499     #define PT0AD_5  0x20
 500     #define PT0AD_4  0x10
 501     #define PT0AD_3  0x08
 502     #define PT0AD_2  0x04
 503     #define PT0AD_1  0x02
 504 SFR(RSTSRC,  0xdf); // Reset source register
 505     #define BOIF     0x40
 506     #define BOF      0x20
 507     #define POF      0x10
 508     #define R_BK     0x08
 509     #define R_WD     0x04
 510     #define R_SF     0x02
 511     #define R_EX     0x01
 512 SFR(RTCCON,  0xd1); // RTC control
 513     #define RTCF     0x80
 514     #define RTCS1    0x40
 515     #define RTCS0    0x20
 516     #define ERTC     0x02
 517     #define RTCEN    0x01
 518 SFR(RTCH,    0xd2); // RTC register high
 519 SFR(RTCL,    0xd3); // RTC register low
 520 SFR(SADDR,   0xa9); // Serial port address register
 521 SFR(SADEN,   0xb9); // Serial port address enable
 522 SFR(SBUF,    0x99); // Serial Port data buffer register
 523 SFR(SCON,    0x98); // Serial port control
 524     SBIT(SCON_7,  0x98, 7);
 525     SBIT(SCON_6,  0x98, 6);
 526     SBIT(SCON_5,  0x98, 5);
 527     SBIT(SCON_4,  0x98, 4);
 528     SBIT(SCON_3,  0x98, 3);
 529     SBIT(SCON_2,  0x98, 2);
 530     SBIT(SCON_1,  0x98, 1);
 531     SBIT(SCON_0,  0x98, 0);
 532     SBIT(SM0,     0x98, 7);
 533     SBIT(FE,      0x98, 7);
 534     SBIT(SM1,     0x98, 6);
 535     SBIT(SM2,     0x98, 5);
 536     SBIT(REN,     0x98, 4);
 537     SBIT(TB8,     0x98, 3);
 538     SBIT(RB8,     0x98, 2);
 539     SBIT(TI,      0x98, 1);
 540     SBIT(RI,      0x98, 0);
 541 SFR(SSTAT,   0xba); // Serial port extended status register
 542     #define DBMOD    0x80
 543     #define INTLO    0x40
 544     #define CIDIS    0x20
 545     #define DBISEL   0x10
 546     #define FE       0x08
 547     #define BR       0x04
 548     #define OE       0x02
 549     #define STINT    0x01
 550 SFR(SP,      0x81); // Stack pointer
 551 SFR(SPCTL,   0xe2); // SPI control register
 552     #define SSIG     0x80
 553     #define SPEN     0x40
 554     #define DORD     0x20
 555     #define MSTR     0x10
 556     #define CPOL     0x08
 557     #define CPHA     0x04
 558     #define SPR1     0x02
 559     #define SPR0     0x01
 560 SFR(SPSTAT,  0xe1); // SPI status register
 561     #define SPIF     0x80
 562     #define WCOL     0x40
 563 SFR(SPDAT,   0xe3); // SPI data register
 564 SFR(TAMOD,   0x8f); // Timer 0 and 1 auxiliary mode
 565     #define T1M2     0x10
 566     #define T0M2     0x01
 567 SFR(TCON,    0x88); // Timer 0 and 1 control
 568     SBIT(TCON_7,  0x88, 7);
 569     SBIT(TCON_6,  0x88, 6);
 570     SBIT(TCON_5,  0x88, 5);
 571     SBIT(TCON_4,  0x88, 4);
 572     SBIT(TCON_3,  0x88, 3);
 573     SBIT(TCON_2,  0x88, 2);
 574     SBIT(TCON_1,  0x88, 1);
 575     SBIT(TCON_0,  0x88, 0);
 576     SBIT(TF1,     0x88, 7);
 577     SBIT(TR1,     0x88, 6);
 578     SBIT(TF0,     0x88, 5);
 579     SBIT(TR0,     0x88, 4);
 580     SBIT(IE1,     0x88, 3);
 581     SBIT(IT1,     0x88, 2);
 582     SBIT(IE0,     0x88, 1);
 583     SBIT(IT0,     0x88, 0);
 584 SFR(TCR20,   0xc8); // CCU control register 0
 585     SBIT(TCR20_7, 0xc8, 7);
 586     SBIT(TCR20_6, 0xc8, 6);
 587     SBIT(TCR20_5, 0xc8, 5);
 588     SBIT(TCR20_4, 0xc8, 4);
 589     SBIT(TCR20_3, 0xc8, 3);
 590     SBIT(TCR20_2, 0xc8, 2);
 591     SBIT(TCR20_1, 0xc8, 1);
 592     SBIT(TCR20_0, 0xc8, 0);
 593     SBIT(PLEEN,   0xc8, 7);
 594     SBIT(HLTRN,   0xc8, 6);
 595     SBIT(HLTEN,   0xc8, 5);
 596     SBIT(ALTCD,   0xc8, 4);
 597     SBIT(ALTAB,   0xc8, 3);
 598     SBIT(TDIR2,   0xc8, 2);
 599     SBIT(TMOD21,  0xc8, 1);
 600     SBIT(TMOD20,  0xc8, 0);
 601 SFR(TCR21,   0xf9); // CCU control register 1
 602     #define TCOU2    0x80
 603     #define PLLDV_3  0x08
 604     #define PLLDV_2  0x04
 605     #define PLLDV_1  0x02
 606     #define PLLDV_0  0x01
 607 SFR(TH0,     0x8c); // Timer 0 high
 608 SFR(TH1,     0x8d); // Timer 1 high
 609 SFR(TH2,     0xcd); // CCU timer high
 610 SFR(TICR2,   0xc9); // CCU interrupt control register
 611     #define TOIE2    0x80
 612     #define TOCIE2D  0x40
 613     #define TOCIE2C  0x20
 614     #define TOCIE2B  0x10
 615     #define TOCIE2A  0x08
 616     #define TICIE2B  0x02
 617     #define TICIE2A  0x01
 618 SFR(TIFR2,   0xe9); // CCU interrupt flag register
 619     #define TOIF2    0x80
 620     #define TOCF2D   0x40
 621     #define TOCF2C   0x20
 622     #define TOCF2B   0x10
 623     #define TOCF2A   0x08
 624     #define TICF2B   0x02
 625     #define TICF2A   0x01
 626 SFR(TISE2,   0xde); // CCU interrupt status encode register
 627     #define ENCINT_2 0x04
 628     #define ENCINT_1 0x02
 629     #define ENCINT_0 0x01
 630 SFR(TL0,     0x8a); // Timer 0 low
 631 SFR(TL1,     0x8b); // Timer 1 low
 632 SFR(TL2,     0xcc); // CCU timer low
 633 SFR(TMOD,    0x89); // Timer 0 and 1 mode
 634     #define T1GATE   0x80
 635     #define T1C_T    0x40
 636     #define T1M1     0x20
 637     #define T1M0     0x10
 638     #define T0GATE   0x08
 639     #define T0C_T    0x04
 640     #define T0M1     0x02
 641     #define T0M0     0x01
 642 SFR(TOR2H,   0xcf); // CCU reload register high
 643 SFR(TOR2L,   0xce); // CCU reload register low
 644 SFR(TPCR2H,  0xcb); // Prescaler control register high
 645     #define TPCR2H_1 0x02
 646     #define TPCR2H_0 0x01
 647 SFR(TPCR2L,  0xca); // Prescaler control register low
 648     #define TPCR2L_7 0x80
 649     #define TPCR2L_6 0x40
 650     #define TPCR2L_5 0x20
 651     #define TPCR2L_4 0x10
 652     #define TPCR2L_3 0x08
 653     #define TPCR2L_2 0x04
 654     #define TPCR2L_1 0x02
 655     #define TPCR2L_0 0x01
 656 SFR(TRIM,    0x96); // Internal oscillator trim register
 657     #define RCCLK    0x80
 658     #define ENCLK    0x40
 659     #define TRIM_5   0x20
 660     #define TRIM_4   0x10
 661     #define TRIM_3   0x08
 662     #define TRIM_2   0x04
 663     #define TRIM_1   0x02
 664     #define TRIM_0   0x01
 665 SFR(WDCON,   0xa7); // Watchdog control register
 666     #define PRE2     0x80
 667     #define PRE1     0x40
 668     #define PRE0     0x20
 669     #define WDRUN    0x04
 670     #define WDTOF    0x02
 671     #define WDCLK    0x01
 672 SFR(WDL,     0xc1); // Watchdog load
 673 SFR(WFEED1,  0xc2); // Watchdog feed 1
 674 SFR(WFEED2,  0xc3); // Watchdog feed 2
 675 SFRX(BODCFG,  0xffc8); // BOD configuration register
 676     #define BOICFG1  0x02
 677     #define BOICFG0  0x01
 678 SFRX(CLKCON,  0xffde); // CLOCK Control register
 679     #define CLKOK    0x80
 680     #define XTALWD   0x10
 681     #define CLKDBL   0x08
 682     #define FOSC2    0x04
 683     #define FOSC1    0x02
 684     #define FOSC0    0x01
 685 SFRX(PGACON1, 0xffe1); // PGA1 control register
 686     #define ENPGA1   0x80
 687     #define PGASEL1_1 0x40
 688     #define PGASEL1_0 0x20
 689     #define PGATRIM_1 0x10
 690     #define PGAG11   0x02
 691     #define PGAG10   0x01
 692 SFRX(PGACON1B, 0xffe4); // PGA1 control register B
 693     #define PGAENO   0x01
 694     #define FF1      0x01
 695 SFRX(PGA1TRIM8X16X, 0xffe3); // PGA1 trim register
 696     #define PGA1_16XTRIM3 0x80
 697     #define PGA1_16XTRIM2 0x40
 698     #define PGA1_16XTRIM1 0x20
 699     #define PGA1_16XTRIM0 0x10
 700     #define PGA1_8XTRIM3 0x08
 701     #define PGA1_8XTRIM2 0x04
 702     #define PGA1_8XTRIM1 0x02
 703     #define PGA1_8XTRIM0 0x01
 704 SFRX(PGA1TRIM2X4X, 0xffe2); // PGA1 trim register
 705     #define PGA1_4XTRIM3 0x80
 706     #define PGA1_4XTRIM2 0x40
 707     #define PGA1_4XTRIM1 0x20
 708     #define PGA1_4XTRIM0 0x10
 709     #define PGA1_2XTRIM3 0x08
 710     #define PGA1_2XTRIM2 0x04
 711     #define PGA1_2XTRIM1 0x02
 712     #define PGA1_2XTRIM0 0x01
 713 SFRX(PGACON0, 0xffca); // PGA0 control register
 714     #define ENPGA0   0x80
 715     #define PGASEL0_1 0x40
 716     #define PGASEL0_0 0x20
 717     #define PGATRIM_0 0x10
 718     #define TSEL1    0x08
 719     #define TSEL0    0x04
 720     #define PGAG01   0x02
 721     #define PGAG00   0x01
 722 SFRX(PGACON0B, 0xffce); // PGA0 control register B
 723     #define PGAENO   0x01
 724     #define FF0      0x01
 725 SFRX(PGA0TRIM8X16X, 0xffcd); // PGA0 trim register
 726     #define PGA0_16XTRIM3 0x80
 727     #define PGA0_16XTRIM2 0x40
 728     #define PGA0_16XTRIM1 0x20
 729     #define PGA0_16XTRIM0 0x10
 730     #define PGA0_8XTRIM3 0x08
 731     #define PGA0_8XTRIM2 0x04
 732     #define PGA0_8XTRIM1 0x02
 733     #define PGA0_8XTRIM0 0x01
 734 SFRX(PGA0TRIM2X4X, 0xffcc); // PGA0 trim register
 735     #define PGA0_4XTRIM3 0x80
 736     #define PGA0_4XTRIM2 0x40
 737     #define PGA0_4XTRIM1 0x20
 738     #define PGA0_4XTRIM0 0x10
 739     #define PGA0_2XTRIM3 0x08
 740     #define PGA0_2XTRIM2 0x04
 741     #define PGA0_2XTRIM1 0x02
 742     #define PGA0_2XTRIM0 0x01
 743 SFRX(RTCDATH, 0xffbf); // Real-time clock data register high
 744 SFRX(RTCDATL, 0xffbe); // Real-time clock data register low
 745 #endif /*REG_P89LPC9351_H*/