sdcc/device/include/mcs51/p89lpc935_6.h

   1 /*-------------------------------------------------------------------------
   2    p89lpc935_6.h - This header allows to use the microcontrolers NXP
   3    (formerly Philips) p89lpc935, 936.
   4
   5    Copyright (C) 2008, Gudjon I. Gudjonsson <gudjon AT gudjon.org>
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 /*-------------------------------------------------------------------------
  31  The registered are ordered in the same way as in the NXP data sheet:
  32  http://www.standardics.nxp.com/products/lpc900/datasheet/p89lpc933.p89lpc934.p89lpc935.p89lpc936.pdf
  33 -------------------------------------------------------------------------*/
  34
  35 #ifndef __P89LPC935_6_H__
  36 #define __P89LPC935_6_H__
  37 #include <compiler.h>
  38
  39 /*BYTE Registers*/
  40 SFR(ACC, 0xE0); // Accumulator
  41         SBIT(ACC_7, 0xE0, 7);
  42         SBIT(ACC_6, 0xE0, 6);
  43         SBIT(ACC_5, 0xE0, 5);
  44         SBIT(ACC_4, 0xE0, 4);
  45         SBIT(ACC_3, 0xE0, 3);
  46         SBIT(ACC_2, 0xE0, 2);
  47         SBIT(ACC_1, 0xE0, 1);
  48         SBIT(ACC_0, 0xE0, 0);
  49 SFR(ADCON0, 0x8E); // A/D control register 0
  50         #define  ENBI0    0x80
  51         #define  ENADCI0  0x40
  52         #define  TMM0     0x20
  53         #define  EDGE0    0x10
  54         #define  ADCI0    0x08
  55         #define  ENADC0   0x04
  56         #define  ADCS01   0x02
  57         #define  ADCS00   0x01
  58 SFR(ADCON1, 0x97); // A/D control register 1
  59         #define  ENBI1    0x80
  60         #define  ENADCI1  0x40
  61         #define  TMM1     0x20
  62         #define  EDGE1    0x10
  63         #define  ADCI1    0x08
  64         #define  ENADC1   0x04
  65         #define  ADCS11   0x02
  66         #define  ADCS10   0x01
  67 SFR(ADINS, 0xA3); // A/D input select
  68         #define  ADI13    0x80
  69         #define  ADI12    0x40
  70         #define  ADI11    0x20
  71         #define  ADI10    0x10
  72         #define  ADI03    0x08
  73         #define  ADI02    0x04
  74         #define  ADI01    0x02
  75         #define  ADI00    0x01
  76 SFR(ADMODA, 0xC0); // A/D mode register A
  77         SBIT(BNDI1,  0xC0, 7);
  78         SBIT(BURST1, 0xC0, 6);
  79         SBIT(SCC1,   0xC0, 5);
  80         SBIT(SCAN1,  0xC0, 4);
  81         SBIT(BNDI0,  0xC0, 3);
  82         SBIT(BURST0, 0xC0, 2);
  83         SBIT(SCC0,   0xC0, 1);
  84         SBIT(SCAN0,  0xC0, 0);
  85 SFR(ADMODB, 0xA1); // A/D mode register B
  86         #define  CLK2     0x80
  87         #define  CLK1     0x40
  88         #define  CLK0     0x20
  89         #define  ENDAC1   0x08
  90         #define  ENDAC0   0x04
  91         #define  BSA1     0x02
  92         #define  BSA0     0x01
  93 SFR(AD0BH,   0xBB); // A/D_0 boundary high register
  94 SFR(AD0BL,   0xA6); // A/D_0 boundary low register
  95 SFR(AD0DAT0, 0xC5); // A/D_0 data register 0
  96 SFR(AD0DAT1, 0xC6); // A/D_0 data register 1
  97 SFR(AD0DAT2, 0xC7); // A/D_0 data register 2
  98 SFR(AD0DAT3, 0xF4); // A/D_0 data register 3
  99 SFR(AD1BH,   0xC4); // A/D_1 boundary high register
 100 SFR(AD1BL,   0xBC); // A/D_1 boundary low register
 101 SFR(AD1DAT0, 0xD5); // A/D_1 data register 0
 102 SFR(AD1DAT1, 0xD6); // A/D_1 data register 1
 103 SFR(AD1DAT2, 0xD7); // A/D_1 data register 2
 104 SFR(AD1DAT3, 0xF5); // A/D_1 data register 3
 105 SFR(AUXR1,   0xA2); // Auxilary function register
 106         #define  CLKLP    0x80
 107         #define  EBRR     0x40
 108         #define  ENT1     0x20
 109         #define  ENT0     0x10
 110         #define  SRST     0x08
 111         #define  DPS      0x01 // Bit 2 is always 0
 112 SFR(B, 0xF0); // B register
 113         SBIT(B7, 0xF0, 7);
 114         SBIT(B6, 0xF0, 6);
 115         SBIT(B5, 0xF0, 5);
 116         SBIT(B4, 0xF0, 4);
 117         SBIT(B3, 0xF0, 3);
 118         SBIT(B2, 0xF0, 2);
 119         SBIT(B1, 0xF0, 1);
 120         SBIT(B0, 0xF0, 0);
 121 SFR(BRGR0,  0xBE); // Baud rate generator rate low
 122 SFR(BRGR1,  0xBF); // Baud rate generator rate high
 123 SFR(BRGCON, 0xBD); // Baud rate generator control
 124         #define  SBRGS    0x02
 125         #define  BRGEN    0x01
 126 SFR(CCCRA,  0xEA); // Capture compare A control register
 127         #define  ICECA2   0x80
 128         #define  ICECA1   0x40
 129         #define  ICECA0   0x20
 130         #define  ICESA    0x10
 131         #define  ICNFA    0x08
 132         #define  FCOA     0x04
 133         #define  OCMA1    0x02
 134         #define  OCMA0    0x01
 135 SFR(CCCRB,  0xEB); // Capture compare B control register
 136         #define  ICECB2   0x80
 137         #define  ICECB1   0x40
 138         #define  ICECB0   0x20
 139         #define  ICESB    0x10
 140         #define  ICNFB    0x08
 141         #define  FCOB     0x04
 142         #define  OCMB1    0x02
 143         #define  OCMB0    0x01
 144 SFR(CCCRC,  0xEC); // Capture compare C control register
 145         #define  FCOC     0x04
 146         #define  OCMC1    0x02
 147         #define  OCMC0    0x01
 148 SFR(CCCRD,  0xED); // Capture compare D control register
 149         #define  FCOD     0x04
 150         #define  OCMD1    0x02
 151         #define  OCMD0    0x01
 152 SFR(CMP1,   0xAC); // Comparator 1 control register
 153         #define  CE1      0x20
 154         #define  CP1      0x10
 155         #define  CN1      0x08
 156         #define  OE1      0x04
 157         #define  CO1      0x02
 158         #define  CMF1     0x01
 159 SFR(CMP2,   0xAD); // Comparator 2 control register
 160         #define  CE2      0x20
 161         #define  CP2      0x10
 162         #define  CN2      0x08
 163         #define  OE2      0x04
 164         #define  CO2      0x02
 165         #define  CMF2     0x01
 166 SFR(DEECON, 0xF1); // Data EEPROM control register
 167         #define  EEIF     0x80
 168         #define  HVERR    0x40
 169         #define  ECTL1    0x20
 170         #define  ECTL0    0x10
 171         #define  EADR8    0x01
 172 SFR(DEEDAT, 0xF2); // Data EEPROM data register
 173 SFR(DEEADR, 0xF3); // Data EEPROM address register
 174 SFR(DIVM,   0x95); // CPU clock divide-by-M control
 175 SFR(DPH,    0x83); // Data Pointer High
 176 SFR(DPL,    0x82); // Data Pointer Low
 177 SFR(FMADRH, 0xE7); // Program flash address high
 178 SFR(FMADRL, 0xE6); // Program flash address low
 179 SFR(FMCON,  0xE4);
 180         // Program flash control (Read)
 181         #define  BUSY     0x80
 182         #define  HVA      0x08
 183         #define  HVE      0x04
 184         #define  SV       0x02
 185         #define  OI       0x01
 186         // Program flash control (Write)
 187         #define  FMCMD_7  0x80
 188         #define  FMCMD_6  0x40
 189         #define  FMCMD_5  0x20
 190         #define  FMCMD_4  0x10
 191         #define  FMCMD_3  0x08
 192         #define  FMCMD_2  0x04
 193         #define  FMCMD_1  0x02
 194         #define  FMCMD_0  0x01
 195 SFR(FMDATA,  0xE5); // Program flash data
 196 SFR(I2ADR,   0xDB); // I2C slave address register
 197         #define I2ADR_6  0x80
 198         #define I2ADR_5  0x40
 199         #define I2ADR_4  0x20
 200         #define I2ADR_3  0x10
 201         #define I2ADR_2  0x08
 202         #define I2ADR_1  0x04
 203         #define I2ADR_0  0x02
 204         #define GC       0x01
 205 SFR(I2CON,  0xD8); // I2C control register
 206         SBIT(I2EN,  0xD8, 6);
 207         SBIT(STA,   0xD8, 5);
 208         SBIT(STO,   0xD8, 4);
 209         SBIT(SI,    0xD8, 3);
 210         SBIT(AA,    0xD8, 2);
 211         SBIT(CRSEL, 0xD8, 0);
 212 SFR(I2DAT,  0xDA); // I2C data register
 213 SFR(I2SCLH, 0xDD); // I2C serial clock generator/SCL duty cycle register high
 214 SFR(I2SCLL, 0xDC); // I2C serial clock generator/SCL duty cycle register low
 215 SFR(I2STAT, 0xD9); // I2C status register
 216         #define STA_4   0x80
 217         #define STA_3   0x40
 218         #define STA_2   0x20
 219         #define STA_1   0x10
 220         #define STA_0   0x08    // Only write 0 to the lowest three bits
 221 SFR(ICRAH,  0xAB); // Input capture A register high
 222 SFR(ICRAL,  0xAA); // Input capture A register low
 223 SFR(ICRBH,  0xAF); // Input capture B register high
 224 SFR(ICRBL,  0xAE); // Input capture B register low
 225 SFR(IEN0,   0xA8); // Interrupt Enable 0
 226         SBIT(EA,     0xA8, 7);
 227         SBIT(EWDRT,  0xA8, 6);
 228         SBIT(EBO,    0xA8, 5);
 229         SBIT(ES_ESR, 0xA8, 4);
 230         SBIT(ET1,    0xA8, 3);
 231         SBIT(EX1,    0xA8, 2);
 232         SBIT(ET0,    0xA8, 1);
 233         SBIT(EX0,    0xA8, 0);
 234 SFR(IEN1,  0xE8); // Interrupt Enable 1
 235         SBIT(EADEE,  0xE8, 7);
 236         SBIT(EST,    0xE8, 6);
 237         SBIT(ECCU,   0xE8, 4);
 238         SBIT(ESPI,   0xE8, 3);
 239         SBIT(EC,     0xE8, 2);
 240         SBIT(EKBI,   0xE8, 1);
 241         SBIT(EI2C,   0xE8, 0);
 242 SFR(IP0, 0xB8); // Interrupt Priority 0
 243         SBIT(PWDRT,  0xB8, 6);
 244         SBIT(PBO,    0xB8, 5);
 245         SBIT(PS_PSR, 0xB8, 4);
 246         SBIT(PT1,    0xB8, 3);
 247         SBIT(PX1,    0xB8, 2);
 248         SBIT(PT0,    0xB8, 1);
 249         SBIT(PX0,    0xB8, 0);
 250 SFR(IP0H, 0xB7); // Interrupt Priority 0 high
 251         #define PWDRTH    0x40
 252         #define PBOH      0x20
 253         #define PSH_PSRH  0x10
 254         #define PT1H      0x08
 255         #define PX1H      0x04
 256         #define PT0H      0x02
 257         #define PX0H      0x01
 258 SFR(IP1,  0xF8); // Interrupt Priority 1
 259         SBIT(PADEE, 0xF8, 7);
 260         SBIT(PST,   0xF8, 6);
 261         SBIT(PCCU,  0xF8, 4);
 262         SBIT(PSPI,  0xF8, 3);
 263         SBIT(PC,    0xF8, 2);
 264         SBIT(PKBI,  0xF8, 1);
 265         SBIT(PI2C,  0xF8, 0);
 266 SFR(IP1H, 0xF7); // Interrupt Priority 1 High
 267         #define PAEEH  0x80
 268         #define PSTH   0x40
 269         #define PCCUH  0x10
 270         #define PSPIH  0x08
 271         #define PCH    0x04
 272         #define PKBIH  0x02
 273         #define PI2CH  0x01
 274 SFR(KBCON, 0x94); // Keypad control register
 275         #define PATN_SEL 0x02
 276         #define KBIF     0x01
 277 SFR(KBMASK, 0x86); // Keypad interrupt mask register
 278 SFR(KBPATN, 0x93); // Keypad pattern register
 279 SFR(OCRAH,  0xEF); // Output compare A register high
 280 SFR(OCRAL,  0xEE); // Output compare A register low
 281 SFR(OCRBH,  0xFB); // Output compare B register high
 282 SFR(OCRBL,  0xFA); // Output compare B register low
 283 SFR(OCRCH,  0xFD); // Output compare C register high
 284 SFR(OCRCL,  0xFC); // Output compare C register low
 285 SFR(OCRDH,  0xFF); // Output compare D register high
 286 SFR(OCRDL,  0xFE); // Output compare D register low
 287 SFR(P0, 0x80); // Port 0
 288         SBIT(P0_7,   0x80, 7);
 289         SBIT(T1,     0x80, 7);
 290         SBIT(KB7,    0x80, 7);
 291         SBIT(P0_6,   0x80, 6);
 292         SBIT(CMP_1,  0x80, 6); // Renamed, not to conflict with the CMP1 register
 293         SBIT(KB6,    0x80, 6);
 294         SBIT(P0_5,   0x80, 5);
 295         SBIT(CMPREF, 0x80, 5);
 296         SBIT(KB5,    0x80, 5);
 297         SBIT(P0_4,   0x80, 4);
 298         SBIT(CIN1A,  0x80, 4);
 299         SBIT(KB4,    0x80, 4);
 300         SBIT(P0_3,   0x80, 3);
 301         SBIT(CIN1B,  0x80, 3);
 302         SBIT(KB3,    0x80, 3);
 303         SBIT(P0_2,   0x80, 2);
 304         SBIT(CIN2A,  0x80, 2);
 305         SBIT(KB2,    0x80, 2);
 306         SBIT(P0_1,   0x80, 1);
 307         SBIT(CIN2B,  0x80, 1);
 308         SBIT(KB1,    0x80, 1);
 309         SBIT(P0_0,   0x80, 0);
 310         SBIT(CMP_2,  0x80, 0); // Renamed, not to conflict with the CMP2 register
 311         SBIT(KB0,    0x80, 0);
 312 SFR(P1, 0x90); // Port 1
 313         SBIT(P1_7,   0x90, 7);
 314         SBIT(OCC,    0x90, 7);
 315         SBIT(P1_6,   0x90, 6);
 316         SBIT(OCB,    0x90, 6);
 317         SBIT(P1_5,   0x90, 5);
 318         SBIT(RST,    0x90, 5);
 319         SBIT(P1_4,   0x90, 4);
 320         SBIT(INT1,   0x90, 4);
 321         SBIT(P1_3,   0x90, 3);
 322         SBIT(INT0,   0x90, 3);
 323         SBIT(SDA,    0x90, 3);
 324         SBIT(P1_2,   0x90, 2);
 325         SBIT(T0,     0x90, 2);
 326         SBIT(SCL,    0x90, 2);
 327         SBIT(P1_1,   0x90, 1);
 328         SBIT(RXD,    0x90, 1);
 329         SBIT(P1_0,   0x90, 0);
 330         SBIT(TXD,    0x90, 0);
 331 SFR(P2, 0xA0); // Port 2
 332         SBIT(P2_7,   0xA0, 7);
 333         SBIT(ICA,    0xA0, 7);
 334         SBIT(P2_6,   0xA0, 6);
 335         SBIT(OCA,    0xA0, 6);
 336         SBIT(P2_5,   0xA0, 5);
 337         SBIT(SPICLK, 0xA0, 5);
 338         SBIT(P2_4,   0xA0, 4);
 339         SBIT(SS,     0xA0, 4);
 340         SBIT(P2_3,   0xA0, 3);
 341         SBIT(MISO,   0xA0, 3);
 342         SBIT(P2_2,   0xA0, 2);
 343         SBIT(MOSI,   0xA0, 2);
 344         SBIT(P2_1,   0xA0, 1);
 345         SBIT(OCD,    0xA0, 1);
 346         SBIT(P2_0,   0xA0, 0);
 347         SBIT(ICB,    0xA0, 0);
 348 SFR(P3, 0xB0); // Port 3
 349         SBIT(P3_7, 0xB0, 7);
 350         SBIT(P3_6, 0xB0, 6);
 351         SBIT(P3_5, 0xB0, 5);
 352         SBIT(P3_4, 0xB0, 4);
 353         SBIT(P3_3, 0xB0, 3);
 354         SBIT(P3_2, 0xB0, 2);
 355         SBIT(P3_1, 0xB0, 1);
 356         SBIT(XTAL1,0xB0, 1);
 357         SBIT(P3_0, 0xB0, 0);
 358         SBIT(XTAL2,0xB0, 0);
 359 SFR(P0M1, 0x84); // Port 0 output mode 1
 360         #define P0M1_7  0x80
 361         #define P0M1_6  0x40
 362         #define P0M1_5  0x20
 363         #define P0M1_4  0x10
 364         #define P0M1_3  0x08
 365         #define P0M1_2  0x04
 366         #define P0M1_1  0x02
 367         #define P0M1_0  0x01
 368 SFR(P0M2, 0x85); // Port 0 output mode 2
 369         #define P0M2_7  0x80
 370         #define P0M2_6  0x40
 371         #define P0M2_5  0x20
 372         #define P0M2_4  0x10
 373         #define P0M2_3  0x08
 374         #define P0M2_2  0x04
 375         #define P0M2_1  0x02
 376         #define P0M2_0  0x01
 377 SFR(P1M1, 0x91); // Port 1 output mode 1
 378         #define P1M1_7  0x80
 379         #define P1M1_6  0x40
 380         #define P1M1_4  0x10
 381         #define P1M1_3  0x08
 382         #define P1M1_2  0x04
 383         #define P1M1_1  0x02
 384         #define P1M1_0  0x01
 385 SFR(P1M2, 0x92); // Port 1 output mode 2
 386         #define P1M2_7  0x80
 387         #define P1M2_6  0x40
 388         #define P1M2_4  0x10
 389         #define P1M2_3  0x08
 390         #define P1M2_2  0x04
 391         #define P1M2_1  0x02
 392         #define P1M2_0  0x01
 393 SFR(P2M1, 0xA4); // Port 2 output mode 1
 394         #define P2M1_7  0x80
 395         #define P2M1_6  0x40
 396         #define P2M1_5  0x20
 397         #define P2M1_4  0x10
 398         #define P2M1_3  0x08
 399         #define P2M1_2  0x04
 400         #define P2M1_1  0x02
 401         #define P2M1_0  0x01
 402 SFR(P2M2, 0xA5); // Port 2 output mode 2
 403         #define P2M2_7  0x80
 404         #define P2M2_6  0x40
 405         #define P2M2_5  0x20
 406         #define P2M2_4  0x10
 407         #define P2M2_3  0x08
 408         #define P2M2_2  0x04
 409         #define P2M2_1  0x02
 410         #define P2M2_0  0x01
 411 SFR(P3M1, 0xB1); // Port 3 output mode 1
 412         #define P3M1_1  0x02
 413         #define P3M1_0  0x01
 414 SFR(P3M2, 0xB2); // Port 3 output mode 2
 415         #define P3M2_1  0x02
 416         #define P3M2_0  0x01
 417 SFR(PCON,  0x87); // Power control register
 418         #define SMOD1   0x80
 419         #define SMOD0   0x40
 420         #define BOPD    0x20
 421         #define BOI     0x10
 422         #define GF1     0x08
 423         #define GF0     0x04
 424         #define PMOD1   0x02
 425         #define PMOD0   0x01
 426 SFR(PCONA, 0xB5); // Power control register A
 427         #define RTCPD   0x80
 428         #define DEEPD   0x40
 429         #define VCPD    0x20
 430         #define ADPD    0x10
 431         #define I2PD    0x08
 432         #define SPPD    0x04
 433         #define SPD     0x02
 434         #define CCUPR   0x01
 435 SFR(PSW, 0xD0); // Program Status Word
 436         SBIT(CY,  0xD0, 7);
 437         SBIT(AC,  0xD0, 6);
 438         SBIT(F0,  0xD0, 5);
 439         SBIT(RS1, 0xD0, 4);
 440         SBIT(RS0, 0xD0, 3);
 441         SBIT(OV,  0xD0, 2);
 442         SBIT(F1,  0xD0, 1);
 443         SBIT(P,   0xD0, 0);
 444 SFR(PT0AD, 0xF6); // Port 0 digital input disable
 445         #define PT0AD_5   0x20
 446         #define PT0AD_4   0x10
 447         #define PT0AD_3   0x08
 448         #define PT0AD_2   0x04
 449         #define PT0AD_1   0x02
 450 SFR(RSTSRC, 0xDF); // Reset source register
 451         #define BOF    0x20
 452         #define POF    0x10
 453         #define R_BK   0x08
 454         #define R_WD   0x04
 455         #define R_SF   0x02
 456         #define R_EX   0x01
 457 SFR(RTCCON, 0xD1); // Real-time clock control
 458         #define RTCF   0x80
 459         #define RTCS1  0x40
 460         #define RTCS0  0x20
 461         #define ERTC   0x02
 462         #define RTCEN  0x01
 463 SFR(RTCH,  0xD2); // Real-time clock register high
 464 SFR(RTCL,  0xD3); // Real-time clock register low
 465 SFR(SADDR, 0xA9); // Serial port address register
 466 SFR(SADEN, 0xB9); // Serial port address enable
 467 SFR(SBUF,  0x99); // Serial port data buffer register
 468 SFR(SCON,  0x98); // Serial port control
 469         SBIT(SM0_FE, 0x98, 7);
 470         SBIT(SM1,    0x98, 6);
 471         SBIT(SM2,    0x98, 5);
 472         SBIT(REN,    0x98, 4);
 473         SBIT(TB8,    0x98, 3);
 474         SBIT(RB8,    0x98, 2);
 475         SBIT(TI,     0x98, 1);
 476         SBIT(RI,     0x98, 0);
 477 SFR(SSTAT, 0xBA); // Serial port extended status register
 478         #define DBMOD  0x80
 479         #define INTLO  0x40
 480         #define CIDIS  0x20
 481         #define DBISEL 0x10
 482         #define FE     0x08
 483         #define BR     0x04
 484         #define OE     0x02
 485         #define STINT  0x01
 486 SFR(SP,     0x81); // Stack Pointer
 487 SFR(SPCTL,  0xE2); // SPI control register
 488         #define SSIG  0x80
 489         #define SPEN  0x40
 490         #define DORD  0x20
 491         #define MSTR  0x10
 492         #define CPOL  0x08
 493         #define CPHA  0x04
 494         #define SPR1  0x02
 495         #define SPR0  0x01
 496 SFR(SPSTAT, 0xE1); // SPI status register
 497         #define SPIF  0x80
 498         #define WCOL  0x40
 499 SFR(SPDAT,  0xE3); // SPI data register
 500 SFR(TAMOD,  0x8F); // Timer 0 and 1 auxiliary mode
 501         #define T1M2  0x10
 502         #define T0M2  0x01
 503 SFR(TCON,   0x88); // Timer 0 and 1 control
 504         SBIT(TF1, 0x88, 7);
 505         SBIT(TR1, 0x88, 6);
 506         SBIT(TF0, 0x88, 5);
 507         SBIT(TR0, 0x88, 4);
 508         SBIT(IE1, 0x88, 3);
 509         SBIT(IT1, 0x88, 2);
 510         SBIT(IE0, 0x88, 1);
 511         SBIT(IT0, 0x88, 0);
 512 SFR(TCR20,  0xC8); // CCU control register 0
 513         SBIT(PLEEN,  0xC8, 7);
 514         SBIT(HLTRN,  0xC8, 6);
 515         SBIT(HLTEN,  0xC8, 5);
 516         SBIT(ALTCD,  0xC8, 4);
 517         SBIT(ALTAB,  0xC8, 3);
 518         SBIT(TDIR2,  0xC8, 2);
 519         SBIT(TMOD21, 0xC8, 1);
 520         SBIT(TMOD20, 0xC8, 0);
 521 SFR(TCR21,  0xF9); // CCU control register 1
 522         #define TCOU2   0x80
 523         #define PLLDV_3 0x08
 524         #define PLLDV_2 0x04
 525         #define PLLDV_1 0x02
 526         #define PLLDV_0 0x01
 527 SFR(TH0,  0x8C); // Timer 0 high
 528 SFR(TH1,  0x8D); // Timer 1 high
 529 SFR(TH2,  0xCD); // CCU timer high
 530 SFR(TICR2,0xC9); // CCU interrupt control register
 531         #define TOIE2    0x80
 532         #define TOCIE2D  0x40
 533         #define TOCIE2C  0x20
 534         #define TOCIE2B  0x10
 535         #define TOCIE2A  0x08
 536         #define TICIE2B  0x02
 537         #define TICIE2A  0x01
 538 SFR(TIFR2,0xE9); // CCU interrupt flag register
 539         #define TOIF2    0x80
 540         #define TOCF2D  0x40
 541         #define TOCF2C  0x20
 542         #define TOCF2B  0x10
 543         #define TOCF2A  0x08
 544         #define TICF2B  0x02
 545         #define TICF2A  0x01
 546 SFR(TISE2,0xDE); // CCU interrupt status encode register
 547         #define ENCINT2  0x04
 548         #define ENCINT1  0x02
 549         #define ENCINT0  0x01
 550 SFR(TL0,   0x8A); // Timer 0 low
 551 SFR(TL1,   0x8B); // Timer 1 low
 552 SFR(TL2,   0xCC); // CCU timer low
 553 SFR(TMOD, 0x89); // Timer 0 and 1 mode
 554         #define T1GATE  0x80
 555         #define T1C_T   0x40
 556         #define T1M1    0x20
 557         #define T1M0    0x10
 558         #define T0GATE  0x08
 559         #define T0C_T   0x04
 560         #define T0M1    0x02
 561         #define T0M0    0x01
 562 SFR(TOR2H, 0xCF); // CCU reload register high
 563 SFR(TOR2L, 0xCE); // CCU reload register low
 564 SFR(TPCR2H,0xCB); // Prescaler control register high
 565         #define TPCR2H_1 0x02
 566         #define TPCR2H_0 0x01
 567 SFR(TPCR2L,0xCA); // Prescaler control register low
 568         #define TPCR2L_7 0x80
 569         #define TPCR2L_6 0x40
 570         #define TPCR2L_5 0x20
 571         #define TPCR2L_4 0x10
 572         #define TPCR2L_3 0x08
 573         #define TPCR2L_2 0x04
 574         #define TPCR2L_1 0x02
 575         #define TPCR2L_0 0x01
 576 SFR(TRIM, 0x96); // Internal oscillator trim register
 577         #define RCCLK   0x80
 578         #define ENCLK   0x40
 579         #define TRIM_5  0x20
 580         #define TRIM_4  0x10
 581         #define TRIM_3  0x08
 582         #define TRIM_2  0x04
 583         #define TRIM_1  0x02
 584         #define TRIM_0  0x01
 585 SFR(WDCON, 0xA7); // Watchdog control register
 586         #define PRE2    0x80
 587         #define PRE1    0x40
 588         #define PRE0    0x20
 589         #define WDRUN   0x04
 590         #define WDTOF   0x02
 591         #define WDCLK   0x01
 592 SFR(WDL,    0xC1); // Watchdog load
 593 SFR(WFEED1, 0xC2); // Watchdog feed 1
 594 SFR(WFEED2, 0xC3); // Watchdog feed 2
 595 #endif // __P89LPC935_6_H__