sdcc/device/include/mcs51/p89v51rd2.h

   1 /*-------------------------------------------------------------------------
   2    p89v51rd2.h - Register Declarations for the Philips P89V51RD2 Processor
   3
   4    Copyright (C) 2005, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   5
   6    This library is free software; you can redistribute it and/or modify it
   7    under the terms of the GNU General Public License as published by the
   8    Free Software Foundation; either version 2, or (at your option) any
   9    later version.
  10
  11    This library is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this library; see the file COPYING. If not, write to the
  18    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  19    MA 02110-1301, USA.
  20
  21    As a special exception, if you link this library with other files,
  22    some of which are compiled with SDCC, to produce an executable,
  23    this library does not by itself cause the resulting executable to
  24    be covered by the GNU General Public License. This exception does
  25    not however invalidate any other reasons why the executable file
  26    might be covered by the GNU General Public License.
  27 -------------------------------------------------------------------------*/
  28
  29
  30 #ifndef REG_P89V51RD2_H
  31 #define REG_P89V51RD2_H
  32
  33 #include <8052.h>     // Load definitions for the 8052
  34
  35 #ifdef REG8052_H
  36 #undef REG8052_H
  37 #endif
  38
  39 // Define P89V51RD2 specific registers only
  40
  41 __sfr __at (0x8E) AUXR;         //Auxiliary function register (Reset value 0x00).
  42         #define EXTRAM 0x02             //'0'=uses internal XRAM.
  43         #define AO 0x01                 //'1'=Disables ALE generation.
  44
  45 __sfr __at (0xA2) AUXR1;        //Auxiliary function register 1 (Reset value 0x00).
  46         #define GF2 0x08                //General purpose user-defined flag.
  47         #define DPS 0x01                //Data pointer select.
  48
  49 __sfr __at (0xFA) CCAP0H;       //Module 0 Capture HIGH.
  50 __sfr __at (0xFB) CCAP1H;       //Module 1 Capture HIGH.
  51 __sfr __at (0xFC) CCAP2H;       //Module 2 Capture HIGH.
  52 __sfr __at (0xFD) CCAP3H;       //Module 3 Capture HIGH.
  53 __sfr __at (0xFE) CCAP4H;       //Module 4 Capture HIGH.
  54 __sfr __at (0xEA) CCAP0L;       //Module 0 Capture LOW.
  55 __sfr __at (0xEB) CCAP1L;       //Module 1 Capture LOW.
  56 __sfr __at (0xEC) CCAP2L;       //Module 2 Capture LOW.
  57 __sfr __at (0xED) CCAP3L;       //Module 3 Capture LOW.
  58 __sfr __at (0xEE) CCAP4L;       //Module 4 Capture LOW.
  59
  60 __sfr __at (0xDA) CCAPM0;       //Module 0 Mode.
  61 __sfr __at (0xDB) CCAPM1;       //Module 1 Mode.
  62 __sfr __at (0xDC) CCAPM2;       //Module 2 Mode.
  63 __sfr __at (0xDD) CCAPM3;       //Module 3 Mode.
  64 __sfr __at (0xDE) CCAPM4;       //Module 4 Mode.
  65 //The preceding five registers have the following bits:
  66         #define ECOM 0x40               //Enable Comparator.
  67         #define CAPP 0x20               //1=enables positive edge capture.
  68         #define CAPN 0x10               //1=enables negative edge capture.
  69         #define MAT  0x08               //When counter matches sets CCF_n bit causing and interrupt.
  70         #define TOG  0x04               //Toggle output on match.
  71         #define PWM  0x02               //Pulse width modulation mode.
  72         #define ECCF 0x01               //Enable CCF interrupt.
  73
  74 __sfr __at (0xD8) CCON; //PCA Counter Control (Reset value 0x00)
  75         __sbit __at (0xDF) CF;  //PCA Counter overflow flag.
  76         __sbit __at (0xDE) CR ; //PCA Counter Run Control Bit. 1=counter on.  0=counter off.
  77         __sbit __at (0xDC) CCF4;//PCA Module 4 Interrupt Flag.
  78         __sbit __at (0xDB) CCF3;//PCA Module 3 Interrupt Flag.
  79         __sbit __at (0xDA) CCF2;//PCA Module 2 Interrupt Flag.
  80         __sbit __at (0xD9) CCF1;//PCA Module 1 Interrupt Flag.
  81         __sbit __at (0xD8) CCF0;//PCA Module 0 Interrupt Flag.
  82
  83 __sfr __at (0xF9) CH;           //PCA Counter HIGH.
  84 __sfr __at (0xE9) CL;           //PCA Counter LOW.
  85
  86 __sfr __at (0xD9) CMOD;         //PCA Counter Mode.
  87         #define CIDL 0x80               //CIDL=0 program the PCA counter to work during idle mode.
  88         #define WDTE 0x40               //Watchdog Timer Enable.
  89         #define CPS1 0x04               //PCA Count Pulse Select bit 1.
  90         #define CPS0 0x02               //PCA Count Pulse Select bit 0.
  91                                                         //00=Internal clock, Fosc/6
  92                                                         //01=Internal clock, Fosc/6
  93                                                         //10=Timer 0 overflow
  94                                                         //11=External clock at ECI/P1.2 pin (max rate=Fosc/4)
  95         #define ECF 0x01                //PCA Enable Counter Overflow Interrupt.
  96
  97 __sfr __at (0xB6) FST;          //Flash Status Register.
  98         #define SB 0x40
  99         #define EDC 0x08
 100
 101 __sfr __at (0xB1) FCF;          //Flash program memory bank selection.
 102         #define SWR  0x02
 103         #define BSEL 0x01
 104
 105 //Attention IEN0 is the same as register IE found in <8051.h> only bit EC added here.
 106 __sfr __at (0xA8) IEN0;         //Interrupt Enable 1.
 107         __sbit __at (0xAE) EC;  //PCA Interrupt Enable bit.
 108
 109 __sfr __at (0xE8) IEN1;         //Interrupt Enable 1
 110         __sbit __at (0xEB) EBO; //Brown-out Interrupt Enable. (Vector is 0x00b4).
 111
 112 //Attention IP0 is the same as register IP found in <8051.h> only bit PPC added here.
 113 __sfr __at (0xB8) IP0;          //Interrupt Priority 0 HIGH.
 114         __sbit __at (0xBE) PPC; //PCA Interrupt Priority low bit.
 115
 116 __sfr __at (0xB7) IP0H;         //Interrupt Priority 0 HIGH
 117         #define PPCH 0x40               //PCA Interrupt Priority High Bit.
 118         #define PT2H 0x20               //Timer 2 Interrupt Interrupt Priority High Bit.
 119         #define PSH  0x10               //Serial Port Interrupt Priority High Bit.
 120         #define PT1H 0x08               //Timer 1 Interrupt Priority High Bit.
 121         #define PX1H 0x04               //External Interrupt 1 Priority High Bit.
 122         #define PT0H 0x02               //Timer 0 Interrupt Priority High Bit.
 123         #define PX0H 0x01               //External Interrupt 0 Priority High Bit.
 124
 125 __sfr __at (0xF8) IP1;          //Interrupt Priority 1.
 126         __sbit __at (0xFB) PBO; //Brown-out Interrupt Priority Bit.
 127
 128 __sfr __at (0xF7) IP1H;         //Interrupt Priority 1 HIGH.
 129         #define PBOH 0x08               //Brown-out Interrupt Priority High Bit.
 130
 131 __sfr __at (0xA9) SADDR;        //Serial Port Address Register.
 132 __sfr __at (0xB9) SADEN;        //Serial Port Address Enable.
 133
 134 __sfr __at (0xD5) SPCR;         //SPI Control Register (Reset value 00000000B).
 135 __sfr __at (0xD5) SPCTL;        //SPI Control Register (This name appears also in the datasheet).
 136         #define SPIE 0x80               //If both SPIE and ES are set to one, SPI interrupts are enabled.
 137         #define SPEN 0x40               //SPI enable bit.  When set enables SPI.
 138         #define SPE  0x40               //Same as above.  This name appears also in the manual :-(
 139         #define DORD 0x20               //Data trans. order. 0=MSB first; 1=LSB first.
 140         #define MSTR 0x10               //1=master mode.  0=slave mode.
 141         #define CPOL 0x08               //1=SCK is high when idle (active low), 0=SCK is low when idle (active high).
 142         #define CPHA 0x04               //1=shift triggered on the trailing edge of SCK.  0=shift trig. on leading edge.
 143         #define SPR1 0x02               //SPI Clork Rate select bit 1.
 144         #define SPR0 0x01               //SPI Clork Rate select bit 0.
 145                                                         //00 = Fosc/4
 146                                                         //01 = Fosc/16
 147                                                         //10 = Fosc/64
 148                                                         //11 = Fosc/128
 149
 150 __sfr __at (0xAA) SPSR;         //SPI Configuration Register (Reset value 00000000B).
 151 __sfr __at (0xAA) SPCFG;        //SPI Configuration Register (This name appears also in the datasheet).
 152         #define SPIF 0x80               //SPI interrupt flag.
 153         #define SPWCOL 0x40             //Write collision Flag.
 154
 155 __sfr __at (0x86) SPDR;         //SPI Data
 156 __sfr __at (0x86) SPDAT;        //SPI Data (This name appears also in the datasheet).
 157
 158 __sfr __at (0xC0) WDTC;         //Watchdog Timer Control (Reset value 0x00).
 159         __sbit __at (0xC4) WDOUT;//Watchdog output enable.
 160         __sbit __at (0xC3) WDRE; //Watchdog timer reset enable.
 161         __sbit __at (0xC2) WDTS; //Watchdog timer reset flag.
 162         __sbit __at (0xC1) WDT;  //Watchdog timer refresh.
 163         __sbit __at (0xC0) SWDT; //Start watchdog timer.
 164
 165 __sfr __at (0x85) WDTD;         //Watchdog Timer Data/Reload.
 166
 167 __sfr __at (0xC9) T2MOD;        //Timer 2 mode control
 168         #define DCEN  0x01              //Down count enable bit
 169         #define T2OE  0x02              //Timer 2 Output Enable bit.
 170         #define ENT2  0x20              //No description???
 171
 172 #endif /*REG_P89V51RD2_H*/