sdcc/device/include/mcs51/p89v66x.h

   1 /*-------------------------------------------------------------------------
   2    p89v66x.h - This header allows to use the microcontroler NXP
   3    (formerly Philips) p89v66x where x stands for 0,2,4.
   4
   5    Copyright (C) 2008, Gudjon I. Gudjonsson <gudjon AT gudjon.org>
   6
   7    This library is free software; you can redistribute it and/or modify it
   8    under the terms of the GNU General Public License as published by the
   9    Free Software Foundation; either version 2, or (at your option) any
  10    later version.
  11
  12    This library is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this library; see the file COPYING. If not, write to the
  19    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  20    MA 02110-1301, USA.
  21
  22    As a special exception, if you link this library with other files,
  23    some of which are compiled with SDCC, to produce an executable,
  24    this library does not by itself cause the resulting executable to
  25    be covered by the GNU General Public License. This exception does
  26    not however invalidate any other reasons why the executable file
  27    might be covered by the GNU General Public License.
  28 -------------------------------------------------------------------------*/
  29
  30 /*-------------------------------------------------------------------------
  31  The registered are ordered in the same way as in the NXP data sheet:
  32  http://www.standardics.nxp.com/products/80c51/datasheet/p89v660.p89v662.p89v664.pdf
  33 -------------------------------------------------------------------------*/
  34
  35 #ifndef __P89V66X_H__
  36 #define __P89V66X_H__
  37 #include <compiler.h>
  38
  39 /*BYTE Registers*/
  40 SFR(ACC, 0xE0); // Accumulator
  41         SBIT(ACC_7, 0xE0, 7);
  42         SBIT(ACC_6, 0xE0, 6);
  43         SBIT(ACC_5, 0xE0, 5);
  44         SBIT(ACC_4, 0xE0, 4);
  45         SBIT(ACC_3, 0xE0, 3);
  46         SBIT(ACC_2, 0xE0, 2);
  47         SBIT(ACC_1, 0xE0, 1);
  48         SBIT(ACC_0, 0xE0, 0);
  49 SFR(AUXR, 0x8E); // Auxiliary
  50         #define  EXTRAM   0x02
  51         #define  AO       0x01
  52 SFR(AUXR1, 0xA2); // Auxiliary 1
  53         #define  ENBOOT   0x20
  54         #define  GF2      0x08
  55         // Bit 2 must be zero
  56         #define  DPS      0x01
  57 SFR(B, 0xF0); // B register
  58         SBIT(B7, 0xF0, 7);
  59         SBIT(B6, 0xF0, 6);
  60         SBIT(B5, 0xF0, 5);
  61         SBIT(B4, 0xF0, 4);
  62         SBIT(B3, 0xF0, 3);
  63         SBIT(B2, 0xF0, 2);
  64         SBIT(B1, 0xF0, 1);
  65         SBIT(B0, 0xF0, 0);
  66 SFR(CCAP0H, 0xFA); // Module 0 Capture High
  67 SFR(CCAP1H, 0xFB); // Module 1 Capture High
  68 SFR(CCAP2H, 0xFC); // Module 2 Capture High
  69 SFR(CCAP3H, 0xFD); // Module 3 Capture High
  70 SFR(CCAP4H, 0xFE); // Module 4 Capture High
  71 SFR(CCAP0L, 0xEA); // Module 0 Capture Low
  72 SFR(CCAP1L, 0xEB); // Module 1 Capture Low
  73 SFR(CCAP2L, 0xEC); // Module 2 Capture Low
  74 SFR(CCAP3L, 0xED); // Module 3 Capture Low
  75 SFR(CCAP4L, 0xEE); // Module 4 Capture Low
  76 SFR(CCAPM0, 0xC2); // Module 0 Mode
  77         #define ECOM_0   0x40
  78         #define CAPP_0   0x20
  79         #define CAPN_0   0x10
  80         #define  MAT_0   0x08
  81         #define  TOG_0   0x04
  82         #define  PWM_0   0x02
  83         #define ECCF_0   0x01
  84 SFR(CCAPM1, 0xC3); // Module 1 Mode
  85         #define ECOM_1   0x40
  86         #define CAPP_1   0x20
  87         #define CAPN_1   0x10
  88         #define  MAT_1   0x08
  89         #define  TOG_1   0x04
  90         #define  PWM_1   0x02
  91         #define ECCF_1   0x01
  92 SFR(CCAPM2, 0xC4); // Module 2 Mode
  93         #define ECOM_2   0x40
  94         #define CAPP_2   0x20
  95         #define CAPN_2   0x10
  96         #define  MAT_2   0x08
  97         #define  TOG_2   0x04
  98         #define  PWM_2   0x02
  99         #define ECCF_2   0x01
 100 SFR(CCAPM3, 0xC5); // Module 3 Mode
 101         #define ECOM_3   0x40
 102         #define CAPP_3   0x20
 103         #define CAPN_3   0x10
 104         #define  MAT_3   0x08
 105         #define  TOG_3   0x04
 106         #define  PWM_3   0x02
 107         #define ECCF_3   0x01
 108 SFR(CCAPM4, 0xC6); // Module 4 Mode
 109         #define ECOM_4   0x40
 110         #define CAPP_4   0x20
 111         #define CAPN_4   0x10
 112         #define  MAT_4   0x08
 113         #define  TOG_4   0x04
 114         #define  PWM_4   0x02
 115         #define ECCF_4   0x01
 116         #define ECOM     0x40
 117         #define CAPP     0x20
 118         #define CAPN     0x10
 119         #define MAT      0x08
 120         #define TOG      0x04
 121         #define PWM      0x02
 122         #define ECCF     0x01
 123 SFR(CCON,   0xC0); // PCA Counter Control
 124         SBIT(CF,   0xC0, 7);
 125         SBIT(CR,   0xC0, 6);
 126         SBIT(CCF4, 0xC0, 4);
 127         SBIT(CCF3, 0xC0, 3);
 128         SBIT(CCF2, 0xC0, 2);
 129         SBIT(CCF1, 0xC0, 1);
 130         SBIT(CCF0, 0xC0, 0);
 131 SFR(CH,   0xF9); // PCA Counter High
 132 SFR(CL,   0xE9); // PCA Counter Low
 133 SFR(CMOD, 0xC1); // PCA Counter Mode
 134         #define CIDL    0x80
 135         #define WDTE    0x40
 136         #define CPS1    0x04
 137         #define CPS0    0x02
 138         #define  ECF    0x01
 139 SFR(DPH,  0x83); // Data Pointer High
 140 SFR(DPL,  0x82); // Data Pointer Low
 141 SFR(IEN0, 0xA8); // Interrupt Enable 0
 142         SBIT(EA,  0xA8, 7);
 143         SBIT(EC,  0xA8, 6);
 144         SBIT(ES1, 0xA8, 5);
 145         SBIT(ES0, 0xA8, 4);
 146         SBIT(ET1, 0xA8, 3);
 147         SBIT(EX1, 0xA8, 2);
 148         SBIT(ET0, 0xA8, 1);
 149         SBIT(EX0, 0xA8, 0);
 150 SFR(IEN1, 0xE8); // Interrupt Enable 1
 151         SBIT(ES3, 0xE8, 2);
 152         SBIT(ES2, 0xE8, 1);
 153         SBIT(ET2, 0xE8, 0);
 154 SFR(IP0, 0xB8); // Interrupt Priority 0
 155         SBIT(PT2, 0xB8, 7);
 156         SBIT(PPC, 0xB8, 6);
 157         SBIT(PS1, 0xB8, 5);
 158         SBIT(PS0, 0xB8, 4);
 159         SBIT(PT1, 0xB8, 3);
 160         SBIT(PX1, 0xB8, 2);
 161         SBIT(PT0, 0xB8, 1);
 162         SBIT(PX0, 0xB8, 0);
 163 SFR(IP0H, 0xB7); // Interrupt Priority 0 High
 164         #define PT2H  0x80
 165         #define PPCH  0x40
 166         #define PS1H  0x20
 167         #define PS0H  0x10
 168         #define PT1H  0x08
 169         #define PX1H  0x04
 170         #define PT0H  0x02
 171         #define PX0H  0x01
 172 SFR(IP1, 0x91); // Interrupt Priority 1
 173         #define PS3  0x02
 174         #define PS2  0x01
 175 SFR(IP1H, 0x92); // Interrupt Priority 1 High
 176         #define PS3H  0x02
 177         #define PS2H  0x01
 178 SFR(P0, 0x80); // Port 0
 179         SBIT(AD7,  0x80, 7);
 180         SBIT(P0_7, 0x80, 7);
 181         SBIT(AD6,  0x80, 6);
 182         SBIT(P0_6, 0x80, 6);
 183         SBIT(AD5,  0x80, 5);
 184         SBIT(P0_5, 0x80, 5);
 185         SBIT(AD4,  0x80, 4);
 186         SBIT(P0_4, 0x80, 4);
 187         SBIT(AD3,  0x80, 3);
 188         SBIT(P0_3, 0x80, 3);
 189         SBIT(AD2,  0x80, 2);
 190         SBIT(P0_2, 0x80, 2);
 191         SBIT(AD1,  0x80, 1);
 192         SBIT(P0_1, 0x80, 1);
 193         SBIT(AD0,  0x80, 0);
 194         SBIT(P0_0, 0x80, 0);
 195 SFR(P1, 0x90); // Port 1
 196         SBIT(T1_CEX4, 0x90, 7);
 197         SBIT(P1_7,    0x90, 7);
 198         SBIT(T0_CEX3, 0x90, 6);
 199         SBIT(P1_6,    0x90, 6);
 200         SBIT(CEX2,    0x90, 5);
 201         SBIT(P1_5,    0x90, 5);
 202         SBIT(CEX1,    0x90, 4);
 203         SBIT(P1_4,    0x90, 4);
 204         SBIT(CEX0,    0x90, 3);
 205         SBIT(P1_3,    0x90, 3);
 206         SBIT(ECI,     0x90, 2);
 207         SBIT(P1_2,    0x90, 2);
 208         SBIT(T2EX,    0x90, 1);
 209         SBIT(P1_1,    0x90, 1);
 210         SBIT(T2,      0x90, 0);
 211         SBIT(P1_0,    0x90, 0);
 212 SFR(P2, 0xA0); // Port 2
 213         SBIT(AD15, 0xA0, 7);
 214         SBIT(P2_7, 0xA0, 7);
 215         SBIT(AD14, 0xA0, 6);
 216         SBIT(P2_6, 0xA0, 6);
 217         SBIT(AD13, 0xA0, 5);
 218         SBIT(P2_5, 0xA0, 5);
 219         SBIT(AD12, 0xA0, 4);
 220         SBIT(P2_4, 0xA0, 4);
 221         SBIT(AD11, 0xA0, 3);
 222         SBIT(P2_3, 0xA0, 3);
 223         SBIT(AD10, 0xA0, 2);
 224         SBIT(P2_2, 0xA0, 2);
 225         SBIT(AD9,  0xA0, 1);
 226         SBIT(P2_1, 0xA0, 1);
 227         SBIT(AD8,  0xA0, 0);
 228         SBIT(P2_0, 0xA0, 0);
 229 SFR(P3, 0xB0); // Port 3
 230         SBIT(RD,   0xB0, 7);
 231         SBIT(P3_7, 0xB0, 7);
 232         SBIT(WR,   0xB0, 6);
 233         SBIT(P3_6, 0xB0, 6);
 234         SBIT(T1,   0xB0, 5);
 235         SBIT(P3_5, 0xB0, 5);
 236         SBIT(T0,   0xB0, 4);
 237         SBIT(P3_4, 0xB0, 4);
 238         SBIT(INT1, 0xB0, 3);
 239         SBIT(P3_3, 0xB0, 3);
 240         SBIT(INT0, 0xB0, 2);
 241         SBIT(P3_2, 0xB0, 2);
 242         SBIT(TXD,  0xB0, 1);
 243         SBIT(P3_1, 0xB0, 1);
 244         SBIT(RXD,  0xB0, 0);
 245         SBIT(P3_0, 0xB0, 0);
 246 SFR(P4, 0xA1); // Port 3
 247         #define SS    0x08
 248         #define P4_3  0x08
 249         #define MOSI  0x04
 250         #define P4_2  0x04
 251         #define MISO  0x02
 252         #define SDA_1 0x02
 253         #define P4_1  0x02
 254         #define SCK   0x01
 255         #define SCL_1 0x01
 256         #define P4_0  0x01
 257 SFR(PCON, 0x87); // Power Control
 258         #define SMOD1  0x80
 259         #define SMOD0  0x40
 260         #define POF    0x10
 261         #define GF1    0x08
 262         #define GF0    0x04
 263         #define PD     0x02
 264         #define IDL    0x01
 265 SFR(PSW, 0xD0); // Program Status Word
 266         SBIT(CY,  0xD0, 7);
 267         SBIT(AC,  0xD0, 6);
 268         SBIT(F0,  0xD0, 5);
 269         SBIT(RS1, 0xD0, 4);
 270         SBIT(RS0, 0xD0, 3);
 271         SBIT(OV,  0xD0, 2);
 272         SBIT(F1,  0xD0, 1);
 273         SBIT(P,   0xD0, 0);
 274 SFR(RCAP2H, 0xCB); // Timer 2 Capture High
 275 SFR(RCAP2L, 0xCA); // Timer 2 Capture Low
 276 SFR(S0CON,  0x98); // Serial Control
 277         SBIT(SM0_FE,0x98, 7);
 278         SBIT(SM1,   0x98, 6);
 279         SBIT(SM2,   0x98, 5);
 280         SBIT(REN,   0x98, 4);
 281         SBIT(TB8,   0x98, 3);
 282         SBIT(RB8,   0x98, 2);
 283         SBIT(TI,    0x98, 1);
 284         SBIT(RI,    0x98, 0);
 285 SFR(S0BUF, 0x99); // Serial Data Buffer
 286 SFR(SADDR, 0xA9); // I2C Slave Address
 287 SFR(SADEN, 0xB9); // I2C Slave Address Mask
 288 SFR(SPCR,  0xD5); // SPI Control Register
 289         #define SPIE  0x80
 290         #define SPEN  0x40
 291         #define DORD  0x20
 292         #define MSTR  0x10
 293         #define CPOL  0x08
 294         #define CPHA  0x04
 295         #define SPR1  0x02
 296         #define SPR0  0x01
 297 /*      SBIT(SPIE,   0x80, 7);   // SPCR is not bit addressable, not yet at least, according to the manual.
 298         SBIT(SPEN,   0x80, 6);
 299         SBIT(DORD,   0x80, 5);
 300         SBIT(MSTR,   0x80, 4);
 301         SBIT(CPOL,   0x80, 3);
 302         SBIT(CPHA,   0x80, 2);
 303         SBIT(SPR1,   0x80, 1);
 304         SBIT(SPR0,   0x80, 0);*/
 305 SFR(SPSR,  0xAA); // SPI Configuration Register
 306         #define SPIF  0x80
 307         #define WCOL  0x40
 308 SFR(SPDAT, 0x86); // SPI Data
 309 SFR(SP,    0x81); // Stack Pointer
 310 SFR(S1DAT, 0xDA); // I2C Serial 1 Data
 311 SFR(S1ADR, 0xDB); // I2C Serial 1 Address
 312         #define S1ADR_6  0x80
 313         #define S1ADR_5  0x40
 314         #define S1ADR_4  0x20
 315         #define S1ADR_3  0x10
 316         #define S1ADR_2  0x08
 317         #define S1ADR_1  0x04
 318         #define S1ADR_0  0x02
 319         #define S1GC     0x01
 320 SFR(S1STA, 0xD9); // I2C Serial 1 Status
 321         #define SC4  0x80
 322         #define SC3  0x40
 323         #define SC2  0x20
 324         #define SC1  0x10
 325         #define SC0  0x08    // Only write 0 to the lowest three bits
 326 SFR(S1CON, 0xD8); // I2C Serial 1 Control
 327         SBIT(CR2,  0xD8, 7);
 328         SBIT(ENS1, 0xD8, 6);
 329         SBIT(STA,  0xD8, 5);
 330         SBIT(STO,  0xD8, 4);
 331         SBIT(SI,   0xD8, 3);
 332         SBIT(AA,   0xD8, 2);
 333         SBIT(CR1,  0xD8, 1);
 334         SBIT(CR0,  0xD8, 0);
 335 SFR(S2DAT, 0xE2); // I2C Serial 1 Data
 336 SFR(S2ADR, 0xE3); // I2C Serial 1 Address
 337         #define S2ADR_6  0x80
 338         #define S2ADR_5  0x40
 339         #define S2ADR_4  0x20
 340         #define S2ADR_3  0x10
 341         #define S2ADR_2  0x08
 342         #define S2ADR_1  0x04
 343         #define S2ADR_0  0x02
 344         #define S2GC     0x01
 345 SFR(S2STA, 0xE1); // I2C Serial 1 Status
 346         #define SC24  0x80
 347         #define SC23  0x40
 348         #define SC22  0x20
 349         #define SC21  0x10
 350         #define SC20  0x08  // Only write 0 to the lowest three bits
 351 SFR(S2CON, 0xF8); // I2C Serial 1 Control
 352         SBIT(CR22,  0xF8, 7);
 353         SBIT(ENS21, 0xF8, 6);
 354         SBIT(STA2,  0xF8, 5);
 355         SBIT(STO2,  0xF8, 4);
 356         SBIT(SI2,   0xF8, 3);
 357         SBIT(AA2,   0xF8, 2);
 358         SBIT(CR21,  0xF8, 1);
 359         SBIT(CR20,  0xF8, 0);
 360 SFR(TCON, 0x88); // Timer Control
 361         SBIT(TF1, 0x88, 7);
 362         SBIT(TR1, 0x88, 6);
 363         SBIT(TF0, 0x88, 5);
 364         SBIT(TR0, 0x88, 4);
 365         SBIT(IE1, 0x88, 3);
 366         SBIT(IT1, 0x88, 2);
 367         SBIT(IE0, 0x88, 1);
 368         SBIT(IT0, 0x88, 0);
 369 SFR(T2CON, 0xC8); // Timer 2 Control
 370         SBIT(TF2,    0xC8, 7);
 371         SBIT(EXF2,   0xC8, 6);
 372         SBIT(RCLK,   0xC8, 5);
 373         SBIT(TCLK,   0xC8, 4);
 374         SBIT(EXEN2,  0xC8, 3);
 375         SBIT(TR2,    0xC8, 2);
 376         SBIT(C_T2,   0xC8, 1);
 377         SBIT(CP_RL2, 0xC8, 0);
 378 SFR(T2MOD,  0xC9); // Timer 2 Mode Control
 379         #define ENT2  0x20
 380         #define T2OE  0x02
 381         #define DCEN  0x01
 382 SFR(TH0,  0x8C); // Timer High 0
 383 SFR(TH1,  0x8D); // Timer High 1
 384 SFR(TH2,  0xCD); // Timer High 2
 385 SFR(TL0,  0x8A); // Timer Low 0
 386 SFR(TL1,  0x8B); // Timer Low 1
 387 SFR(TL2,  0xCC); // Timer Low 2
 388 SFR(TMOD, 0x89); // Timer Mode
 389         #define GATE_1  0x80
 390         #define  C_T_1  0x40
 391         #define   M1_1  0x20
 392         #define   M0_1  0x10
 393         #define GATE_0  0x08
 394         #define  C_T_0  0x04
 395         #define   M1_0  0x02
 396         #define   M0_0  0x01
 397 SFR(WDTRST, 0xA6); // Watchdog Timer Reset
 398
 399 #endif  //__P89V66X_H__