sdcc/device/include/mcs51/reg764.h

   1 /*-------------------------------------------------------------------------
   2    reg764 - register Declarations for 87C764
   3
   4    Copyright (C) 2005, Robert Lacoste <robert_lacoste AT yahoo.fr>
   5      based upon reg51.h written by Sandeep Dutta
   6      Registers are taken from the Phillips Semiconductor
   7
   8    This library is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published by the
  10    Free Software Foundation; either version 2, or (at your option) any
  11    later version.
  12
  13    This library is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this library; see the file COPYING. If not, write to the
  20    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  21    MA 02110-1301, USA.
  22
  23    As a special exception, if you link this library with other files,
  24    some of which are compiled with SDCC, to produce an executable,
  25    this library does not by itself cause the resulting executable to
  26    be covered by the GNU General Public License. This exception does
  27    not however invalidate any other reasons why the executable file
  28    might be covered by the GNU General Public License.
  29 -------------------------------------------------------------------------*/
  30
  31 #ifndef REGC764_H
  32 #define REGC764_H
  33
  34 #include <compiler.h>
  35
  36 /*  Special Function Registers  */
  37
  38 SFR(P0,         0x80);   // Port 0
  39 SFR(SP,         0x81);   // Stack Pointer
  40 SFR(DPL,        0x82);   // Data Pointer Low
  41 SFR(DPH,        0x83);   // Data Pointer High
  42 SFR(P0M1,       0x84);   // Port 0 output mode 1
  43 SFR(P0M2,       0x85);   // Port 0 output mode 2
  44 SFR(KBI,        0x86);   // Keyboard interrupt
  45 SFR(PCON,       0x87);   // Power Control
  46 SFR(TCON,       0x88);   // Timer Control
  47 SFR(TMOD,       0x89);   // Timer Mode
  48 SFR(TL0,        0x8A);   // Timer Low 0
  49 SFR(TL1,        0x8B);   // Timer Low 1
  50 SFR(TH0,        0x8C);   // Timer High 0
  51 SFR(TH1,        0x8D);   // Timer High 1
  52
  53 SFR(P1,         0x90);   // Port 1
  54 SFR(P1M1,       0x91);   // Port 1 output mode 1
  55 SFR(P1M2,       0x92);   // Port 1 output mode 2
  56 SFR(DIVM,       0x95);   // CPU clock divide by N control
  57 SFR(SCON,       0x98);   // Serial Control
  58 SFR(SBUF,       0x99);   // Serial Data Buffer
  59
  60 SFR(P2,         0xA0);   // Port 2
  61 SFR(AUXR1,      0xA2);   // Auxilliary 1 (not available on 80C51FA/87C51Fx)
  62 SFR(P2M1,       0xA4);   // Port 2 output mode 1
  63 SFR(P2M2,       0xA5);   // Port 2 output mode 2
  64 SFR(WDRST,      0xA6);   // Watchdog reset register
  65 SFR(WDCON,      0xA7);   // Watchdog control register
  66 SFR(IEN0,       0xA8);   // Interrupt Enable 0
  67 SFR(SADDR,      0xA9);   // Serial slave Address
  68 SFR(CMP1,       0xAC);   // Comparator 1 control register
  69 SFR(CMP2,       0xAD);   // Comparator 2 control register
  70
  71 SFR(IP0H,       0xB7);   // Interrupt Priority 0 High
  72 SFR(IP0,        0xB8);   // Interrupt Priority 0
  73 SFR(SADEN,      0xB9);   // Serial slave Address Mask
  74
  75 SFR(I2CFG,      0xC8);   // I2C configuration register
  76
  77 SFR(PSW,        0xD0);   // Program Status Word
  78 SFR(I2CON,      0xD8);   // I2C control register
  79 SFR(I2DAT,      0xD9);   // I2C data register
  80
  81 SFR(ACC,        0xE0);   // Accumulator
  82 SFR(IEN1,       0xE8);   // Interrupt enable 1
  83
  84 SFR(B,          0xF0);   // B Register
  85 SFR(PT0AD,      0xF6);   // Port 0 digital input disable
  86 SFR(IP1H,       0xF7);   // Interrupt Priority 1 High
  87 SFR(IP1,        0xF8);   // Interrupt Priority 1
  88
  89
  90 /*  Bit Addressable Registers  */
  91
  92 /*  P0    */
  93 SBIT(P0_0,              0x80,   0); // Also CMP2
  94 SBIT(P0_1,              0x80,   1); // Also CIN2B
  95 SBIT(P0_2,              0x80,   2); // Also CIN2A
  96 SBIT(P0_3,              0x80,   3); // Also CIN1B
  97 SBIT(P0_4,              0x80,   4); // Also CIN1A
  98 SBIT(P0_5,              0x80,   5); // Also CMPREF
  99 SBIT(P0_6,              0x80,   6); // Also CMP1
 100 SBIT(P0_7,              0x80,   7); // Also T1
 101
 102 /*  TCON  */
 103 SBIT(IT0,               0x88,   0); // External Interrupt 0 Type
 104 SBIT(IE0,               0x88,   1); // External Interrupt 0 Edge Flag
 105 SBIT(IT1,               0x88,   2); // External Interrupt 1 Type
 106 SBIT(IE1,               0x88,   3); // External Interrupt 1 Edge Flag
 107 SBIT(TR0,               0x88,   4); // Timer 0 Run Control
 108 SBIT(TF0,               0x88,   5); // Timer 0 Overflow Flag
 109 SBIT(TR1,               0x88,   6); // Timer 1 Run Control
 110 SBIT(TF1,               0x88,   7); // Timer 1 Overflow Flag
 111
 112 /*  P1 */
 113 SBIT(P1_0,              0x90,   0); // Also TxD
 114 SBIT(P1_1,              0x90,   1); // Also RxD
 115 SBIT(P1_2,              0x90,   2); // Also T0
 116 SBIT(P1_3,              0x90,   3); // Also INT0
 117 SBIT(P1_4,              0x90,   4); // Also INT1
 118 SBIT(P1_5,              0x90,   5); // Also RST
 119 SBIT(P1_6,              0x90,   6);
 120 SBIT(P1_7,              0x90,   7);
 121
 122 /*  SCON  */
 123 SBIT(RI,                0x98,   0); // Receive Interrupt Flag
 124 SBIT(TI,                0x98,   1); // Transmit Interrupt Flag
 125 SBIT(RB8,               0x98,   2); // Receive Bit 8
 126 SBIT(TB8,               0x98,   3); // Transmit Bit 8
 127 SBIT(REN,               0x98,   4); // Receiver Enable
 128 SBIT(SM2,               0x98,   5); // Serial Mode Control Bit 2
 129 SBIT(SM1,               0x98,   6); // Serial Mode Control Bit 1
 130 SBIT(SM0,               0x98,   7); // Serial Mode Control Bit 0
 131
 132 /*  P2    */
 133 SBIT(P2_0,              0xA0,   0); // Also X2
 134 SBIT(P2_1,              0xA0,   1); // Also X1
 135
 136 /*  IEN0 */
 137 SBIT(EX0,               0xA8,   0); // External Interrupt 0 Enable
 138 SBIT(ET0,               0xA8,   1); // Timer 0 Interrupt Enable
 139 SBIT(EX1,               0xA8,   2); // External Interrupt 1 Enable
 140 SBIT(ET1,               0xA8,   3); // Timer 1 Interrupt Enable
 141 SBIT(ES,                0xA8,   4); // Serial Port Interrupt Enable
 142 SBIT(EBO,               0xA8,   5); // Brownout Interrupt Enable
 143 SBIT(EWD,               0xA8,   6); // Watchdog Interrupt Enable
 144 SBIT(EA,                0xA8,   7); // Global Interrupt Enable
 145
 146 /*  IP0   */
 147 SBIT(PX0,               0xB8,   0); // External Interrupt 0 Priority
 148 SBIT(PT0,               0xB8,   1); // Timer 0 Interrupt Priority
 149 SBIT(PX1,               0xB8,   2); // External Interrupt 1 Priority
 150 SBIT(PT1,               0xB8,   3); // Timer 1 Interrupt Priority
 151 SBIT(PS,                0xB8,   4); // Serial Port Interrupt Priority
 152 SBIT(PBO,               0xB8,   5); // Brownout Interrupt Priority
 153 SBIT(PWD,               0xB8,   6); // Watchdog Interrupt Priority
 154
 155 /*  I2CFG */
 156 SBIT(CT0,               0xC8,   0); // Clock Time Select 0
 157 SBIT(CT1,               0xC8,   1); // Clock Time Select 1
 158 SBIT(TIRUN,             0xC8,   4); // Timer I Run Enable
 159 SBIT(CLRTI,             0xC8,   5); // Clear Timer I
 160 SBIT(MASTRQ,    0xC8,   6); // Master Request
 161 SBIT(SLAVEN,    0xC8,   7); // Slave Enable
 162
 163 /*  PSW   */
 164 SBIT(P,                 0xD0,   0); // Accumulator Parity Flag
 165 SBIT(F1,                0xD0,   1); // Flag 1
 166 SBIT(OV,                0xD0,   2); // Overflow Flag
 167 SBIT(RS0,               0xD0,   3); // Register Bank Select 0
 168 SBIT(RS1,               0xD0,   4); // Register Bank Select 1
 169 SBIT(F0,                0xD0,   5); // Flag 0
 170 SBIT(AC,                0xD0,   6); // Auxiliary Carry Flag
 171 SBIT(CY,                0xD0,   7); // Carry Flag
 172
 173 /*  I2CON */
 174 SBIT(XSTP,              0xD8,   0);
 175 SBIT(MASTER,    0xD8,   1);// Master Status
 176 SBIT(STP,               0xD8,   2); // Stop Detect Flag
 177 SBIT(STR,               0xD8,   3); // Start Detect Flag
 178 SBIT(ARL,               0xD8,   4); // Arbitration Loss Flag
 179 SBIT(DRDY,              0xD8,   5); // Data Ready Flag
 180 SBIT(ATN,               0xD8,   6); // Attention: I2C Interrupt Flag
 181 SBIT(RDAT,              0xD8,   7); // I2C Read Data
 182
 183 /*  ACC   */
 184 SBIT(ACC_0,             0xE0,   0);
 185 SBIT(ACC_1,             0xE0,   1);
 186 SBIT(ACC_2,             0xE0,   2);
 187 SBIT(ACC_3,             0xE0,   3);
 188 SBIT(ACC_4,             0xE0,   4);
 189 SBIT(ACC_5,             0xE0,   5);
 190 SBIT(ACC_6,             0xE0,   6);
 191 SBIT(ACC_7,             0xE0,   7);
 192
 193 /*  IEN1  */
 194 SBIT(EI2,               0xE8,   0); // I2C Interrupt Enable
 195 SBIT(EKB,               0xE8,   1); // Keyboard Interrupt Enable
 196 SBIT(EC2,               0xE8,   2); // Comparator 2 Interrupt Enable
 197 SBIT(EC1,               0xE8,   5); // Comparator 1 Interrupt Enable
 198 SBIT(ETI,               0xE8,   7); // Timer I Interrupt Enable
 199
 200 /*  B     */
 201 SBIT(B_0,               0xF0,   0);
 202 SBIT(B_1,               0xF0,   1);
 203 SBIT(B_2,               0xF0,   2);
 204 SBIT(B_3,               0xF0,   3);
 205 SBIT(B_4,               0xF0,   4);
 206 SBIT(B_5,               0xF0,   5);
 207 SBIT(B_6,               0xF0,   6);
 208 SBIT(B_7,               0xF0,   7);
 209
 210 /*  IP1  */
 211 SBIT(PI2,               0xF8,   0); // I2C Interrupt Priority
 212 SBIT(PKB,               0xF8,   1); // Keyboard Interrupt Priority
 213 SBIT(PC2,               0xF8,   2); // Comparator 2 Interrupt Priority
 214 SBIT(PC1,               0xF8,   5); // Comparator 1 Interrupt Priority
 215 SBIT(PTI,               0xF8,   7); // Timer I Interrupt Priority
 216
 217 /* Bitmasks for SFRs */
 218
 219 /* AUXR1 bits  */
 220 #define DPS     0x01
 221 #define SRST    0x08
 222 #define LPEP    0x10
 223 #define BOI     0x20
 224 #define BOD     0x40
 225 #define KBF     0x80
 226
 227 /* CMP1 bits   */
 228 #define CMF1    0x01
 229 #define CO1     0x02
 230 #define OE1     0x04
 231 #define CN1     0x08
 232 #define CP1     0x10
 233 #define CE1     0x20
 234
 235 /* CMP2 bits   */
 236 #define CMF2    0x01
 237 #define CO2     0x02
 238 #define OE2     0x04
 239 #define CN2     0x08
 240 #define CP2     0x10
 241 #define CE2     0x20
 242
 243 /* I2DAT bits  */
 244 #define RDAT    0x80
 245 #define XDAT    0x80
 246
 247 /* IP1H bits   */
 248 #define PI2H    0x01
 249 #define PKBH    0x02
 250 #define PC2H    0x04
 251 #define PC1H    0x20
 252 #define PTIH    0x80
 253
 254 /* PCON bits   */
 255 #define IDL     0x01
 256 #define PD      0x02
 257 #define GF0     0x04
 258 #define GF1     0x08
 259 #define POF     0x10
 260 #define BOF     0x20
 261 #define SMOD0   0x40
 262 #define SMOD1   0x80
 263
 264 /* P2M1 bits   */
 265 #define ENT0    0x04
 266 #define ENT1    0x08
 267 #define ENTCLK  0x10
 268 #define P0S     0x20
 269 #define P1S     0x40
 270 #define P2S     0x80
 271
 272 /* TMOD bits */
 273 #define M0_0    0x01
 274 #define M1_0    0x02
 275 #define C_T0    0x04
 276 #define GATE0   0x08
 277 #define M0_1    0x10
 278 #define M1_1    0x20
 279 #define C_T1    0x40
 280 #define GATE1   0x80
 281
 282 /* WDCON bits */
 283 #define WDS0    0x01
 284 #define WDS1    0x02
 285 #define WDS2    0x04
 286 #define WDCLK   0x08
 287 #define WDRUN   0x10
 288 #define WDOVF   0x20
 289
 290
 291 /*  Masks for I2CFG bits */
 292 #define BTIR    0x10       // Mask for TIRUN bit.
 293 #define BMRQ    0x40       // Mask for MASTRQ bit.
 294 #define BSLV    0x80       // Mask for SLAVEN bit.
 295
 296
 297 /* Masks for I2CON bits */
 298 #define BCXA    0x80       // Mask for CXA bit.
 299 #define BIDLE   0x40       // Mask for IDLE bit.
 300 #define BCDR    0x20       // Mask for CDR bit.
 301 #define BCARL   0x10       // Mask for CARL bit.
 302 #define BCSTR   0x08       // Mask for CSTR bit.
 303 #define BCSTP   0x04       // Mask for CSTP bit.
 304 #define BXSTR   0x02       // Mask for XSTR bit.
 305 #define BXSTP   0x01       // Mask for XSTP bit.
 306
 307
 308 #endif