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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / include / mcs51 / regc515c.h
blob5277c9a2e65218cefde5799e044dc40e10bf4753
1 /*---------------------------------------------------------------------------
2 regc515c.h - This file contains definitions for the builtin CAN-Bus
3 Controller of the Siemens c515c controller
4
5 Copyright (C) 2005, Maarten Brock, sourceforge.brock@dse.nl
6
7 This library is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published by the
9 Free Software Foundation; either version 2, or (at your option) any
10 later version.
11
12 This library is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this library; see the file COPYING. If not, write to the
19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
20 MA 02110-1301, USA.
21
22 As a special exception, if you link this library with other files,
23 some of which are compiled with SDCC, to produce an executable,
24 this library does not by itself cause the resulting executable to
25 be covered by the GNU General Public License. This exception does
26 not however invalidate any other reasons why the executable file
27 might be covered by the GNU General Public License.
28 -------------------------------------------------------------------------*/
29
30 #ifndef _REGC515C_H
31 #define _REGC515C_H
32
33 #include <compiler.h>
34
35 /* define CPU_CLK_10MHZ or CPU_CLK_8MHZ to select the right values for */
36 /* the bit timing registers */
37
38 #define CPU_CLK_10MHZ
39
40 /* address of can controller in xmem */
41 #define CAN_CTRL 0xf700
42
43 /* size of message buffer including 1 dummy byte at end */
44 #define CAN_MSG_SZ 0x10
45
46 /* register offset definitions */
47 #define CR 0
48 #define SR 1
49 #define IR 2
50
51 #define BT_0 4
52 #define BT_1 5
53 #define GMS_0 6
54 #define GMS_1 7
55 #define GME_0 8
56 #define GME_1 9
57 #define GME_2 0xa
58 #define GME_3 0xb
59 #define MSG15MSK_0 0xc
60 #define MSG15MSK_1 0xd
61 #define MSG15MSK_2 0xe
62 #define MSG15MSK_3 0xf
63
64 /* register offsets in message buffer */
65 #define MCR_0 0
66 #define MCR_1 1
67 #define ARB_0 2
68 #define ARB_1 3
69 #define ARB_2 4
70 #define ARB_3 5
71 #define MCFG 6
72 /* beginning of message data */
73 #define DATA 7
74
75 /* bits in cntr_x registers */
76 #define MSGVAL 0x80
77 #define TXIE 0x20
78 #define RXIE 0x8
79 #define INTPND 0x2
80 #define RMTPND 0x80
81 #define TXRQST 0x20
82 #define MSGLST 0x8
83 #define CPUUPD 0x8
84 #define NEWDAT 0x2
85
86 /* macros for setting and resetting above bits, see Siemens documentation */
87 #define MCR_BIT_SET(p,x) ((p) = (0xff & ~((x) >> 1)))
88 #define MCR_BIT_RES(p,x) ((p) = (0xff & ~(x)))
89
90 /* direction = transmit in mcfg */
91 #define DIR_TRANSMIT 0x8
92
93 /* constants for bit timing registers */
94 /* 8 MHZ */
95 #ifdef CPU_CLK_8MHZ
96 #define BT_0_125K 0x3
97 #define BT_1_125K 0x1c
98 #define BT_0_250K 0x1
99 #define BT_1_250K 0x1c
100 #define BT_0_500K 0x0
101 #define BT_1_500K 0x1c
102 #define BT_0_1M 0x0
103 #define BT_1_1M 0x14
104 #endif
105 /* dito, 10 MHZ */
106 #ifdef CPU_CLK_10MHZ
107 #define BT_0_125K 0x3
108 #define BT_1_125K 0x1c
109 #define BT_0_250K 0x1
110 #define BT_1_250K 0x1c
111 #define BT_0_500K 0x0
112 #define BT_1_500K 0x2f
113 #define BT_0_1M 0x0
114 #define BT_1_1M 0x25
115 #endif
116
117 /* Control register bits */
118
119 #define CINIT 0x1
120 #define IE 0x2
121 #define SIE 0x4
122 #define EIE 0x8
123
124 #define CCE 0x40
125
126 /* status register bits */
127 #define LEC0 0x1
128 #define LEC1 0x2
129 #define LEC2 0x4
130 #define TXOK 0x8
131 #define RXOK 0x10
132 #define WAKE 0x20
133 #define WARN 0x40
134 #define BOFF 0x80
135
136
137 typedef struct can_msg
138 {
139 unsigned char mcr_0;
140 unsigned char mcr_1;
141 unsigned char arb_0;
142 unsigned char arb_1;
143 unsigned char arb_2;
144 unsigned char arb_3;
145 unsigned char mcfg;
146 unsigned char data_bytes[8];
147 unsigned char dummy;
148 } *can_msgp;
149
150 __xdata __at CAN_CTRL struct
151 {
152 unsigned char cr;
153 unsigned char sr;
154 unsigned char ir;
155 unsigned char res0;
156 unsigned char bt_0;
157 unsigned char bt_1;
158 unsigned char gms_0;
159 unsigned char gms_1;
160 unsigned char gme_0;
161 unsigned char gme_1;
162 unsigned char gme_2;
163 unsigned char gme_3;
164 unsigned char msg15msk_0;
165 unsigned char msg15msk_1;
166 unsigned char msg15msk_2;
167 unsigned char msg15msk_3;
168 struct can_msg msgbufs[15];
169 } can_ctrl;
170
171 /* Byte registers in numerical order */
172
173 SFR(P0, 0x80);
174 SFR(SP, 0x81);
175 SFR(DPL, 0x82);
176 SFR(DPH, 0x83);
177 SFR(WDTREL, 0x86);
178 SFR(PCON, 0x87);
179 SFR(TCON, 0x88);
180 SFR(PCON1, 0x88);
181 SFR(TMOD, 0x89);
182 SFR(TL0, 0x8A);
183 SFR(TL1, 0x8B);
184 SFR(TH0, 0x8C);
185 SFR(TH1, 0x8D);
186 SFR(P1, 0x90);
187 SFR(XPAGE, 0x91);
188 SFR(DPSEL, 0x92);
189 SFR(SSCCON, 0x93);
190 SFR(STB, 0x94);
191 SFR(SRB, 0x95);
192 SFR(SSCMOD, 0x96);
193 SFR(SCON, 0x98);
194 SFR(SBUF, 0x99);
195 SFR(IEN2, 0x9A);
196 SFR(P2, 0xA0);
197 SFR(IEN0, 0xA8);
198 SFR(IP0, 0xA9);
199 SFR(SRELL, 0xAA);
200 SFR(SCF, 0xAB);
201 SFR(SCIEN, 0xAC);
202 SFR(P3, 0xB0);
203 SFR(SYSCON, 0xB1);
204 SFR(IEN1, 0xB8);
205 SFR(IP1, 0xB9);
206 SFR(SRELH, 0xBA);
207 SFR(IRCON, 0xC0);
208 SFR(CCEN, 0xC1);
209 SFR(CCL1, 0xC2);
210 SFR(CCH1, 0xC3);
211 SFR(CCL2, 0xC4);
212 SFR(CCH2, 0xC5);
213 SFR(CCL3, 0xC6);
214 SFR(CCH3, 0xC7);
215 SFR(T2CON, 0xC8);
216 SFR(CRCL, 0xCA);
217 SFR(CRCH, 0xCB);
218 SFR(TL2, 0xCC);
219 SFR(TH2, 0xCD);
220 SFR(PSW, 0xD0);
221 SFR(ADCON0, 0xD8);
222 SFR(ADDATH, 0xD9);
223 SFR(ADDATL, 0xDA);
224 SFR(P6, 0xDB);
225 SFR(ADCON1, 0xDC);
226 SFR(ACC, 0xE0);
227 SFR(P4, 0xE8);
228 SFR(B, 0xF0);
229 SFR(P5, 0xF8);
230 SFR(DIR5, 0xF8);
231 SFR(P7, 0xFA);
232
233
234 /* defining bits in SFR P0 */
235 SBIT(P0_0, 0x80, 0);
236 SBIT(P0_1, 0x80, 1);
237 SBIT(P0_2, 0x80, 2);
238 SBIT(P0_3, 0x80, 3);
239 SBIT(P0_4, 0x80, 4);
240 SBIT(P0_5, 0x80, 5);
241 SBIT(P0_6, 0x80, 6);
242 SBIT(P0_7, 0x80, 7);
243
244
245
246 /* defining bits in SFR PCON1 */
247 SBIT(IT0, 0x88, 0);
248 SBIT(IE0, 0x88, 1);
249 SBIT(IT1, 0x88, 2);
250 SBIT(IE1, 0x88, 3);
251 SBIT(TR0, 0x88, 4);
252 SBIT(TF0, 0x88, 5);
253 SBIT(TR1, 0x88, 6);
254 SBIT(TF1, 0x88, 7);
255 SBIT(EWPD, 0x88, 7);
256
257
258
259 /* defining bits in SFR P1 */
260 SBIT(P1_0, 0x90, 0);
261 SBIT(INT3, 0x90, 0);
262 SBIT(P1_1, 0x90, 1);
263 SBIT(INT4, 0x90, 1);
264 SBIT(P1_2, 0x90, 2);
265 SBIT(INT5, 0x90, 2);
266 SBIT(P1_3, 0x90, 3);
267 SBIT(INT6, 0x90, 3);
268 SBIT(P1_4, 0x90, 4);
269 SBIT(INT2, 0x90, 4);
270 SBIT(P1_5, 0x90, 5);
271 SBIT(T2EX, 0x90, 5);
272 SBIT(P1_6, 0x90, 6);
273 SBIT(CLKOUT, 0x90, 6);
274 SBIT(P1_7, 0x90, 7);
275 SBIT(T2, 0x90, 7);
276
277
278
279 /* defining bits in SFR SCON */
280 SBIT(RI, 0x98, 0);
281 SBIT(TI, 0x98, 1);
282 SBIT(RB8, 0x98, 2);
283 SBIT(TB8, 0x98, 3);
284 SBIT(REN, 0x98, 4);
285 SBIT(SM2, 0x98, 5);
286 SBIT(SM1, 0x98, 6);
287 SBIT(SM0, 0x98, 7);
288
289
290
291 /* defining bits in SFR P2 */
292 SBIT(P2_0, 0xa0, 0);
293 SBIT(P2_1, 0xa0, 1);
294 SBIT(P2_2, 0xa0, 2);
295 SBIT(P2_3, 0xa0, 3);
296 SBIT(P2_4, 0xa0, 4);
297 SBIT(P2_5, 0xa0, 5);
298 SBIT(P2_6, 0xa0, 6);
299 SBIT(P2_7, 0xa0, 7);
300
301
302
303 /* defining bits in SFR IEN0 */
304 SBIT(EX0, 0xa8, 0);
305 SBIT(ET0, 0xa8, 1);
306 SBIT(EX1, 0xa8, 2);
307 SBIT(ET1, 0xa8, 3);
308 SBIT(ES, 0xa8, 4);
309 SBIT(ET2, 0xa8, 5);
310 SBIT(WDT, 0xa8, 6);
311 SBIT(EA, 0xa8, 7);
312
313
314
315 /* defining bits in SFR P3 */
316 SBIT(P3_0, 0xb0, 0);
317 SBIT(RXD, 0xb0, 0);
318 SBIT(P3_1, 0xb0, 1);
319 SBIT(TXD, 0xb0, 1);
320 SBIT(P3_2, 0xb0, 2);
321 SBIT(INT0, 0xb0, 2);
322 SBIT(P3_3, 0xb0, 3);
323 SBIT(INT1, 0xb0, 3);
324 SBIT(P3_4, 0xb0, 4);
325 SBIT(T0, 0xb0, 4);
326 SBIT(P3_5, 0xb0, 5);
327 SBIT(T1, 0xb0, 5);
328 SBIT(P3_6, 0xb0, 6);
329 SBIT(WR, 0xb0, 6);
330 SBIT(P3_7, 0xb0, 7);
331 SBIT(RD, 0xb0, 7);
332
333
334
335 /* defining bits in SFR IEN1 */
336 SBIT(EADC, 0xb8, 0);
337 SBIT(EX2, 0xb8, 1);
338 SBIT(EX3, 0xb8, 2);
339 SBIT(EX4, 0xb8, 3);
340 SBIT(EX5, 0xb8, 4);
341 SBIT(EX6, 0xb8, 5);
342 SBIT(SWDT, 0xb8, 6);
343 SBIT(EXEN2, 0xb8, 7);
344
345
346
347 /* defining bits in SFR IRCON */
348 SBIT(IADC, 0xc0, 0);
349 SBIT(IEX2, 0xc0, 1);
350 SBIT(IEX3, 0xc0, 2);
351 SBIT(IEX4, 0xc0, 3);
352 SBIT(IEX5, 0xc0, 4);
353 SBIT(IEX6, 0xc0, 5);
354 SBIT(TF2, 0xc0, 6);
355 SBIT(EXF2, 0xc0, 7);
356
357
358
359 /* defining bits in SFR T2CON */
360 SBIT(T2I0, 0xc8, 0);
361 SBIT(T2I1, 0xc8, 1);
362 SBIT(T2CM, 0xc8, 2);
363 SBIT(T2R0, 0xc8, 3);
364 SBIT(T2R1, 0xc8, 4);
365 SBIT(I2FR, 0xc8, 5);
366 SBIT(I3FR, 0xc8, 6);
367 SBIT(T2PS, 0xc8, 7);
368
369
370
371 /* defining bits in SFR PSW */
372 SBIT(P, 0xd0, 0);
373 SBIT(F1, 0xd0, 1);
374 SBIT(OV, 0xd0, 2);
375 SBIT(RS0, 0xd0, 3);
376 SBIT(RS1, 0xd0, 4);
377 SBIT(F0, 0xd0, 5);
378 SBIT(AC, 0xd0, 6);
379 SBIT(CY, 0xd0, 7);
380
381
382
383 /* defining bits in SFR ADCON0 */
384 SBIT(MX0, 0xd8, 0);
385 SBIT(MX1, 0xd8, 1);
386 SBIT(MX2, 0xd8, 2);
387 SBIT(ADM, 0xd8, 3);
388 SBIT(BSY, 0xd8, 4);
389 SBIT(ADEX, 0xd8, 5);
390 SBIT(CLK, 0xd8, 6);
391 SBIT(BD, 0xd8, 7);
392
393
394
395 /* defining bits in SFR ACC */
396 SBIT(ACC_0, 0xe0, 0);
397 SBIT(ACC_1, 0xe0, 1);
398 SBIT(ACC_2, 0xe0, 2);
399 SBIT(ACC_3, 0xe0, 3);
400 SBIT(ACC_4, 0xe0, 4);
401 SBIT(ACC_5, 0xe0, 5);
402 SBIT(ACC_6, 0xe0, 6);
403 SBIT(ACC_7, 0xe0, 7);
404
405
406
407 /* defining bits in SFR P4 */
408 SBIT(P4_0, 0xe8, 0);
409 SBIT(ADST, 0xe8, 0);
410 SBIT(P4_1, 0xe8, 1);
411 SBIT(SCLK, 0xe8, 1);
412 SBIT(P4_2, 0xe8, 2);
413 SBIT(SRI, 0xe8, 2);
414 SBIT(P4_3, 0xe8, 3);
415 SBIT(STO, 0xe8, 3);
416 SBIT(P4_4, 0xe8, 4);
417 SBIT(SLS, 0xe8, 4);
418 SBIT(P4_5, 0xe8, 5);
419 SBIT(INT8, 0xe8, 5);
420 SBIT(P4_6, 0xe8, 6);
421 SBIT(TXDC, 0xe8, 6);
422 SBIT(P4_7, 0xe8, 7);
423 SBIT(RXDC, 0xe8, 7);
424
425
426
427 /* defining bits in SFR B */
428 SBIT(B_0, 0xf0, 0);
429 SBIT(B_1, 0xf0, 1);
430 SBIT(B_2, 0xf0, 2);
431 SBIT(B_3, 0xf0, 3);
432 SBIT(B_4, 0xf0, 4);
433 SBIT(B_5, 0xf0, 5);
434 SBIT(B_6, 0xf0, 6);
435 SBIT(B_7, 0xf0, 7);
436
437
438
439 /* defining bits in SFR DIR5 */
440 SBIT(P5_0, 0xf8, 0);
441 SBIT(P5_1, 0xf8, 9);
442 SBIT(P5_2, 0xf8, 2);
443 SBIT(P5_3, 0xf8, 3);
444 SBIT(P5_4, 0xf8, 4);
445 SBIT(P5_5, 0xf8, 5);
446 SBIT(P5_6, 0xf8, 6);
447 SBIT(P5_7, 0xf8, 7);
448 SBIT(DIR5_0, 0xf8, 0);
449 SBIT(DIR5_1, 0xf8, 1);
450 SBIT(DIR5_2, 0xf8, 2);
451 SBIT(DIR5_3, 0xf8, 3);
452 SBIT(DIR5_4, 0xf8, 4);
453 SBIT(DIR5_5, 0xf8, 5);
454 SBIT(DIR5_6, 0xf8, 6);
455 SBIT(DIR5_7, 0xf8, 7);
456
457 #endif /* _REGC515C_H */
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