sdcc/device/include/mcs51/stc89.h

   1 /*-------------------------------------------------------------------------
   2    stc89c.h - Register Declarations for STC89Cxx Series
   3    Based on stc12.h
   4
   5    Copyright (c) 2012, intron@intron.ac
   6    Copyright (c) 2020, flameeyes@flameeyes.com
   7
   8    This library is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published by the
  10    Free Software Foundation; either version 2, or (at your option) any
  11    later version.
  12
  13    This library is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this library; see the file COPYING. If not, write to the
  20    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  21    MA 02110-1301, USA.
  22
  23    As a special exception, if you link this library with other files,
  24    some of which are compiled with SDCC, to produce an executable,
  25    this library does not by itself cause the resulting executable to
  26    be covered by the GNU General Public License. This exception does
  27    not however invalidate any other reasons why the executable file
  28    might be covered by the GNU General Public License.
  29 -------------------------------------------------------------------------*/
  30
  31 /*
  32    Brief:
  33
  34        STC89Cxx/STC89LExx series are 8051-compatible MCU's. The "official"
  35    websites are http://www.stcmcu.com/ (In Chinese Han only) and
  36    http://www.stcmicro.com/ (in English), and datasheets in Chinese Han and
  37    English can be downloaded there.
  38
  39    Reference:
  40
  41    1.
  42    1. The "official" C header file (written for another C51 compiler):
  43         http://www.stcmcu.com/datasheet/stc/STC-AD-PDF/STC_NEW_8051.H
  44    2. Datasheets for STC89(C/LE)xx series:
  45       English:
  46         http://www.stcmicro.com/datasheet/STC89C51RC-en.pdf
  47  */
  48
  49 #ifndef _STC89_H_
  50 #define _STC89_H_
  51
  52 #include <8051.h>
  53 #include <compiler.h>
  54
  55 #ifdef REG8051_H
  56 #undef REG8051_H
  57 #endif
  58
  59 /*
  60  * Auxiliary Register
  61  *   Bit Mapping: - - - - - - EXTRAM ALEOFF
  62  *   Reset Value: xxxx,xx00
  63  */
  64 SFR(AUXR, 0x8E);
  65
  66 /*
  67  * Auxiliary Register 1
  68  *   Bit Mapping: - - - - - - GF2 - - DPS
  69  *   Reset Value: 0xxx,0xx0
  70  */
  71 SFR(AUXR1, 0xA2);
  72
  73 /* Slave Address for Serial Communication
  74  *   Reset Value: 0000,0000
  75  */
  76 SFR(SADDR, 0xA9);
  77
  78 /*
  79  * Higher bits for Interrupt Priority
  80  *   Bit Mapping: PX3H PX2H PT2H PSH PT1H PX1H PT0H PX0H
  81  *   Reset Value: 0000,0000
  82  */
  83 SFR(IPH, 0xB7);
  84
  85 /* Slave Address Mask for Serial Communication
  86  *   Reset Value: 0000,0000
  87  */
  88 SFR(SADEN, 0xB9);
  89
  90 /* Auxiliary Input Control
  91  *   Bit Mapping: PX3 EX3 IE3 IT3 PX2 EX2 HE2 IT2
  92  *   Reset Value: 0000,0000
  93  */
  94 SFR(XICON, 0xC0);
  95
  96 /* Timer/Counter 2 registers are compatible with AT89x52 */
  97
  98 /* Timer/Counter 2 Control
  99  *   Bit Mapping: TF2 EXF2 RCLK TCLK EXEN2 TR2 C/!T2 CP/!RL2
 100  *   Reset Value: 0000,0000
 101  */
 102 SFR(T2CON, 0xC8);
 103
 104 /* Timer/Counter 2 Mode
 105  *   Bit Mapping: - - - - - - T2OE DCEN
 106  *   Reset Value: xxxx,xx00
 107  */
 108 SFR(T2MOD, 0xC9);
 109
 110 /* Timer/Counter 2 Reload/Capture Low Byte
 111  *   Reset Value: 0000,0000
 112  */
 113 SFR(RCAP2L, 0xCA);
 114
 115 /* Timer/Counter 2 Reload/Capture High Byte
 116  *   Reset Value: 0000,0000
 117  */
 118 SFR(RCAP2H, 0xCB);
 119
 120 /* Timer/Counter 2 Low Byte
 121  *   Reset Value: 0000,0000
 122  */
 123 SFR(TL2, 0xCC);
 124
 125 /* Timer/Counter 2 High Byte
 126  *   Reset Value: 0000,0000
 127  */
 128 SFR(TH2, 0xCD);
 129
 130 /*
 131  * Watchdog Timer Control Register
 132  *   Bit Mapping: - - EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0
 133  *   Reset Value: xx00,0000
 134  */
 135 SFR(WDT_CONTR, 0xE1);
 136
 137 /* In-Application-Programming Data Register
 138  *   Reset Value: 1111,1111
 139  */
 140 SFR(IAP_DATA, 0xE2);
 141
 142 /* In-Application-Programming Address Registers
 143  *   Reset Values: 0000, 0000
 144  *                 0000, 0000
 145  */
 146 SFR(IAP_ADDRH, 0xE3); /* Higher 8 bits */
 147 SFR(IAP_ADDRL, 0xE4); /* Lower 8 bits */
 148
 149 /*
 150  * In-Application-Programming Address Registers
 151  *   Bit Mapping: - - - - - MS2 MS1 MS0
 152  *   Reset Value: xxxx,x000
 153  */
 154 SFR(IAP_CMD, 0xE5);
 155
 156 /* In-Application-Programming Trigger Registers
 157  *   Reset Value: xxxx,xxxx
 158  */
 159 SFR(IAP_TRIG, 0xE6);
 160
 161 /*
 162  * In-Application-Programming Control Register
 163  *   Bit Mapping: ISPEN SWBS SWRST - - WT2 WT1 WT0
 164  *   Reset Value: 000x,x000
 165  */
 166 SFR(IAP_CONTR, 0xE7);
 167
 168 /*
 169  * One Extended GPIO Port: P4
 170  * - For PLCC-44 and LQFP-44 packages, only lower 4 bits of P4 are available.
 171  */
 172 SFR(P4, 0xE8);
 173     SBIT(P4_0, 0xC0, 0);
 174     SBIT(P4_1, 0xC0, 1);
 175     SBIT(P4_2, 0xC0, 2);
 176     SBIT(P4_3, 0xC0, 3);
 177
 178 #endif /* _STC89_H_ */
 179