sdcc/device/include/mcs51/uPSD32xx.h

   1 /*-------------------------------------------------------------------------
   2    uPSD23xx.h - Register Declarations for ST's uPSD325x
   3    Based upon  uPSD33xx.h from SDCC compiler set, and
   4    uPSD3254/3253 datasheet - November 2004
   5    Register Declarations for ST's uPSD32xx "Fast 8032 MCU with Programmable Logic"
   6
   7    Copyright (C) 2009, GHJ Morsink
   8    Original 33xx file Written By -  Jesus Calvino-Fraga / jesusc at ece.ubc.ca (May 2007)
   9
  10    This library is free software; you can redistribute it and/or modify it
  11    under the terms of the GNU General Public License as published by the
  12    Free Software Foundation; either version 2, or (at your option) any
  13    later version.
  14
  15    This library is distributed in the hope that it will be useful,
  16    but WITHOUT ANY WARRANTY; without even the implied warranty of
  17    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18    GNU General Public License for more details.
  19
  20    You should have received a copy of the GNU General Public License
  21    along with this library; see the file COPYING. If not, write to the
  22    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  23    MA 02110-1301, USA.
  24
  25    As a special exception, if you link this library with other files,
  26    some of which are compiled with SDCC, to produce an executable,
  27    this library does not by itself cause the resulting executable to
  28    be covered by the GNU General Public License. This exception does
  29    not however invalidate any other reasons why the executable file
  30    might be covered by the GNU General Public License.
  31 -------------------------------------------------------------------------*/
  32
  33 #ifndef REG_UPSD32XX_H
  34 #define REG_UPSD32XX_H
  35
  36 #include <compiler.h>
  37
  38 #ifndef PSD_CSIOP
  39 #define PSD_CSIOP 0x00                /* for reference for PSD registers as default (page 99 datasheet) */
  40                                       /* This must be set in PSDSoft "Define PSD pin/node Functions"
  41                                          Step3 'Next', tab "Chip Select Equations"  */
  42 #endif
  43
  44 //Interrupt vector numbers (see table 24 on datasheet page 39)
  45 #define EXT0_INTERRUPT   ((0x03-3)/8)
  46 #define TIMER0_INTERRUPT ((0x0B-3)/8)
  47 #define EXT1_INTERRUPT   ((0x13-3)/8)
  48 #define TIMER1_INTERRUPT ((0x1B-3)/8)
  49 #define UART0_INTERRUPT  ((0x23-3)/8)
  50 #define TIMER2_INTERRUPT ((0x2B-3)/8)
  51 #define TX2_INTERRUPT    ((0x2B-3)/8)
  52 #define USB_INTERRUPT    ((0x33-3)/8)
  53 #define DDC_INTERRUPT    ((0x3B-3)/8)
  54 #define I2C_INTERRUPT    ((0x43-3)/8)
  55 #define UART1_INTERRUPT  ((0x4B-3)/8)
  56
  57
  58 SFR(P0, 0x80); // Port 0
  59     SBIT(P0_0, 0x80, 0); // Port 0 bit 0.
  60     SBIT(P0_1, 0x80, 1); // Port 0 bit 1.
  61     SBIT(P0_2, 0x80, 2); // Port 0 bit 2.
  62     SBIT(P0_3, 0x80, 3); // Port 0 bit 3.
  63     SBIT(P0_4, 0x80, 4); // Port 0 bit 4.
  64     SBIT(P0_5, 0x80, 5); // Port 0 bit 5.
  65     SBIT(P0_6, 0x80, 6); // Port 0 bit 6.
  66     SBIT(P0_7, 0x80, 7); // Port 0 bit 7.
  67
  68
  69 SFR(SP,   0x81); // Stack Pointer.
  70 SFR(DPL,  0x82); // Data Pointer Low.
  71 SFR(DPH,  0x83); // Data Pointer High.
  72
  73 SFR(DPTC, 0x85); // Data Pointer Control Register.
  74 SFR(DPS,  0x85); // Data Pointer Control Register alias for SDCC
  75     #define AT 0x40 //0:Manually Select Data Pointer / 1:Auto Toggle between DPTR0 and DPTR1
  76     #define DPSE0 0x01 // 0:DPTR0 Selected for use as DPTR / 1:DPTR1 Selected for use as DPTR
  77
  78 SFR(PCON, 0x87); // Power Control.
  79     #define SMOD0  0x80 //Baud Rate Double Bit (UART0)
  80     #define SMOD1  0x40 //Baud Rate Double Bit (UART1)
  81     #define POR    0x10 //Only a power-on reset sets this bit (cold reset).
  82     #define RCLK1  0x08 //Receive Clock Flag (UART1)
  83     #define TCLK1  0x04 //Transmit Clock Flag (UART1)
  84     #define PD     0x02 //Power-Down Mode Enable.
  85     #define IDL    0x01 //Idle Mode Enable.
  86
  87 SFR(TCON, 0x88); // Timer/Counter Control.
  88     SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
  89     SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
  90     SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
  91     SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
  92     SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
  93     SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
  94     SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
  95     SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
  96
  97 SFR(TMOD, 0x89); // Timer/Counter Mode Control.
  98     #define GATE1 0x80 // External enable for timer 1.
  99     #define C_T1  0x40 // Timer or counter select for timer 1.
 100     #define M1_1  0x20 // Operation mode bit 1 for timer 1.
 101     #define M0_1  0x10 // Operation mode bit 0 for timer 1.
 102     #define GATE0 0x08 // External enable for timer 0.
 103     #define C_T0  0x04 // Timer or counter select for timer 0.
 104     #define M1_0  0x02 // Operation mode bit 1 for timer 0.
 105     #define M0_0  0x01 // Operation mode bit 0 for timer 0.
 106
 107 SFR(TL0, 0x8A); // Timer 0 LSB.
 108 SFR(TL1, 0x8B); // Timer 1 LSB.
 109 SFR(TH0, 0x8C); // Timer 0 MSB.
 110 SFR(TH1, 0x8D); // Timer 1 MSB.
 111
 112 SFR(P1, 0x90); // Port 1
 113     SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
 114     SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
 115     SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
 116     SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
 117     SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
 118     SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
 119     SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
 120     SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
 121     //Alternate names (from figure 3)
 122     SBIT(T2,     0x90, 0); //Input to Timer/Counter 2.
 123     SBIT(T2X,    0x90, 1); //Capture/reload trigger for Counter 2.
 124     SBIT(RXD1,   0x90, 2);
 125     SBIT(TXD1,   0x90, 3);
 126     SBIT(SPICLK, 0x90, 4);
 127     SBIT(SPIRXD, 0x90, 5);
 128     SBIT(SPITXD, 0x90, 6);
 129     SBIT(SPISEL, 0x90, 7);
 130
 131 SFR(P1SFS, 0x91); // Port 1 Special Function Select Register
 132     #define P1SF7 0x80
 133     #define P1SF6 0x40
 134     #define P1SF5 0x20
 135     #define P1SF4 0x10
 136     #define P1SF3 0x08
 137     #define P1SF2 0x04
 138     #define P1SF1 0x02
 139     #define P1SF0 0x01
 140
 141 SFR(P3SFS, 0x93); // Port 3 Special Function Select Register
 142     #define P3SF7 0x80
 143     #define P3SF6 0x40
 144     #define P3SF5 0x20
 145     #define P3SF4 0x10
 146     #define P3SF3 0x08
 147     #define P3SF2 0x04
 148     #define P3SF1 0x02
 149     #define P3SF0 0x01
 150
 151 SFR(P4SFS, 0x94); //Port 4 Special Function Select Register.
 152     #define P4SF7 0x80
 153     #define P4SF6 0x40
 154     #define P4SF5 0x20
 155     #define P4SF4 0x10
 156     #define P4SF3 0x08
 157     #define P4SF2 0x04
 158     #define P4SF1 0x02
 159     #define P4SF0 0x01
 160
 161 SFR(ASCL, 0x95); // ADC pre-scaler
 162     #define ADCCE  0x08 // ADC Conversion Reference Clock Enable.
 163     //ADC Reference Clock PreScaler. Only three Prescaler values are allowed:
 164     #define ADCPS2 0x02 // Resulting ADC clock is fOSC.
 165     #define ADCPS1 0x01 // Resulting ADC clock is fOSC/2.
 166     #define ADCPS0 0x00 // Resulting ADC clock is fOSC/4.
 167
 168 SFR(ADAT, 0x96); // A/D result register (bits 0 to 7).
 169 SFR(ACON, 0x97); // A/D control register.
 170     #define AINTF  0x80 // ADC Interrupt flag. This bit must be cleared with software.
 171     #define AINTEN 0x40 // ADC Interrupt Enable.
 172     #define ADEN   0x20 // ADC Enable Bit.
 173     #define ADS2   0x10 // Analog channel Select bit 3.
 174     #define ADS1   0x08 // Analog channel Select bit 2.
 175     #define ADS0   0x04 // Analog channel Select bit 1.
 176     #define ADST   0x02 // ADC Start Bit.
 177     #define ADSF   0x01 // ADC Status Bit.
 178
 179 SFR(SCON, 0x98); // For compatibity with legacy code
 180 SFR(SCON0, 0x98); // Serial Port UART0 Control Register
 181     SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
 182     SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
 183     SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
 184     SBIT(REN, 0x98, 4); // Enables serial reception.
 185     SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
 186     SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
 187     SBIT(TI,  0x98, 1); // Transmit interrupt flag.
 188     SBIT(RI,  0x98, 0); // Receive interrupt flag.
 189
 190 SFR(SBUF, 0x99);  // For compatibity with legacy code.
 191 SFR(SBUF0, 0x99); // Serial Port UART0 Data Buffer.
 192
 193 SFR(SCON2, 0x9A); // Serial Port Control.
 194 /* These bits are not bit-addressable */
 195     #define SM01  0x80  // Serial Port Mode Bit 0.
 196     #define SM11  0x40  // Serial Port Mode Bit 1.
 197     #define SM21  0x20  // Serial Port Mode Bit 2.
 198     #define REN1  0x10  // Enables serial reception.
 199     #define TB81  0x08  // The 9th data bit that will be transmitted in Modes 2 and 3.
 200     #define RB81  0x04  // In Modes 2 and 3, the 9th data bit that was received.
 201     #define TI1   0x02  // Transmit interrupt flag.
 202     #define RI1   0x01  // Receive interrupt flag.
 203
 204 SFR(SBUF2, 0x9B);   // Data buffer for UART1.
 205
 206 SFR(P2, 0xA0); // Port 2
 207     SBIT(P2_0, 0xA0, 0); // Port 2 bit 0.
 208     SBIT(P2_1, 0xA0, 1); // Port 2 bit 1.
 209     SBIT(P2_2, 0xA0, 2); // Port 2 bit 2.
 210     SBIT(P2_3, 0xA0, 3); // Port 2 bit 3.
 211     SBIT(P2_4, 0xA0, 4); // Port 2 bit 4.
 212     SBIT(P2_5, 0xA0, 5); // Port 2 bit 5.
 213     SBIT(P2_6, 0xA0, 6); // Port 2 bit 6.
 214     SBIT(P2_7, 0xA0, 7); // Port 2 bit 7.
 215
 216 SFR(PWMCON, 0xA1);      // PWM control register for 4+1 channels
 217     #define PWML   0x80 // Polarity 0-3
 218     #define PWMP   0x40 // Polarity 4
 219     #define PWME   0x20 // Enable Bit. (0 = disabled)
 220     #define CFG4   0x10 // Output4: 0=open drain, 1=pushpull
 221     #define CFG3   0x08 // Output3: 0=open drain, 1=pushpull
 222     #define CFG2   0x04 // Output2: 0=open drain, 1=pushpull
 223     #define CFG1   0x02 // Output1: 0=open drain, 1=pushpull
 224     #define CFG0   0x01 // Output0: 0=open drain, 1=pushpull
 225
 226
 227 SFR(PWM0, 0xA2); // PWM0 counter.
 228 SFR(PWM1, 0xA3); //  counter.
 229 SFR(PWM2, 0xA4); //
 230 SFR(PWM3, 0xA5); //
 231 SFR(PWM4P, 0xAA); // PWM4 Period
 232 SFR(PWM4W, 0xAB); // PWM4 Width
 233 SFR(PSCL0L, 0xB1); // The low 8 bits of PSCL 0 16-bit counter. (Prescaler for PWM)
 234 SFR(PSCL0H, 0xB2); // The high 8 bits of PSCL 0 16-bit counter.
 235 SFR(PSCL1L, 0xB3); // The low 8 bits of PSCL 1 16-bit counter.
 236 SFR(PSCL1H, 0xB4); // The high 8 bits of PSCL 1 16-bit counter.
 237
 238
 239 SFR(IEA, 0xA7); // Interrupt Enable Addition Register.
 240     #define EADC 0x80 // Enable ADC Interrupt.
 241     #define ESPI 0x40 // Enable SPI Interrupt.
 242     #define EPCA 0x20 // Enable Programmable Counter Array Interrupt.
 243     #define ES1  0x10 // Enable UART1 Interrupt.
 244     #define EI2C 0x02 // Enable I2C Interrupt.
 245
 246 SFR(IE, 0xA8); // Interrupt Enable Register.
 247     SBIT(EA,  0xA8, 7); // Global disable bit.
 248     SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt.
 249     SBIT(ES0, 0xA8, 4); // Enable UART0 Interrupt.
 250     SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt.
 251     SBIT(EX1, 0xA8, 2); // Enable External Interrupt INT1.
 252     SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt.
 253     SBIT(EX0, 0xA8, 0); // Enable External Interrupt INT0.
 254
 255
 256 SFR(WDRST, 0xA6);   // Watchdog Timer Reset Counter Register.
 257 SFR(WDKEY, 0xAE);   //Watchdog Timer Key Register.
 258
 259 SFR(P3, 0xB0); // Port 3
 260     SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
 261     SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
 262     SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
 263     SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
 264     SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
 265     SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
 266     SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
 267     SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
 268
 269 SFR(IPA, 0xB7); // Interrupt Priority Addition register.
 270     #define PDDC 0x80 // DDC Interrupt priority level.
 271     #define PS1  0x10 // UART1 Interrupt priority.
 272     #define PI2C 0x02 // I2C Interrupt priority level.
 273     #define PUSB 0x01 // USB Interrupt priority level.
 274
 275 SFR(IP, 0xB8);  // Interrupt Priority Register.
 276     SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt priority level.
 277     SBIT(PS0, 0xB8, 4); // UART0 Interrupt priority level.
 278     SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt priority level.
 279     SBIT(PX1, 0xB8, 2); // External Interrupt INT1 priority level.
 280     SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt priority level.
 281     SBIT(PX0, 0xB8, 0); // External Interrupt INT0 priority level.
 282
 283 SFR(P4, 0xC0); // I/O Port 4 Register
 284     SBIT(P4_0, 0xC0, 0); // Port 4 bit 0.
 285     SBIT(P4_1, 0xC0, 1); // Port 4 bit 1.
 286     SBIT(P4_2, 0xC0, 2); // Port 4 bit 2.
 287     SBIT(P4_3, 0xC0, 3); // Port 4 bit 3.
 288     SBIT(P4_4, 0xC0, 4); // Port 4 bit 4.
 289     SBIT(P4_5, 0xC0, 5); // Port 4 bit 5.
 290     SBIT(P4_6, 0xC0, 6); // Port 4 bit 6.
 291     SBIT(P4_7, 0xC0, 7); // Port 4 bit 7.
 292
 293
 294 SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
 295     SBIT(TF2,   0xC8, 7); // Timer 2 overflow flag.
 296     SBIT(EXF2,  0xC8, 6); // Timer 2 external flag.
 297     SBIT(RCLK,  0xC8, 5); // Receive clock flag.
 298     SBIT(TCLK,  0xC8, 4); // Transmit clock flag.
 299     SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
 300     SBIT(TR2,   0xC8, 2); // Start/stop control for timer 2.
 301     SBIT(CNT2,  0xC8, 1); // Timer or coutner select.
 302     SBIT(CAP2,  0xC8, 0); // Capture/reload flag.
 303
 304 SFR(T2MOD, 0xC9); // Timer / Counter 2 Mode
 305    #define DCEN   0x01   // DC Enable
 306
 307 SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
 308 SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
 309 SFR(TL2,    0xCC); // Timer 2 LSB.
 310 SFR(TH2,    0xCD); // Timer 2 MSB.
 311
 312 SFR(PSW, 0xD0); // Program Status Word.
 313     SBIT(CY,  0xD0, 7); // Carry Flag.
 314     SBIT(AC,  0xD0, 6); // Auxiliary Carry Flag.
 315     SBIT(F0,  0xD0, 5); // User-Defined Flag.
 316     SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
 317     SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
 318     SBIT(OV,  0xD0, 2); // Overflow Flag.
 319     SBIT(P,   0xD0, 0); // Parity Flag.
 320
 321 SFR(S1SETUP, 0xD1); // I2C START Condition Sample Setup register.
 322     #define EN_SS     0x80 // Enable Sample Setup.
 323     #define SMPL_SET6 0x40 // Sample Setting bit 7.
 324     #define SMPL_SET5 0x20 // Sample Setting bit 6.
 325     #define SMPL_SET4 0x10 // Sample Setting bit 5.
 326     #define SMPL_SET3 0x08 // Sample Setting bit 4.
 327     #define SMPL_SET2 0x04 // Sample Setting bit 3.
 328     #define SMPL_SET1 0x02 // Sample Setting bit 2.
 329     #define SMPL_SET0 0x01 // Sample Setting bit 1.
 330
 331 SFR(S2SETUP, 0xD2); // I2C (S2) SETUP
 332 SFR(RAMBUF,  0xD4); // DDC Ram Buffer
 333 SFR(DDCDAT,  0xD5); // DDC (I2C) data xmit register
 334 SFR(DDCADR,  0xD6); // DDC (I2C) address pointer register
 335 SFR(DDCCON,  0xD7); // DDC Control Register
 336    #define EX_DAT 0x40
 337    #define SWENB  0x20
 338    #define DDC_AX 0x10
 339    #define DDCINT 0x08
 340    #define DDC1EN 0x04
 341    #define SWHINT 0x02
 342    #define M0     0x01
 343
 344 SFR(S1CON, 0xD8); // I2C Interface Control Register.
 345 SFR(S2CON, 0xDC); // I2C Interface Control Register.
 346     #define CR2  0x80 // SCL clock frequency select bit 3.
 347     #define ENI1 0x40 // I2C Interface Enable.
 348     #define STA  0x20 // START flag.
 349     #define STO  0x10 // STOP flag.
 350     #define ADDR 0x08 // Slave mode address.
 351     #define AA   0x04 // Assert Acknowledge enable.
 352     #define CR1  0x02 // SCL clock frequency select bit 2.
 353     #define CR0  0x01 // SCL clock frequency select bit 1.
 354
 355 SFR(S1STA, 0xD9); // I2C Interface Status Register.
 356 SFR(S2STA, 0xDD); // I2C Interface Status Register.
 357     #define GC       0x80 // General Call flag.
 358     #define STOP     0x40 // STOP flag.
 359     #define INTR     0x20 // Interrupt flag.
 360     #define TX_MODE  0x10 // Transmission Mode flag.
 361     #define BBUSY    0x08 // Bus Busy flag.
 362     #define BLOST    0x04 // Bus Lost flag.
 363     #define ACK_RESP 0x02 // Not Acknowledge Response flag.
 364     #define SLV      0x01 // Slave Mode flag.
 365
 366 SFR(S1DAT, 0xDA); // I2C Data Shift Register.
 367 SFR(S1ADR, 0xDB); // I2C Address Register (bit 0 not used).
 368 SFR(S2DAT, 0xDE); // I2C Data Shift Register.
 369 SFR(S2ADR, 0xDF); // I2C Address Register (bit 0 not used).
 370
 371 SFR(A, 0xE0);
 372 SFR(ACC, 0xE0); // Accumulator
 373     SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
 374     SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
 375     SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
 376     SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
 377     SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
 378     SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
 379     SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
 380     SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
 381
 382 /*
 383  The USB function are described in the datasheet page 83 and further.
 384  Further notes can be found in application note AN1877 Rev.1 page 37 up; downloadable from ST.Com
 385  */
 386 SFR(USCL, 0xE1);  // USB Prescaler
 387
 388 SFR(UDT1,  0xE6); // USB Endpt1 Data Xmit
 389 SFR(UDT0,  0xE7); // USB Endpt0 Data Xmit
 390 SFR(UISTA, 0xE8); // USB Interrupt Status
 391    #define SUSPND 0x80
 392    #define RSTF   0x20
 393    #define TXD0F  0x10
 394    #define RXD0F  0x08
 395    #define RXD1F  0x04
 396    #define EOPF   0x02
 397    #define RESUMF 0x01
 398
 399 SFR(UIEN, 0xE9); // USB Interrupt Enable
 400    #define SUSPNDIE  0x80
 401    #define RSTE      0x40
 402    #define RSTFIE    0x20
 403    #define TXD0IE    0x10
 404    #define RXD0IE    0x08
 405    #define TXD1IE    0x04
 406    #define EOPIE     0x02
 407    #define RESUMIE   0x01
 408
 409 SFR(UCON0, 0xEA); // USB Endpt0 Xmit Control
 410    #define TSEQ0     0x80
 411    #define STALL0    0x40
 412    #define TX0E      0x20
 413    #define RX0E      0x10
 414    #define TP0SIZ3   0x08
 415    #define TP0SIZ2   0x04
 416    #define TP0SIZ1   0x02
 417    #define TP0SIZ0   0x01
 418
 419 SFR(UCON1, 0xEB);  // USB Endpt1 Xmit Control
 420    #define TSEQ1     0x80
 421    #define EP12SEL   0x40
 422    #define FRESUM    0x10
 423    #define TP1SIZ3   0x08
 424    #define TP1SIZ2   0x04
 425    #define TP1SIZ1   0x02
 426    #define TP1SIZ0   0x01
 427
 428 SFR(UCON2, 0xEC );  // USB Control Register
 429    #define SOUT      0x10
 430    #define EP2E      0x08
 431    #define EP1E      0x04
 432    #define STALL2    0x02
 433    #define STALL1    0x01
 434
 435 SFR(USTA, 0xED); // USB Endpt0 Status
 436    #define RSEQ      0x80
 437    #define SETUP     0x40
 438    #define IN        0x20
 439    #define OUT       0x10
 440    #define RP0SIZ3   0x08
 441    #define RP0SIZ2   0x04
 442    #define RP0SIZ1   0x02
 443    #define RP0SIZ0   0x01
 444
 445 SFR(UADR, 0xEE); // USB Address Register
 446    #define USBEN     0x80
 447
 448 SFR(UDR0, 0xEF); // USB Endpt0 Data Recv
 449
 450 SFR(B, 0xF0); // B Register
 451     SBIT(B_0, 0xF0, 0); // Register B bit 0.
 452     SBIT(B_1, 0xF0, 1); // Register B bit 1.
 453     SBIT(B_2, 0xF0, 2); // Register B bit 2.
 454     SBIT(B_3, 0xF0, 3); // Register B bit 3.
 455     SBIT(B_4, 0xF0, 4); // Register B bit 4.
 456     SBIT(B_5, 0xF0, 5); // Register B bit 5.
 457     SBIT(B_6, 0xF0, 6); // Register B bit 6.
 458     SBIT(B_7, 0xF0, 7); // Register B bit 7.
 459
 460
 461 // PSD registers definition - by Jan Waclawek - wek at efton dot sk - May 2007
 462 // all defines here are with PSD_ prefix to identify them as PSD-related
 463 //
 464 // Based on uPSD33xx datasheet (preliminary) - Jan 2005, Table 79 at pages 145/146
 465 // and subsequent text
 466 // Based on uPSD3254A datasheet Rev.4 - 4 Nov 2004, Table 84 at page 99
 467 // and subsequent text
 468
 469 // requires to have PSD_CSIOP defined to the base address of the PSD IO area,
 470 //     as defined in PSDSoftExpress or CUPS
 471 #ifndef PSD_CSIOP
 472 #error PSD_CSIOP has to be #define-d (before #include-ing this file) to the base address of the PSD registers area, according to csiop setting in CUPS/PSDSoftExpress
 473 #else
 474                                          //  -- Port A not available on 52-pin uPSD33xx devices
 475 SFRX(PSD_DATAIN_A,    PSD_CSIOP+0x00);   // MCU I/O Mode Port A Data In Register
 476                                          //   reads 0 if pin is log.0, 1 if pin is log. 1
 477                                          //   READ only
 478 SFRX(PSD_DATAOUT_A,   PSD_CSIOP+0x04);   // MCU I/O Mode Port A Data Out Register
 479                                          //   write 0 to set pin to log. 0, 1 to set pin to log. 1
 480                                          //   read back written value
 481                                          //   reset default = 00
 482 SFRX(PSD_DIRECTION_A, PSD_CSIOP+0x06);   // MCU I/O Mode Port A Direction Register
 483                                          //   write 1 to set pin as output, 0 to set pin as input
 484                                          //   read back written value
 485                                          //   reset default = 00
 486 SFRX(PSD_DRIVE_A,     PSD_CSIOP+0x08);   // Select Open Drain or High Slew Rate for port A
 487                                          //   PA0-PA3: write 0 to select standard push-pull CMOS output, 1 to select High Slew Rate push-pull CMOS output
 488                                          //   PA4-PA7: write 0 to select standard push-pull CMOS output, 1 to select Open Drain output
 489                                          //   reset default = 00
 490 SFRX(PSD_CONTROL_A,   PSD_CSIOP+0x02);   // Selects MCU I/O or Latched Address Out mode for port A
 491                                          //   write 0 to select standard I/O pin, 1 to drive demultiplexed address signal on pin
 492                                          //   read back written value
 493                                          //   reset default = 00
 494 SFRX(PSD_OUTENABLE_A, PSD_CSIOP+0x0C);   // Read state of Output Enable Logic on each I/O port driver of Port A
 495                                          //   1 - driver output is enabled, 0 - driver is off (high impedance)
 496                                          //   READ only
 497
 498                                          // -- for comment on individual registers, see above Port A
 499 SFRX(PSD_DATAIN_B,    PSD_CSIOP+0x01);   // MCU I/O Mode Port B Data In Register
 500 SFRX(PSD_DATAOUT_B,   PSD_CSIOP+0x05);   // MCU I/O Mode Port B Data Out Register
 501 SFRX(PSD_DIRECTION_B, PSD_CSIOP+0x07);   // MCU I/O Mode Port B Direction Register
 502 SFRX(PSD_DRIVE_B,     PSD_CSIOP+0x09);   // Select Open Drain or High Slew Rate for port B
 503                                          // PB0-PB3: standard/High Slew Rate, PB4-PB7: standard/Open Drain
 504 SFRX(PSD_CONTROL_B,   PSD_CSIOP+0x03);   // Selects MCU I/O or Latched Address Out mode for port B
 505 SFRX(PSD_OUTENABLE_B, PSD_CSIOP+0x0D);   // Read state of Output Enable Logic on each I/O port driver of Port B
 506
 507                                          // -- for comment on individual registers, see above Port A
 508                                          // only pins PC2, PC3, PC4, PC7 available; other bits in registers are undefined
 509 SFRX(PSD_DATAIN_C,    PSD_CSIOP+0x10);   // MCU I/O Mode Port C Data In Register
 510 SFRX(PSD_DATAOUT_C,   PSD_CSIOP+0x12);   // MCU I/O Mode Port C Data Out Register
 511 SFRX(PSD_DIRECTION_C, PSD_CSIOP+0x14);   // MCU I/O Mode Port C Direction Register
 512 SFRX(PSD_DRIVE_C,     PSD_CSIOP+0x16);   // Select Open Drain for port C
 513 SFRX(PSD_OUTENABLE_C, PSD_CSIOP+0x1A);   // Read state of Output Enable Logic on each I/O port driver of Port C
 514
 515                                          // -- for comment on individual registers, see above Port A
 516                                          // only pins PD1, PD2 available (PD2 not available on 52-pin package); other bits in registers are undefined
 517 SFRX(PSD_DATAIN_D,    PSD_CSIOP+0x11);   // MCU I/O Mode Port D Data In Register
 518 SFRX(PSD_DATAOUT_D,   PSD_CSIOP+0x13);   // MCU I/O Mode Port D Data Out Register
 519 SFRX(PSD_DIRECTION_D, PSD_CSIOP+0x15);   // MCU I/O Mode Port D Direction Register
 520 SFRX(PSD_DRIVE_D,     PSD_CSIOP+0x17);   // Select High Slew Rate for port D
 521 SFRX(PSD_OUTENABLE_D, PSD_CSIOP+0x1B);   // Read state of Output Enable Logic on each I/O port driver of Port D
 522
 523 SFRX(PSD_IMC_A,       PSD_CSIOP+0x0A);   // Read to obtain logic state of Input Macrocells connected to Port A
 524                                          //   READ only
 525 SFRX(PSD_IMC_B,       PSD_CSIOP+0x0B);   // Read to obtain logic state of Input Macrocells connected to Port B
 526 SFRX(PSD_IMC_C,       PSD_CSIOP+0x18);   // Read to obtain logic state of Input Macrocells connected to Port C
 527                                          //   only pins PC2, PC3, PC4, PC7 available; other bits in register are undefined
 528 SFRX(PSD_OMC_AB,      PSD_CSIOP+0x20);   // Read logic state of macrocells AB. Write to load macrocell AB flip-flops.
 529 SFRX(PSD_OMC_BC,      PSD_CSIOP+0x21);   // Read logic state of macrocells BC. Write to load macrocell BC flip-flops.
 530 SFRX(PSD_OMCMASK_AB,  PSD_CSIOP+0x22);   // Write to set mask for macrocell AB.
 531                                          //    1 blocks READs/WRITEs of OMF, 0 will pass OMF value
 532                                          //    Read back written value.
 533 SFRX(PSD_OMCMASK_BC,  PSD_CSIOP+0x23);   // Write to set mask for macrocell BC.
 534
 535 // -- all three Power Management Register are set to 00 after PowerUp, but unchanged during reset (/RST)
 536 SFRX(PSD_PMMR0,       PSD_CSIOP+0xB0);   // -- Power Management Register 0 - write/read
 537 // bit 0 unused and should be set to 0
 538 #define PSD_APD_ENA            0x02      // 0 - Automatic Power Down (APD) counter is disabled, 1 - APD enabled
 539 // bit 2 unused and should be set to 0
 540 #define PSD_TURBO_DISA         0x08      // 0 - PSD Turbo mode enabled, 1 - Turbo mode off, saving power
 541 #define PSD_BLOCK_CLKIN_PLD    0x10      // 0 - CLKIN to PLD not blocked, 1 - no CLKIN to PLD Input Bus, saving power
 542 #define PSD_BLOCK_CLKIN_OMC    0x20      // 0 - CLKIN to Output Macrocells not blocked, 1 - blocked, saving power
 543 // bits 6 and 7 unused and should be set to 0
 544
 545 SFRX(PSD_PMMR2,       PSD_CSIOP+0xB4);   // -- Power Management Register 2 - write/read
 546 // bits 0 and 1 unused and should be set to 0
 547 #define PSD_BLOCK_WR_PLD       0x04      // 0 - /WR from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
 548 #define PSD_BLOCK_RD_PLD       0x08      // 0 - /RD from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
 549 #define PSD_BLOCK_PSEN_PLD     0x10      // 0 - /PSEN from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
 550 #define PSD_BLOCK_ALE_PLD      0x20      // 0 - ALE from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
 551 #define PSD_BLOCK_PC7_PDL      0x40      // 0 - input from Port C pin 7 to PLD Input Bus not blocked, 1 - blocked, saving power
 552 // bit 7 unused and should be set to 0
 553
 554 SFRX(PSD_PMMR3,       PSD_CSIOP+0xC7);   // -- Power Management Register 3 - write/read
 555 // bit 0 unused and should be set to 0
 556 #define PSD_FORCE_PD           0x02      // 0 - APD counter, if enabled, will cause powerdown, 1 - powerdown will be entered immediately
 557                                          //   - once set, cleared only by reset condition
 558 // bit 2 not defined by datasheet
 559 // bits 3 to 7 unused and should be set to 0
 560
 561 SFRX(PSD_MAINPROTECT, PSD_CSIOP+0xC0);   // -- Main Flash Memory Protection Definition
 562                                          //   bit 0 to bit 7 - sector 0 to sector 7 protection status
 563                                          //      - 1 - flash sector write protected, 0 - not write protected
 564                                          //   READ only
 565 SFRX(PSD_ALTPROTECT,  PSD_CSIOP+0xC2);   // -- Secondary Flash Memory Protection Definition
 566                                          //   bit 0 to bit 3 - sector 0 to sector 3 protection status
 567                                          //      - 1 - flash sector write protected, 0 - not write protected
 568                                          //   bit 7 - Security Bit
 569                                          //      - 1 - device is secured against external reading and writing, 0 - not secured
 570                                          //   READ only
 571
 572 SFRX(PSD_PAGE,        PSD_CSIOP+0xE0);   // -- Memory Page Register
 573
 574 SFRX(PSD_VM,          PSD_CSIOP+0xE2);   // -- Memory Mapping Register
 575                                          //   Places PSD Module memories into 8032 Program Address Space
 576                                          //   and/or 8032 XDATA Address Space
 577                                          //   Default value of bits 0 to 4 is loaded from Non-Volatile
 578                                          //   setting as specified from PSDsoft Express upon any reset
 579                                          //   or power-up condition. The default value of these bits
 580                                          //   can be overridden by 8032 at run-time.
 581 #define PSD_VM_SRAM_CODE       0x01      // 0 - SRAM not accessible as CODE (/PSEN) memory, 1 - SRAM accessible as CODE memory
 582 #define PSD_VM_ALT_CODE        0x02      // 0 - secondary FLASH not accessible as CODE (/PSEN) memory, 1 - secondary FLASH accessible as CODE memory
 583 #define PSD_VM_MAIN_CODE       0x04      // 0 - primary FLASH not accessible as CODE (/PSEN) memory, 1 - primary FLASH accessible as CODE memory
 584 #define PSD_VM_ALT_XDATA       0x08      // 0 - secondary FLASH not accessible as XDATA (/RD/WR) memory, 1 - secondary FLASH accessible as XDATA memory
 585 #define PSD_VM_MAIN_XDATA      0x10      // 0 - primary FLASH not accessible as XDATA (/RD/WR) memory, 1 - primary FLASH accessible as XDATA memory
 586 // bits 5 and 6 unused
 587 #define PSD_VM_PIO_EN          0x80      // 0 - disable, 1- enable peripheral I/O mode on Port A
 588
 589 // another terminology for FLASH - MAIN/ALTERNATIVE -> PRIMARY/SECONDARY
 590 #define PSD_VM_PRI_CODE   PSD_VM_MAIN_CODE
 591 #define PSD_VM_SEC_CODE   PSD_VM_ALT_CODE
 592 #define PSD_VM_PRI_XDATA  PSD_VM_MAIN_XDATA
 593 #define PSD_VM_SEC_XDATA  PSD_VM_ALT_XDATA
 594
 595 #endif
 596
 597 #endif //REG_UPSD32XX_H